In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit — (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using 0.18 μm Bipolar-CMOS–DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.
Semiconductor process technologies have been developed to further miniaturize integrated circuits (ICs). However, in ICs, circuit failures due to electrostatic discharge (ESD) is a serious problem. Thus, along with an increase in the demand for analog and high-voltage IC technologies, ESD protection circuits have come to be regarded as ever more important to ensure the reliability of ICs
Since high-voltage ICs are commonly used in ESD protection circuits, the demand for such ICs for high-voltage applications, such as automotive analog driver ICs, power management ICs, inverters, power distribution systems, and light-emitting diode (LED) driver ICs, has sharply increased.
MOSFET-based devices, such as a silicon controlled rectifier (SCR) or a bipolar junction transistor (BJT), are commonly used in high-voltage ESD protection circuits, as are switching devices and output drivers
An SCR-based ESD protection circuit can effectively discharge an ESD surge; this is due to the fact that such a circuit has a high current-driving capacity compared to its area, due to the positive feedback structure of parasitic NPN/PNP bipolar transistors within the circuit’s silicon substrate. However, parasitic NPN/PNP BJTs are susceptible to
in high-voltage applications, because they have a low holding voltage of about 2 V as a turn-on voltage
In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. A circuit having the proposed new structure is fabricated by using a 0.18 μm Bipolar-CMOS–DMOS (BCD) process, and its electrical characteristics and robustness are evaluated.
II. Proposed ESD Protection Circuit
- 1. HHVSCR and AHHVSCR ESD Protection Circuits
show the respective cross-sections of a high holding voltage SCR (HHVSCR) ESD protection circuit and an AHHVSCR ESD protection circuit.
shows an equivalent circuit.
shows a cross-section of an HHVSCR, in which an ESD protection circuit is created by inserting a P+ (P-drift) cathode junction that passes through both N-well regions and the P-well region. The P+ (P-drift) cathode junction assists in reducing the trigger voltage; yet, at the same time, it also performs the function of increasing the holding voltage (as does the cathode N-well). The operating principle of the HHVSCR ESD protection circuit is as follows. An ESD surge is applied to the anode, thus increasing the potential energy in the anode N-well. The anode N-well together with the P+ (P-drift) cathode junction create a state of reverse bias, which increases the potential energy in the anode N-well. The P+ (P-drift) cathode junction experiences an
due to the high electric field between the anode N-well and the P+ (P-drift) cathode junction.
(a) Cross-section of HHVSCR ESD protection circuit, (b) cross-section of AHHVSCR ESD protection circuit, and (c) equivalent circuit.
Electron–hole pairs (EHPs) will be generated by the avalanche breakdown, and the current from the holes moves to the P-well region; the potential energy of this region exceeds the internal electric field for the P-well and N-well junction, for which the junction becomes a forward bias. The parasitic NPN BJT Q3 is turned on. Once it is turned on, the current at Q3 causes a voltage drop at the internal resistance of the anode N-well. The parasitic PNP BJTs Q1 and Q2 are also turned on. The voltage at the anode no longer needs to provide a bias for Q1, and the tuning for the holding voltage is accomplished by adjusting the length of the P+ (P-drift) cathode junction
shows a cross-section of an AHHVSCR, in which the ESD protection circuit is removed after the insertion of the P+ (P-drift) cathode junction between the cathode N-well and P-well, inducing an avalanche breakdown. In addition, an N+ floating diffusion region was inserted into the anode N-well. The N+ floating diffusion region ensures a low current gain for the parasitic BJTs Q1, Q2, and Q3. Thus, further bias is needed at the parasitic PNP BJTs to maintain their operation. However, this results in a high holding voltage.
The operating principle of the AHHVSCR ESD protection circuit when an ESD surge is applied is as follows. When an ESD surge comes from the anode, the anode N-well together with the P+ (P-well) cathode junction create a state of reverse bias, which increase the potential energy in the anode N-well. Then, when the increasing potential energy reaches a critical value, an avalanche breakdown occurs between the anode N-well and the P+ (P-drift) cathode junction. Due to the EHPs created by the avalanche breakdown, the current generated by the holes flows to the anode N+ diffusion region through the N+ floating diffusion region, which now has a low resistance due to the high doping density inside the anode N-well. It then continues to flow to the P+ (P-drift) cathode junction inside of the P-well. When the difference between the potential energy of the P-well (which has increased due to the current generated by the holes) and the potential energy of the right N-well junction becomes greater than the built-in potential energy of the well junction and these two junctions are biased in the forward direction, the parasitic NPN BJT Q3 turns on. When the parasitic NPN BJT Q3 turns on, the current at Q3 causes a voltage drop through the internal resistance of the anode N-well and the parasitic PNP BJTs Q1 and Q2. Thus, the currents at the parasitic PNP BJTs Q1 and Q2 cause a voltage drop due to the internal resistance of the P-well, which maintains the “turn-on” state of the parasitic NPN BJT Q3.
When the total resistance of an SCR in either an HHVSCR or AHHVSCR is increased to raise the holding voltage, the robustness drops relatively.
- 2. Proposed ESD Protection Circuit and Simulation Results
A cross-sectional view of the proposed new structure for an AHHVSCR and the equivalent schematic is shown in
. The proposed new structure contains an additional parasitic PNP BJT (Q4), which is achieved by adding a gate and a cathode P+ diffusion region. The proposed new structure (that is, the
) is highly robust due to the addition of this parasitic PNP BJT.
(a) Cross-section of proposed circuit and (b) equivalent circuit.
The operating mechanism of the proposed circuit is as follows. When the anode voltage increases through an ESD surge, the potential energy of the anode N+ diffusion region and the anode N-well increases. As the anode voltage increases, the junction between the anode N-well and the P-well is
until it goes into an avalanche breakdown.
After the creation of EHPs, the current generated by the holes flows into the P+ (P-drift) floating diffusion region, and the current generated by the electrons flows into the anode N+ diffusion region through the anode N-well. When the potential energy between the anode N-well and the anode P+ diffusion region reaches about 0.7 V, the junction that lies between them is
and parasitic PNP BJTs Q1 and Q2 are turned on. When the PNP BJTs Q1 and Q2 are turned on, the floating N+ diffusion region reduces the current gain of the PNP BJT Q2, because it increases the recombination rate. The current through Q1 flows into the cathode N+ diffusion region, and the current through Q2 flows into the P-drift diffusion region. When the junction between the P-well and the cathode N-well is forward-biased by the currents passing through Q1 and Q2, the NPN BJT Q3 turns on. In addition, the current through Q3 turns the PNP BJT Q4 on.
The electrical characteristics, including the breakdown voltage, trigger voltage, and holding voltage, are analyzed by setting design variables
). Design variable
1 is the distance between the anode N-well and the P-well, which is related to the trigger voltage. Design variable
2 is the length of the floating N+ diffusion region, which is related to the holding voltage, and design variable
3 is the length of the P-well, which is the base width of the parasitic NPN BJT Q3 and is related to the holding voltage. In addition, the P-well is heavily doped to obtain a higher robustness characteristic on which to add the P-body-resistance.
shows the simulated structure of the proposed circuit. The simulated structure for ESD protection is designed with TSUPREM4 of SYNOPSYS, and the electrical characteristics are analyzed using MEDICI.
Simulated structure of proposed circuit.
show the total current flow for the proposed circuit.
is the state before the triggering of the proposed circuit. As shown in the figure, most currents are shown to be between the anode N-well and the P+ (P-drift) diffusion region. In addition, there is a leakage current between the anode N-well and P-well.
shows the current flow for the trigger condition of the proposed circuit.
is an example of the kind of current flow that can occur immediately after the passing of a discharge current through the proposed circuit. From this figure, we can see that all the internal parasitic BJTs of the SCR are activated, discharging the ESD current from the anode to the cathode.
Current flow lines through proposed circuit.
The AHHVSCR-based ESD protection circuit having the proposed new structure, a standard AHHVSCR-based ESD protection circuit, and a standard HHVSCR-based ESD protection circuit are compared by way of a TACD simulation.
shows a graph of the lattice temperature over time after the application of 2 kV HBM. As a result of the TACD simulation, in the process of discharging the ESD surge after the application of 2 kV HBM, the lattice temperature of the proposed circuit is 321 K, which is lower than the lattice temperature of 380 K for the standard AHHVSCR-based ESD protection circuit and 365 K for the standard HHVSCR-based ESD protection circuit. This result is closely related to the robustness of ESD, and it confirms that the robustness of the proposed circuit is higher than that of the other two considered circuits.
TCAD simulation results of AHHVSCR-based ESD protection circuit having proposed new structure, standard AHHVSCR-based ESD protection circuit, and standard HHVSCR-based ESD protection circuit.
The electrical characteristics, such as trigger voltage and holding voltage, can be optimized by adjusting the design variables
shows the TCAD simulation results obtained through varying only
1. This distance is responsible for increases in the trigger voltage (17.89 V, 23.71 V, and 33.73 V); the holding voltage is kept constant at 2.9 V. We note that it is the design variable
1 that is the dominant factor here, as it is this which affects the avalanche breakdown voltage.
shows the simulation characteristics for
shows the TCAD simulation results obtained through varying
3. The design variable
2 is related to the holding voltage;
3 is related to the length of the P-well, which is the base width of the parasitic NPN BJT Q3 and is also related to the holding voltage. As the N+ floating and P+ (P-drift) floating diffusion regions increase in length, the trigger voltage increases accordingly from 17.89 V to 19.44 V, and the holding voltage increases from 2.92 V to 5.7 V, respectively.
presents the simulation characteristics for
Simulated characteristics for design variableD1.
|Design variables (D1) ||Breakdown voltage ||Trigger voltage ||Holding voltage |
|0 μm ||13.1 V ||17.89 V ||2.92 V |
|0.5 μm ||16.1 V ||23.71 V ||2.90 V |
|1.0 μm ||26.0 V ||33.73 V ||2.92 V |
Simulated I-V curve characteristic of design variable D1.
Simulated I-V curve characteristic of design variables D2 and D3.
Simulated characteristics ofD2 andD3 design variables.
|Design variables (D1) ||Breakdown voltage ||Trigger voltage ||Holding voltage |
|2 μm, 4 μm ||13.1 V ||17.89 V ||2.92 V |
|4 μm, 6 μm ||13.1 V ||18.91 V ||3.89 V |
|6 μm, 8 μm ||13.1 V ||19.44 V ||5.7 V |
- 3. Transmission Line Pulse Characteristics of Proposed Circuit
The electrical characteristics of the proposed circuit are obtained by first considering transmission line pulse (TLP) measurements. Before the proposed circuit is designed, an ESD protection design window is determined in accordance with the proposed circuit’s internal core circuit. Within this given window, possible ESD protection circuits are considered through an examination of the TLP measurements.
The TLP measurement method is the most widely used method to analyze the electrical characteristics of ESD protection circuits
shows the TLP system. The operation mechanism of the TLP measurement system is as follows. A rectangular current pulse with a pulse width of 100 ns is applied to the device under test (DUT), and the current flowing through the DUT and the voltage across the DUT is recorded on a digital oscilloscope. A pulse response curve across the DUT is obtained after extraction of both the preconfigured voltage and the leakage current.
TLP test system.
The layouts of the three considered circuits are based on 0.18 μm BCD technologies, as shown in
. A comparison of the three considered circuits is shown in
in terms of the TLP
characteristics, which reveals a 10.54 V increase (from 13.21 V to 23.75 V) in the trigger voltage as well as an 8.46 V increase (from 9.97 V to 18.43 V) in the holding voltage. The standard AHHVSCR-based and HHVSCR-based ESD protection circuits operate in latch mode with two PNP BJTs and one NPN BJT. On the other hand, the proposed circuit operates with four BJTs — it has an additional PNP BJT. Therefore, the comparison shows a 2.36 A increase (from 2.87 A to 5.23 A) for the second breakdown current (
), achieved by the addition of the proposed new structure, which has a small area of 4,465 μm
presents the TLP characteristics for
(a) Layouts of three considered circuits and (b) TLP I-V curve characteristics.
Resulting TLP characteristics of three considered circuits.
|ESD protection circuit ||Trigger voltage ||Holding voltage ||Second breakdown current |
|HHVSCR ||13.21 V ||9.97 V ||2.87 A |
|AHHVSCR ||25.72 V ||18.13 V ||3.08 A |
|Proposed circuit ||23.75 V ||18.43 V ||5.23 A |
shows the TLP
1 varies from 0.5 μm to 2 μm. The results of the measurements indicate that the trigger voltage increases from 25.62 V to 34.74 V, and the holding voltage increases from 18.49 V to 23.76 V. Therefore,
1 has a greater effect on the trigger voltage as opposed to the holding voltage. In addition, a high second breakdown current (
) can be observed at above 6 A.
presents the TLP characteristics seen in
Measured design variable D1 TLP I-V curve characteristics.
Resulting TLP characteristics of proposed circuit resulting fromD1 design variable.
|Design variables (D1) ||Breakdown voltage ||Trigger voltage ||Holding voltage |
|0.5 μm ||16.6 V ||25.62 V ||18.49 V |
|1.0 μm ||18.8 V ||28.57 V ||20.38 V |
|1.5 μm ||20.5 V ||31.53 V ||22.43 V |
|2.0 μm ||23.0 V ||34.74 V ||23.76 V |
shows the TLP
characteristics as the
2 length varies from 2 μm to 8 μm and the
3 length varies from 4 μm to 10 μm. The results of the measurements indicate that the trigger voltage increases from 22.56 V to 29.11 V and the holding voltage increases from 12.12 V to 28.03 V; the breakdown voltage remains at 16.6 V with no change as
4 increase. The trigger voltage increases with the holding voltage because more bias is needed to turn it on as the current gain decreases. Meanwhile, the second breakdown current decreases as
4 increase because the floating region causes an increase in the current density at the surface and degrades the current capability.
presents the TLP characteristics of
Measured design variables D2 and D3 TLP I-V curve characteristics.
Resulting TLP characteristics of proposed circuit resulting fromD2 andD3 design variables.
|Design variables (D2, D3) ||Trigger voltage ||Holding voltage ||Second breakdown current |
|2 μm, 4 μm ||22.56 V ||12.12 V ||8.40 A |
|4 μm, 6 μm ||24.56 V ||19.14 V ||5.83 A |
|6 μm, 8 μm ||27.05 V ||25.02 V ||3.78 A |
|8 μm, 10 μm ||29.11 V ||28.03 V ||2.41 A |
To properly design the proposed circuit for a high voltage application, researchers have used the P-body layer in the P-well. Without the P-body layer, the proposed circuit has a trigger voltage of 24.56 V, a holding voltage of 19.14 V, and a second breakdown current of 5.83 A. On the other hand, when a partial P-body layer is added to the P-well, the proposed circuit has a holding voltage of 18.78 V, a trigger voltage of 22.83 V, and a second breakdown current of 8.14 A. Both the trigger voltage and the second breakdown current are higher with the partial P-body layer than without the P-body layer. The trigger voltage, on-resistance, and second breakdown current characteristics are improved because the P-body layer using the P-well has a doping concentration that is higher than the number of carriers that are present, and because the resistance component decreases.
shows a comparison of the standard AHHVSCR-based ESD protection circuit, the proposed circuit, and the proposed circuit with P-body layer;
shows the TLP
presents the characteristics from
(a) Standard AHHVSCR-based ESD protection circuit, proposed circuit, and proposed circuit with P-body layer and (b) TLP I-V curve characteristics.
Resulting TLP characteristics of standard AHHVSCR-based ESD protection circuit, proposed circuit, and proposed circuit with P-body layer.
|ESD Protection ||Trigger voltage ||Holding voltage ||Second breakdown current |
|AHHVSCR ||25.76 V ||18.13 V ||3.08 A |
|Proposed circuit ||24.56 V ||19.14 V ||5.83 A |
|Proposed circuit + P-body ||22.83 V ||18.78 V ||8.14 A |
In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) was proposed. It is highly robust and has a holding voltage for a high-voltage I/O and power clamp application. The standard HHVSCR-based and AHHVSCR-based ESD protection circuits have a problem in that they exhibit a low current driving capability, due to the parasitic resistance resulting from the P-drift diffusion region and both N-wells. The proposed circuit improves the second breakdown current by forming an additional PNP BJT. The three considered circuits were fabricated using a 0.18 μm BCD process. The proposed circuit has a high second breakdown current of 5.23 A, whereas the standard AHHVSCR-based and HHVSCR-based ESD protection circuits have currents of 3.08 A and 2.87 A, respectively. The trigger voltage increases from 25.62 V to 34.71 V as the
1 design variable varies. In addition, the holding voltage increases from 12.12 V to 28.03 V as the
3 design variables vary. Furthermore, the proposed circuit is highly robust, and has an HBM measurement of 8 kV and machine model of 800 V, which are beyond the commercialization standards of 2 kV, 200 V, respectively. Therefore, the proposed circuit can be designed to suit multiple supply voltages as a design variable, which can improve the reliability of an IC, since it provides immunity to a state of latch-up and is highly robust.
The present research was conducted with the support of the research fund of Dankook University in 2016.
Bo Bae Song is currently working toward his PhD degree in electronic and electrical engineering at Dankook University, Yongin, Rep. of Korea. His research interests include power semiconductor devices and electrostatic discharge protection circuit design.
Corresponding Author firstname.lastname@example.org
Yong Seo Koo received his BS, MS, and PhD degrees in electronic engineering from Sogang University, Seoul, Rep. of Korea, in 1981, 1983, and 1992, respectively. He joined the Department of Electronics and Electrical Engineering, Dankook University, Yongin, Rep. of Korea, as a professor, in 2009. His research interests include power semiconductor devices, power management integrated circuits, and electrostatic discharge protection circuit design.
“Investigation and Design of on-Chip Power-Rail ESD Clamp Circuits without Suffering Latch up-Like Failure during System-Level ESD Test,”
IEEE J. Solid-State Circuits
DOI : 10.1109/JSSC.2008.2005451
“High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps,”
IEEE Trans. Device Mater. Rel.
DOI : 10.1109/TDMR.2004.826584
“High Holding Current SCRs (HHI-SCR) for ESD Protection and Latch-up Immune IC Operation,”
Charlotte, NC, USA
Oct. 6–10, 2002
“ESD Protection for High-Voltage CMOS Technologies,”
Anaheim, CA, USA
Sept. 10–15, 2006
“ESD Protection Solutions for High Voltage Technologies,”
Grapevine, TX, USA
Sept. 19–23, 2004
“A Study on the Novel SCR NANO ESD Protection Device Design and Fabrication,”
J. Institute Korean Electr. Electron. Eng.
“Design of SCR-Based ESD Protection Circuit for 3.3 V I/O and 20 V Power Clamp,”
DOI : 10.4218/etrij.15.0114.0730
“TLP Calibration, Correlation, Standards, and New Techniques [ESD Test],”
Anaheim, CA, USA
Sept. 26–28, 2000
“Obtaining TLP-like Information from an HBM Simulator,”
Anaheim, CA, USA
Sept. 16–21, 2007