In this paper, we investigate the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under different p-body implantation conditions (low and high). Also, design considerations for the TSBRs are discussed in this paper. The TSBRs’ electrical properties depend strongly on their respective p-body implantation conditions. In the case of the TSBR with a low p-body implantation condition, it exhibits MOSFET-like properties, such as a low forward voltage ( V _F ) drop, high reverse leakage current, and a low peak reverse recovery current owing to a majority carrier operation. However, in the case of the TSBR with a high p-body implantation condition, it exhibits pn junction diode–like properties, such as a high V _F , low reverse leakage current, and high peak reverse recovery current owing to a minority carrier operation. As a result, the TSBR with a low p-body implantation condition is capable of operating as a MOSFET, and the TSBR with a high p-body implantation condition is capable of operating as either a pn junction diode or a MOSFET, but not both at the same time. With the rapidly increasing demands pertaining to high-voltage applications in modern power electronic systems, such as automotive, power management integration circuit (PMIC), and power distribution applications, power devices (for example, rectifiers, MOSFETs, and IGBTs) have become widely used in today’s power applications. A power rectifier (power diode) with improved performance is considered a major device in modern power applications. For an improved performance of the power application, a power rectifier needs the following requirements: a low forward voltage drop ( V _F ), low on-resistance ( R _ON ), low reverse leakage current, fast switching speed ( t _rr ), high reverse breakdown voltage, and high temperature reliability [1] – [4] . In general, two families of rectifiers (pn junction and Schottky) are widely used for power rectifiers. A pn (PIN) junction rectifier has several advantages, such as a low leakage current and high temperature stability, but has a slow t _rr and high V _F owing to a minority carrier operation and high built-in potential [5] – [11] . Moreover, in the case of a Schottky rectifier, it can achieve a high-speed operation and low V _F properties as owing to a majority carrier operation, but has a particularly high leakage current at high temperature. To resolve the problem of having two different families, the super-barrier rectifier (SBR) concept was introduced [1] , [2] , where a super barrier for a majority carrier operation is created without an unreliable Schottky contact ( Fig. 1 ). In an SBR device, the most important parts are the channel regions of the SBR itself; the doping concentration in the SBR’s channel can be adjusted to suit a desired performance. The SBR creates a majority barrier in the MOS channel under the gate oxide — the height of which can be adjusted by the channel doping concentration and channel length [8] . To make an SBR an effective rectifier, its channel has to be very short. The channel of a lateral-gate-type SBR can be shortened in several different ways — either through changing the device layout, the self-alignment process, and so on. However, the channel of a trench-gate-type SBR (TSBR) can only be adjusted in accordance with a p-body implantation condition. In addition, the TSBR must be operated in accordance with the electrical properties of either a pn junction diode or a Schottky diode, depending on the p-body channel doping condition. In this paper, we will discuss considerations for the design of a p-body implantation condition with the help of some electrical results. We have successfully fabricated two TSBRs using a TCAD simulator. In particular, we focus on investigating the electrical properties of TSBRs under different p-body implantation conditions to see whether they exhibit either MOSFET-like or pn junction diode–like properties, or both. To determine the p-body channel doping concentration of our fabricated TSBRs, the built-in potential of a pn junction diode and threshold voltage of a MOSFET are analyzed using simple equations. In this paper, the built-in potential is taken to represent the forward voltage drop. The basic equations for the built-in potential of a pn junction diode and the threshold voltage of a MOSFET are as follows: where k , T , and q denote Boltzmann’s constant (8.62 × 10 ⁻⁵ eV/K), temperature, and electronic charge, respectively. In addition, N _a and N _d are the concentration of the acceptor and donor in the pn junction diode, respectively; n _i is the intrinsic carrier concentration (≈ 1.5 × 10 ¹⁰ ); Φ _ms is the metal and semiconductor work-function difference; Q _i and Q _d are the effective MOS interface charge per area (C/cm ² ) and the depletion region charge (C/cm ² ), respectively; C _i is the gate oxide capacitance; and ϕ _F is the Fermi-potential. Using (1) and (2), we can simulate results for both the built-in potential of a pn junction diode and the threshold voltage of a MOSFET for a given p-body implantation condition (see Fig. 2 ). In the case of the MOSFET, the values of t _ox , Φ _ms , and N _d are assumed to be 250Å-SiO ₂ , −0.95 eV, and 1.4 × 10 ¹⁶ , respectively. Generally, N _d is determined based on the epitaxial grown n -layer used to fabricate a power device (regardless of whether it is a MOSFET, TSBR, or pn junction diode). Based on the simulated results, the electrical properties of a TSBR with a given p-body implantation condition, such as the forward voltage drop and breakdown voltage, can be determined. When a TSBR has a p-body channel doping concentration of less than 4.5 × 10 ¹⁶ /cm ³ , V _TH as opposed to V _O better estimates its forward voltage drop. The opposite is true in the case of a TSBR having a p-body channel doping concentration greater than 4.5 × 10 ¹⁶ /cm ³ . In other words, when a forward bias exceeds the TSBR’s critical voltage, the TSBR is able to exhibit the properties of either a pn junction diode or a MOSFET, but not both at the same time. To confirm the variation in electrical characteristics with the change in p-body implantation condition, the breakdown voltage, leakage current, and forward conducting characteristics are investigated using a Synopsys TCAD simulator. The characteristics are investigated through simulating TSBR devices that are based on a 35 V SBR with an N-drift thickness and resistivity of 5.5 μm and 0.4 Ω·cm, respectively. Figure 3 shows the simulation results of two TSBRs — each with a trench gate of width 1 μm and depth 1.5 μm. The implant conditions of the TSBRs are 1E13/cm ² (red line) and 5E13/cm ² (blue line); the areas (device width) of the TSBRs are not taken into consideration. As shown in Fig. 3(a) , the TSBRs are designed based on a trench double-diffused MOSFET (TDMOS). However, the trench gate, source, and body regions are commonly connected at the anode electrode, which acts as an anode of the diode. A comparison of the p-body channel doping concentrations and channel depths is also shown in Fig. 3(b) . In the case of the TSBR with a p-body implantation condition of 1E13/cm ² , its p-body channel doping concentration is about 5E16/cm ³ and thus we can conclude that this TSBR exhibits operating characteristics similar to those of a MOSFET. On the other hand, in the case of the TSBR with a p-body implantation condition of 5E13/cm ² , its p-body channel doping concentration is about 2E17 cm ³ and thus we can conclude that this TSBR exhibits operating characteristics similar to those of a pn junction diode. The channel length of the TSBR with the lower p-body implantation condition (1E13/cm ² ) is shorter than that of the TSBR with the higher p-body implantation condition (5E13/cm ² ). Figure 4 shows the forward-conducting characteristics of both the 1 × 10 ¹³ /cm ² doped TSBR and the 5 × 10 ¹³ /cm ² doped TSBR, along with their respective current-flow line distributions for anode biases of 0.6 V and 1 V. As shown in Fig. 4(a) , the forward voltage drops of the 1 × 10 ¹³ /cm ² doped TSBR and the 5 × 10 ¹³ /cm ² doped TSBR are 0.3 V and 0.65 V, respectively, for an anode current of 1 × 10 ⁻⁶ A. In more detail, the I _Anode of the 1 × 10 ¹³ /cm ² doped TSBR can be separated into three parts: Regions 1 and 2 are the sub-threshold and linear regions indicative of a MOSFET. The last region (region 5) is a high-level injection and series-resistance region indicative of a pn junction diode. In the case of the 5 × 10 ¹³ /cm ² doped TSBR, the I _Anode is composed of the generation-recombination (region 3), the diffusion current (region 4), and the high-level injection and series-resistance (region 5) regions; namely, the 5 × 10 ¹³ /cm ² doped TSBR appears to have a conventional pn junction diode operation. Figures 4(b) and 4(c) depict the simulated forward-conducting characteristics of the 1 × 10 ¹³ /cm ² doped TSBR at V _Anode = 0.6 V and 1.0 V, respectively. As shown in Fig. 4(b) , at a forward voltage drop of 0.6 V, the 1 × 10 ¹³ /cm ² doped TSBR’s current flow is well controlled by the gate voltage, illustrating that this device appears to have a conventional MOSFET operation. However, in the case of Fig. 4(c) , the device appears to have a conventional pn junction diode operation at V _Anode = 1.0 V. The breakdown voltage for both TSBRs is the same (see Fig. 5 ), due to the fact that this is dependent upon the thickness and resistivity of each TSBR’s epitaxially grown silicon layer (drift region). However, the leakage current is very different in each case. The leakage current of the 5 × 10 ¹³ /cm ² doped TSBR is much smaller than that of the 1 × 10 ¹³ /cm ² doped TSBR. The 1 × 10 ¹³ /cm ² doped TSBR has a short channel, which causes a large leakage current between the anode and the cathode. On the other hand, the 5 × 10 ¹³ /cm ² doped TSBR has a stable leakage current performance. The leakage current performance is less sensitive to a “short-channel effect” in the case of the 5 × 10 ¹³ /cm ² doped TSBR. Figures 4 and 5 show that the electrical properties, such as the forward voltage drop, breakdown voltage, and leakage current, of the TSBRs is strongly dependent upon the p-body implantation condition. The TSBRs are designed based on a trench double-diffused MOSFET (TDMOS). To fabricate a 35 V rated TSBR, the thickness and resistivity of the top epitaxial layer need to be 5.5 μm and 0.4 Ω·cm, respectively, with the top layer grown on an N ⁺⁺ type handling wafer. The top layer defines the final active region of the TSBRs. The wafers are patterned to make a trench-gate-type gate region; consequently, the gate oxidation process forms an MOS capacitor that is equivalent in structure to a MOSFET. In addition, a doped poly-Si was deposited and etched back to the top layer surface, which functions in the same way as the material used to construct the gate of a MOSFET. The p-body and P ⁺ implantations were conducted and diffused using the same annealing process. To compare the variation in electrical properties of the TSBRs, p-body implantation conditions were verified. Fabrication processes, such as source implantation and front metallization, were applied. Finally, wafer thinning and back-side metallization processes were conducted to reduce the series resistance in the TSBRs. Unlike the three electrodes (drain, gate, and source) of a conventional trench power MOSFET, the electrodes of the developed TSBRs consist of an anode and a cathode, such as in a conventional diode. The gate and source terminal are commonly connected as an anode electrode. Figure 6 shows a cross-sectional SEM image of one of the fabricated TSBRs. Low-voltage electrical characteristics, such as V _F and breakdown voltage, were recorded with an Agilent 4156C semiconductor parameter analyzer. High-voltage electrical characteristics, such as the maximum current, were measured using a curve tracer (Tektronics). Moreover, the reverse recovery time ( T _rr ) in the fabricated TSBRs was measured using a standard test circuit (which is described in [12] ). Figure 7 shows linear scale plots of anode current against anode voltage in the cases of both room temperature (25 °C) and a high temperature (125 °C). In addition, simulated results in relation to the TSBRs’ channel width (about 1,000 μm) are shown in the insert of Fig. 8 . The simulated results are similar to the measured results. In the case of the 1 × 10 ¹³ /cm ² doped TSBR at room temperature, the properties of the anode current are typical of those exhibited by MOSFETs. The forward voltage is 0.36 V at an anode current of 0.1 A. At the high temperature (125 °C), the threshold voltage ( V _TH ) decreases and on-resistance increases. At room temperature, the 5 × 10 ¹³ /cm ² doped TSBR exhibits both MOSFET-like and pn junction diode–like properties; that is, the 5 × 10 ¹³ /cm ² doped TSBR has MOSFET-like properties at V _F < 0.65 V and pn junction diode–like properties at V _F > 0.65 V; the forward voltage is 1.046 V at an anode current of 0.1 A. When a TSBR has a p-body channel doping concentration of less than 4.5 × 10 ¹⁶ /cm ³ , V _TH as opposed to V _O better estimates its forward voltage drop. The opposite is true in the case of a TSBR having a p-body channel doping concentration greater than 4.5 × 10 ¹⁶ /cm ³ . In other words, when a forward bias exceeds the TSBR’s critical voltage, the TSBR is able to exhibit the properties of either a pn junction diode or a MOSFET, but not both at the same time. Moreover, the 5 × 10 ¹³ /cm ² doped TSBR has a lower current level compared to the 1 × 10 ¹³ /cm ² doped TSBR, owing to the high injection and serial resistance effects. In the case of the high temperature (125 °C), V _TH at a low current level and V ₀ at a high current level is reduced. As a result, the cross-over point (from MOSFET-like operation to pn junction diode–like operation) lies at an anode voltage of around 0.6 V. Comparing the simulation and measurement forward-conducting curves of the 5 × 10 ¹³ /cm ² doped TSBR, we can observe that the two curves differ (see Fig. 7 ). The measurement curve reveals that the TSBR operates both as a MOSFET and a pn junction diode, but not at the same time. In contrast, the simulation curves suggest that this TSBR should operate only in a manner similar to that of a pn junction diode. The 5 × 10 ¹³ /cm ² doped TSBR has a p-body channel doping concentration of 2E17/cm ³ in the simulation results of Fig. 3 ; however, in reality, it will have a lower p-body channel doping concentration. The fact that the 5 × 10 ¹³ /cm ² doped TSBR is able to exhibit both MOSFET-like and pn junction diode–like properties is also well reflected in the breakdown property. Figure 8 shows the breakdown voltage and reverse current for the two considered p-body implantation conditions. In the case of the 1 × 10 ¹³ /cm ² doped TSBR, the higher reverse leakage current and lower breakdown voltage properties are due to the TSBR’s short channel. In the case of a MOSFET with a short channel, the potential barrier between the source and channel decreases with an increase in the drain voltage, leading to drain-induced barrier lowering (DIBL). The generation of DIBL leads to a punch-through leakage and an early breakdown [13] . With an increase in the p-body implantation condition, however, the reverse leakage current decreases, because the MOSFET property of the TSBR is gradually diminished, whereas the pn junction diode property progressively dominates. The peak reverse recovery current, I _PR , and reverse recovery time, t _rr , in a power device, such as an IGBT, power MOSFET, power diode, and so on, are very important, especially when the switching devices (power devices) are turned off. These properties can be calculated based on the energy loss of the power device through the following equations: where E _OFF is the energy loss of the diode and V _bat is the battery voltage. In addition, Q _RR is the measured stored charge of the diode. Figure 9 shows the reverse recovery performance for the two considered P-body implantation condition. In the case of the 1 × 10 ¹³ /cm ² doped TSBR, t _rr and I _PR are 35.4 μs and −1.58 V, respectively. However, t _rr and I _PR in the case of the 5 × 10 ¹³ /cm ² doped TSBR are 35.4 μs and −1.8 V, respectively. Using (3), the calculated Q _RR of the 5 × 10 ¹³ /cm ² doped TSBR and 1 × 10 ¹³ /cm ² doped TSBR is 31.86 μC and 27.96 μC, respectively. Moreover, the E _OFF of the 5 × 10 ¹³ /cm ² doped TSBR ( E _OFF = 828 μJ) is higher than that of the 1 × 10 ¹³ /cm ² doped TSBR ( E _OFF = 727 μJ) based on (4). This is because the diode property of the 5 × 10 ¹³ /cm ² doped TSBR, when turned on, can increase the stored charge in the drift region, which creates a higher energy loss compared to when it is turned off. We investigated the variation of the electrical characteristics of two trench-gate-type super-barrier rectifiers (TSBRs) under various p-body implantation conditions (low and high). The forward voltage drop ( V _F ), reverse leakage (| I _Anode |), and reverse recovery properties of the TSBRs depend strongly on their respective p-body channel doping concentrations, as is the case with a MOSFET or pn junction diode. In the case of the 1 × 10 ¹³ /cm ² doped TSBR, it exhibits MOSFET-like properties, such as a low V _F , low peak reverse recovery current ( I _PR ), and high reverse leakage current, owing to its short channel. However, in the case of the 5 × 10 ¹³ /cm ² doped TSBR, it exhibits the electrical characteristics of either a MOSFET or a pn junction diode, but not both at the same time, such as a high V _F and low reverse leakage current. Moreover, this TSBR has a larger stored charge ( Q _RR ) compared to the 1 × 10 ¹³ /cm ² doped TSBR — the properties of which increase the energy loss at turn-off time. Corresponding Author moseho@etri.re.kr Jong Il Won received his BS and MS degrees in electronic engineering from Seokyeong University, Seoul, Rep. of Korea, in 2008 and 2010, respectively. In 2011, he joined ETRI, where he is now a senior researcher. His research interests include silicon and silicon carbide power semiconductor devices, such as power diodes, MOSFETs, IGBTs, and electrostatic discharge protection circuit design. kunsik@etri.re.kr Kun Sik Park received his BS, MS, and PhD degrees in material engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1991, 1996, and 2011, respectively. From 1996 to 2000, he worked for LG Semicon Co., Ltd., CheongJu, where he developed device technology for DRAM. Since 2000, he has been working at ETRI, where he is responsible for research and development of Si- and SiC-based devices, including power devices, sensors, and detectors. cdhengud@naver.com Doo Hyung Cho received his BS degree in electrical and electronic engineering from Dankook University, Seoul, Rep. of Korea, in 2011 and his MS degree in electronic engineering from Sogang University, Seoul, Rep. of Korea, in 2013. He is currently working toward his PhD degree in electronic engineering at Sogang University. His research interests include Si/SiC power semiconductor device design and power conversion circuits. jgkoo@etri.re.kr Jin Gun Koo received his BS and MS degrees in electronic engineering from Kyungpook National University, Dageu, Rep. of Korea, in 1980 and 1992, respectively. From 1980 to 1985, worked on silicon-based device design and process integration of high-speed bipolar transistors at the Korean Institute of Electronics Technology Sejong, Rep. of Korea. Since 1986, he has been with the Semiconductor Fields Department of ETRI, where he is now a head of the Semiconductor Process Team. His research interests include power MOSFETs and IGBTs; power ICs; MEMS and sensors; and semiconductor equipment and facilities. sgkim@etri.re.kr Sang Gi Kim received his MS and PhD degrees in physics from Yeungnam University, Kyeongsan, Rep. of Korea, in 1989 and 1996, respectively. In 1981, he joined the Semiconductor Division of ETRI, where he has been working on materials science and device characterization in advanced TDMOS and technology for power devices. His work also includes the development of oxide, silicon, SiC, and metal dry etching processes, the development of CMP processes, and the development of technology for trench etching, trench gate devices, and SIC power devices. leejinho@etri.re.kr Jin Ho Lee received his BS degree in physics from Kyungpook National University, Daegu, Rep. of Korea, in 1980 and his MS degree from Korea University, Seoul, Rep. of Korea, in 1982. He received his PhD degree from Kyungpook National University, in 1998. He joined ETRI in 1982. He has been working on power electronic devices, thin-film transistor technology, and flexible devices. At present, he is the managing director of the IT Components and Materials Industry Technology Research Department at ETRI.