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Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation
Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation
ETRI Journal. 2016. Mar, 38(1): 133-140
Copyright © 2016, Electronics and Telecommunications Research Institute (ETRI)
  • Received : July 28, 2015
  • Accepted : December 30, 2015
  • Published : March 01, 2016
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About the Authors
Woojin Chang
Young-Rak Park
Jae Kyoung Mun
Sang Choon Ko

Abstract
This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) field-effect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.
Keywords
I. Introduction
A power semiconductor device used in a power electronic system requires a high breakdown voltage, high current, low on-resistance, and high-speed switching characteristics. In particular, when a power semiconductor device with a high-speed switching operation enabled is used, the sizes of the inductors and capacitors in the power electronic system can be reduced.
Gallium nitride (GaN)–based transistors have been used for many years for RF applications. GaN-based power semiconductor devices have been recently studied to achieve a low cost and high performance of related power electronic systems because the GaN device is an emerging candidate as an attractive device for high frequencies compared to the silicon (Si) metal–oxide–semiconductor field-effect transistor (MOSFET) with the same efficiency. A GaN transistor has both a higher band-gap, electron mobility and a higher electron velocity than an Si or SiC device. These material characteristics make the GaN device more suitable for higher frequencies and operating voltages. The switching frequency has been continuously increased to several megahertz to reduce the sizes of the passive components and increase the power density [1] [4] .
A GaN FET can be adjusted to shift the gate threshold voltage from negative to positive, resulting in an enhancement-mode device. However, an enhancement-mode GaN FET has a low threshold voltage. In addition, compared to a depletion-mode GaN FET, the driving voltage and saturation current for the enhancement-mode GaN FET are limited [5] , [6] . GaN cascode FETs with high-voltage depletion-mode GaN FETs and low-voltage enhancement-mode Si MOSFETs behave much like low-voltage enhancement-mode Si MOSFETs with their operating voltage extended by the high breakdown voltage of the high-voltage depletion-mode GaN FETs, and are also compatible with commercial gate drivers [7] .
The switching loss of a GaN cascode FET is not only determined by the GaN die, but is also related to the parasitic inductances of the packaging. These parasitic inductances will worsen the switch transition and increase the switching loss. In terms of the speed and energy loss, several critical parasitic inductances of a GaN cascode FET were identified through a theoretical analysis and verified using a simulation model, as reported in [7] .
This paper aims to reduce the most critical parasitic inductance of the GaN cascode FET using an additional bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET for a high-speed switching operation and low switching loss.
II. Design of GaN Cascode FET
With regards to studying the influence of the packaging, much effort has been spent on Si MOSFETs with single-switch structures [8] [10] . It is common sense for the common-source inductance (CSI), which is defined as the inductance shared by the power loop and driving loop, to be the most critical parasitic element. The CSI acts as negative feedback to slow down the driver during the turn-on and turn-off transitions; thus, it prolongs the voltage and current crossover time, and significantly increases the switching loss [7] .
Recently, some papers have discussed the package influence of a GaN cascode FET [5] , [7] , [11] . Several critical parasitic inductances were identified through a theoretical analysis and verified using a simulation model. In terms of the GaN cascode FET, as shown in Fig. 1 , because L int3 is the CSI of both the high-voltage depletion-mode GaN FET and the Si MOSFET, it should be the most critical inductance, providing the major switching loss [7] .
Compared with a conventional GaN cascode FET schematic, shown in Fig. 1 , the proposed GaN cascode FET schematic, shown in Fig. 2 , has an additional bonding wire ( L gs,int ) to reduce the most critical inductance ( L int3 ) acting as the CSI. To analyze whether the most critical inductance ( L int3 ) is reduced by the additional bonding wire ( L gs,int ), a pi-network composed of L gs,int , L int2 , and L int3 , marked by the red dotted box in Fig. 2 , has been converted into a T-network composed of L 1 , L 2 , and L 3 , as shown in Fig. 3 .
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Most critical inductance from perspective of conventional GaN cascode FET [7].
Figure 3(a) shows the parasitic inductances and impedances of the bonding wires interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in the proposed GaN cascode FET structure, as shown by the red dotted box of Fig. 2 . In addition, Fig. 3(b) shows the parasitic inductances and impedances after the pi-to-T network transformation in Fig. 3(a) using (1) through (3). Here, L 1 , L 2 , and L 3 of the T-network in Fig. 3(b) are expressed in (4) through (6).
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Proposed GaN cascode FET schematic with additional bonding wire (Lgs,int) to reduce most critical inductance.
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Pi-to-T network transformation: (a) pi- and (b) T-network.
(1) Z 1 = Z a Z c Z a + Z b + Z c ,
(2) Z 2 = Z b Z c Z a + Z b + Z c ,
(3) Z 3 = Z a Z b Z a + Z b + Z c ,
(4) L 1 = L int3 L gs,int L int3 + L int2 + L gs,int ,
(5) L 2 = L int2 L gs,int L int3 + L int2 + L gs,int ,
(6) L 3 = L int3 L int2 L int3 + L int2 + L gs,int .
Figure 4 shows an equivalent circuit of the proposed GaN cascode FET with an additional bonding wire ( L gs,int ) after the pi-to-T network transformation. The value of L int3 , which is the sum of L 1 and L 3 , is matched with the most critical inductance ( L int3 ) in Fig. 1 . In addition, the value of L int2 , which is the sum of L 2 and L 3 , is matched with L int2 in Fig. 1 .
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Equivalent circuit of GaN cascode FET with additional bonding wire (Lgs,int) after pi-to-T network transformation.
From (7) through (12), it is shown that the additional bonding wire ( L gs,int ) can reduce the parasitic inductances, such as L int2 and L int3 . Moreover, because L int3 is less than L int3 , which should be the most critical inductance, thereby giving the major switching loss, the proposed GaN cascode FET is expected to have a faster switching speed and less energy consumption at the switching transition region than a conventional GaN cascode FET.
(7) L int3 ' = L 1 + L 3 = L int3 ( L int2 + L gs,int ) L int3 + L int2 + L gs,int ,
(8) L int3 ' = L 2 + L 3 = L int2 ( L int3 + L gs,int ) L int3 + L int2 + L gs,int ,
(9) L int2 + L gs,int L int3 + L int2 + L gs,int <1,
(10) L int3 + L gs,int L int3 + L int2 + L gs,int <1,
(11) L int3 ' < L int3 ,
(12) L int2 ' < L int2 .
Figure 5 shows the bonding diagrams of the conventional and proposed GaN cascode FETs to compare the packaging structures. The conventional packaging structure [7] is matched with the schematic shown in Fig. 1 . In addition, the proposed packaging structure is also matched with the schematic having an additional bonding wire ( L gs,int ) interconnected between the source of the Si MOSFET and the gate of the GaN FET shown in Fig. 2 .
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Simplified bonding diagrams of GaN cascode FET package: (a) conventional [7] and (b) proposed structures.
Figure 6 shows photographs of a GaN cascode FET in a TO-254 metal package using a conventional cascode structure and the proposed cascode structure with an additional bonding wire ( L gs,int ). The low-voltage enhancement-mode Si MOSFET made by Trinno Technology in the package has a threshold voltage of 4.5 V, a maximum drain-source current of 40 A, a drain-source breakdown voltage of 100 V, a drain-source on-resistance of 30 mΩ, and a size of 2.9 mm × 2.9 mm. In addition, the high-voltage depletion-mode GaN FET on a silicon substrate, fabricated by ETRI, in the package has a gate length of 1 μm, a unit gate width of 0.5 mm, a total gate width of 26 mm, a gate-to-source distance of 2 μm, a gate-to-drain distance of 21 μm, and a size of 2.2 mm × 1.7 mm. The GaN FET has a measured threshold voltage of −5.5 V, a maximum drain-source current of 9.7 A, a drain-source leakage current density of 0.6 mA/mm at 600 V, a drain-source breakdown voltage of 604 V at a drain-source leakage current density of 1 mA/mm, and a drain-source on-resistance of 450 mΩ. An Au 0.8 Sn 0.2 eutectic bonding technique was used for the chip die attached to the TO-254 package body for a high thermal conductivity, and a 4-mil ribbon-bonding technique was also used for pad-to-pad and pad-to-lead interconnections for a high current flow.
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Photographs of GaN cascode FETs in TO-254 metal packages: (a) proposed cascode structure with additional bonding wire (Lgs,int) and (b) conventional cascode structure after detaching additional bonding wire from proposed cascode structure.
III. Measurements
Figure 7 shows the measured results of the I DS - V DS characteristics for the packaged GaN cascode FET with an additional bonding wire ( L gs,int ) using a Tektronix 370A TM curve tracer. A threshold voltage of 4.5 V; a drain-source current of 9.1 A at V gs = 7 V and V ds = 6.2 V; and a drain-source on-resistance of 500 mΩ were achieved. In addition, after detaching the additional bonding wire from the proposed GaN cascode FET to make a conventional cascode structure, it had the same dc characteristics.
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Measured results of IDS-VDS characteristics for packaged GaN cascode FET with additional bonding wire (Lgs,int).
Figure 8 shows the measured results of the switching waveforms for the proposed GaN cascode FET at 30 V, 5 A, and V gs = 0/8 V (off/on). Owing to the limitation of our switching measurement system with an inductive load, we had to measure it under the conditions of 30 V and 5 A. It had a turn-on delay time ( t d,on ) of 27.2 ns, a rising time ( t r ) of 45.0 ns, a turn-off delay time ( t d,off ) of 36.4 ns, and a falling time ( t f ) of 18.4 ns. In addition, to investigate the differences between the conventional and proposed GaN cascode FETs, an additional bonding wire ( L gs,int ) was detached from the proposed GaN cascode FET after all measurements were taken, and the switching characteristics were then immediately measured under the same conditions of the measurement system. This means that the proposed GaN cascode FET and the conventional GaN cascode FET under the same conditions of the measurement system had the same chips, package body, die bonding, and ribbon-wire bonding, with the only exception being the additional bonding wire ( L gs,int ). The conventional GaN cascode FET had a turn-on delay time ( t d,on ) of 27.6 ns, a rising time ( t r ) of 46.6 ns, a turn-off delay time ( t d,off ) of 34.4 ns, and a falling time ( t f ) of 20.0 ns, as shown in Fig. 9 .
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Measured results of switching waveforms for proposed GaN cascode FET at 30 V, 5 A, and Vgs = 0/8 V (off/on): (a) turn-on characteristics during 200 ns and (b) turn-off characteristics during 200 ns.
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Measured results of switching waveforms for conventional GaN cascode FET at 30 V, 5 A, and Vgs = 0/8 V (off/on): (a) turn-on characteristics during 200 ns and (b) turn-off characteristics during 200 ns.
From the measured results, the turn-on delay time, the rising time, and the falling time of the proposed GaN cascode FET were up to 0.4 ns, 1.6 ns, and 1.6 ns lower than those of the conventional GaN cascode FET, respectively. This means that the proposed GaN cascode FET was faster than the conventional GaN cascode FET owing to the additional bonding wire ( L gs,int ) in the proposed GaN cascode FET.
Figure 10 shows the measured results of the turn-on switching waveforms for the proposed and conventional GaN cascode FETs at 30 V, 5 A, and V gs = 0/8 V (off/on). The maximum turn-on power losses of the proposed and conventional GaN cascode FETs were 50.2 W at 147.2 ns and 50.6 W at 149.2 ns, respectively. The second peaks of the power losses of the proposed and conventional GaN cascode FETs were 23.1 W at 217.4 ns and 25.3 W at 213.6 ns, respectively. In addition, the third peaks of the power losses of the proposed and conventional GaN cascode FETs were 21.8 W at 256.0 ns and 22.6 W at 252.8 ns, respectively. From the results, the maximum, second peak, and third peak power losses of the proposed GaN cascode FET were up to 0.4 W, 2.2 W, and 1.8 W lower than those of the conventional GaN cascode FET, respectively.
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Measured results of turn-on switching waveforms for GaN cascode FETs at 30 V, 5 A, and Vgs = 0/8 V (off/on): (a) Vds and Ids, and (b) turn-on power loss over time.
The energy loss of the proposed GaN cascode FET during the turn-on delay time of 107.8 ns to 135.0 ns was 18.1 nJ. In addition, the energy loss of the conventional GaN cascode FET during the turn-on delay time of 104.8 ns to 132.4 ns was 33.1 nJ. The energy loss of the proposed GaN cascode FET during the rising time of 135.0 ns to 180.0 ns was 1,903.4 nJ. Moreover, the energy loss of the conventional GaN cascode FET during a rising time of 132.4 ns to 179.0 ns was 1,909.0 nJ. The energy losses of the proposed GaN cascode FET during the turn-on delay time and rising time were up to 15 nJ and 5.6 nJ lower than those of the conventional GaN cascode FET, respectively.
Figure 11 presents the measured results of the turn-off switching waveforms for the proposed and conventional GaN cascode FETs at 30 V, 5 A, and V gs = 0/8 V (off/on). The maximum turn-off power losses of the proposed and conventional GaN cascode FETs were 67.1 W at 194.6 ns and 71.3 W at 195.4 ns, respectively. The second peaks of the power losses of the proposed and conventional GaN cascode FETs were 3.6 W at 220.6 ns and 5.0 W at 224.0 ns, respectively. The maximum and second-peak power losses of the proposed GaN cascode FET were up to 4.2 W and 1.4 W lower than those of the conventional GaN cascode FET, respectively.
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Measured results of turn-off switching waveforms for GaN cascode FETs at 30 V, 5 A, and Vgs = 0/8 V (off/on): (a) Vds and Ids and (b) turn-off power loss over time.
The energy loss of the proposed GaN cascode FET during a turn-off delay time of 139.8 ns to 176.2 ns was 478.4 nJ. In addition, the energy loss of the conventional GaN cascode FET during the turn-off delay time of 141.4 ns to 175.8 ns was 522.8 nJ. The energy loss of the proposed GaN cascode FET during a falling time of 176.2 ns to 194.6 ns was 751.1 nJ. Moreover, the energy loss of the conventional GaN cascode FET during a falling time of 141.4 ns to 175.8 ns was 805.4 nJ. From the measured results, the turn-off delay time and falling time energy losses of the proposed GaN cascode FET were up to 44.4 nJ and 54.3 nJ lower than those of the conventional GaN cascode FET, respectively.
Table 1 shows a comparison of the measured switching characteristics between the conventional and proposed GaN cascode FETs. The rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, for the measurement conditions of 30 V/5 A. For the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.
Comparison of measured switching characteristics between conventional and proposed GaN cascode FETs.
Parameter Unit Conventional GaN cascode FET Proposed GaN cascode FET
Turn-on switching transition characteristics Rising time, tr ns 46.6 45.0
Turn-on delay time, td,on ns 27.6 27.2
Energy loss for tr nJ 1,909.0 1,903.4
Energy loss for td,on nJ 33.1 18.1
Turn-off switching transition characteristics Falling time, tf ns 20.0 18.4
Turn-off delay time, td,off ns 34.4 36.4
Energy loss for tf nJ 805.4 751.1
Energy loss for td,off nJ 522.8 478.4
The results indicate that the additional bonding wire ( L gs,int ) between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in the GaN cascode FET can reduce the most critical inductance ( L int3 ) among the parasitic inductances in the package acting as the CSI, which provides the major switching and energy losses of the GaN cascode FET.
IV. Conclusion
This paper presented a method for reducing the parasitic inductance for a high-speed switching and efficiency operation of a cascode structure with a low-voltage Si MOSFET and high-voltage depletion-mode GaN FET. The measured results of the proposed and conventional GaN cascode FETs show that the energy losses of the proposed GaN cascode FET during the turn-on delay time and rising time were up to 15 nJ and 5.6 nJ lower than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. The rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under the same measurement conditions. For the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively. Therefore, the inductance made by the additional bonding wire between the source electrode of the Si MOSFET and the gate electrode of the GaN FET reduces the most critical inductance, acting as the common-source inductance, which can achieve a faster switching speed and lessen the switching loss. These characteristics make the GaN cascode FET more suitable for high-speed and high-efficient power applications.
This work was supported by the “Next Generation Optical and Electrical Module Technology for Smart Data Center” IT Convergence Device R&D project (No. B0101-15-0132), the “Development of High Efficiency GaN-Based Key Components and Modules for Base and Mobile Stations” R&D project (No. B0132-15-1006), and the “High Efficiency GaN-Based Inverter Using GaN-SBD and FET Discrete Devices Technology” INNOPOLIS Foundation R&D project (No. 14DDI100) of Korea Ministry of Science, ICT and Future Planning.
BIO
Corresponding Author wjchang@etri.re.kr
Woojin Chang received his BS and MS degrees in information engineering from Korea University, Sejong and Seoul, Rep. of Korea, in 1996 and 1998, respectively, and his PhD degree in electronic engineering from Chungnam National University, Daejeon, Rep. of Korea, in 2008. From 1998 to 1999, he worked as an engineer with LG Precision Co. Ltd., Yongin, Rep. of Korea, where he was engaged in the research and development of power amplifier modules for wireless communications. In 1999, he joined ETRI, where he is currently a principal engineer. His research interests include the design and analysis of GaN cascode switches and MMICs operating up to the millimeter-wave range.
raferer@etri.re.kr
Young-Rak Park received his BS degree in information and communications engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 2008 and his MS degree in electrical engineering from Seoul National University, Rep. of Korea, in 2011. He has studied the design of radio frequency power amplifiers and millimeter-wave ICs. Since February 2011, he has been with ETRI. His research activities include the fabrication and design of GaN devices.
jkmun@etri.re.kr
Jae Kyoung Mun received his BS degree in materials science and engineering from Ajou University, Suwon, Rep. of Korea, in 1990 and his MS and PhD degrees in materials science and engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1992 and 2006, respectively. In 1992, he began working at ETRI. His research interests included the development of GaAs MMIC front- and backside processes, reliability, and failure mechanisms. From 2004, he worked on designing RF and millimeter-wave band MMIC switches. From 2006 to 2009, he worked as an adjunct associated professor at Daejeon University, Rep. of Korea. From 2009 to 2010, he worked as a consultant at Bell Labs, Murray Hill, NJ, USA. From 2011 to 2013, he was in charge of GaN RF & power devices R&D group. From 2013, he was also a professor with the Department of Advanced Device Engineering, Korea University of Science and Technology, Daejeon, Rep. of Korea. His main research interests are GaN devices and Au-free CMOS compatible process developments. He received the Best Student Award from Ajou University upon his graduation in 1990. He received scholarships from the Ministry of Science & Technology in 1990 and 1991. He has published 52 SCI papers and 41 international conference proceedings. Besides this, he has over 51 US patents and 66 Korean patents.
scko@etri.re.kr
Sang Choon Ko received his BS and MS degrees in electrical engineering from Sungkyunkwan University, Suwon, Rep. of Korea, in 1994 and 1996, respectively. He then went on to receive his PhD degree in mechanical precision engineering from Tohoku University, Sendai, Japan, in 1999. Later that year, he joined the Microsystem Technology Laboratory of DaimlerChrysler Co., München, Germany, as a visiting researcher. At the same time, he was a research associate with the Department of Mechatronics and Electronics, Tohoku University. In 2000, he joined Pohang University of Science and Technology, Rep. of Korea in a post-doctoral position. Since 2001, he has been working with the Microsystem Team, ETRI. He has worked on projects related to piezoelectric acoustic devices, condenser microphones, and energy harvesting devices. Currently, he is working on wide bandgap–based power devices and modules.
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