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High-Performance Amorphous Multilayered ZnO-SnO2 Heterostructure Thin-Film Transistors: Fabrication and Characteristics
High-Performance Amorphous Multilayered ZnO-SnO2 Heterostructure Thin-Film Transistors: Fabrication and Characteristics
ETRI Journal. 2015. Dec, 37(6): 1135-1142
Copyright © 2015, Electronics and Telecommunications Research Institute (ETRI)
  • Received : June 22, 2014
  • Accepted : August 10, 2015
  • Published : December 01, 2015
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About the Authors
Su-Jae Lee
Chi-Sun Hwang
Jae-Eun Pi
Jong-Heon Yang
Chun-Won Byun
Hye Yong Chu
Kyoung-Ik Cho
Sung Haeng Cho

Abstract
Multilayered ZnO-SnO 2 heterostructure thin films consisting of ZnO and SnO 2 layers are produced by alternating the pulsed laser ablation of ZnO and SnO 2 targets, and their structural and field-effect electronic transport properties are investigated as a function of the thickness of the ZnO and SnO 2 layers. The performance parameters of amorphous multilayered ZnO-SnO 2 heterostructure thin-film transistors (TFTs) are highly dependent on the thickness of the ZnO and SnO 2 layers. A highest electron mobility of 43 cm 2 /V·s, a low subthreshold swing of a 0.22 V/dec, a threshold voltage of 1 V, and a high drain current on-to-off ratio of 10 10 are obtained for the amorphous multilayered ZnO(1.5 nm)-SnO 2 (1.5 nm) heterostructure TFTs, which is adequate for the operation of next-generation microelectronic devices. These results are presumed to be due to the unique electronic structure of amorphous multilayered ZnO-SnO 2 heterostructure film consisting of ZnO, SnO 2 , and ZnO-SnO 2 interface layers.
Keywords
I. Introduction
Thin-film transistors (TFTs) based on wide bandgap amorphous oxide semiconductors, including zinc tin oxide (ZTO), indium gallium zinc oxide (IGZO), indium zinc oxide, and indium zinc tin oxide have been intensively studied in the field of thin-film electronics during the past decades [1] [7] , and are rapidly approaching commercialization as a replacement for amorphous Si in high-performance electronics applications, such as active-matrix organic light-emitting diodes, active-matrix liquid-crystal displays, and flexible displays [7] . In particular, IGZO is one of the most promising channel materials because of its high carrier mobility, good TFT performance, low processing temperature, excellent environmental stability, and high transparency. Thus far, there have been significant attempts to find a new oxide semiconductor as an alternative to indium/gallium-based semiconducting oxides, owing to their rarity, high cost, and toxicity. Still, for TFTs and next-generation microelectronic device applications with low power consumption and higher performance, it is necessary to develop new eco-friendly semiconducting oxide materials exhibiting better transistor properties; that is, higher mobility, a smaller subthreshold swing (ss), a higher ratio of on-to-off drain current ( I on / I off ), and longer stability. Multilayer thin films have been widely studied because their properties are different from those of conventional thin films and bulk materials owing to the two-dimensional film and high-density interface. Since the recent observation of high-mobility two-dimensional electron gas (2DEG) at the interface between the two insulating oxides in a LaTiO 3 /SrTiO 3 heterostructure [8] , a high mobility 2DEG behavior has been seen in semiconductor ZnO-based ZnO/Zn 1−x Mg x O heterostructures. Thus far, several studies regarding the formation of 2DEG and the performance of field-effect transistors (FETs) with a single crystalline or polycrystalline semiconducting ZnO/MgZnO heterostruture have been carried out [9] [12] . K. Koike and others reported high-performance ZnO-based FETs that were designed to take advantage of a high-mobility electron channel formed in the ZnO/ZnMgO heterostructure, and demonstrated a transconductance of 0.7 mS/mm with a very high field-effect mobility of 140 cm 2 /V·s at room temperature [9] . Such interfacial electron gases in a two-oxide heterostructure can be used to design innovative oxide electronic devices. Thus, the electronic structure of a two-oxide heterointerface is important for its stability, function, and improved performance in many devices. Among the ZnO-based semiconducting oxides, the binary ZnO-SnO 2 systems that possess high electron conductivity and high electron mobility have currently attracted significant attention as low-cost indium/gallium-free alternative transparent conducting and amorphous semiconducting oxide materials for applications in many devices, such as transparent electrodes for solar cells, electronics, flat panel displays (FPDs), sensors, photocatalysts, and the active channel layer of TFTs [3] [4] , [13] . ZnO and SnO 2 are generic n-type semiconductors with wide band gaps of 3.2 eV and 3.6 eV, respectively. ZnO and SnO 2 have different crystal structures; namely, wurtzite and rutile structures, respectively. In addition, they also have different semiconducting properties. Multilayered ZnO-SnO 2 heterostructure thin films consisting of two ZnO and SnO 2 layers that are expected to have an unusual property owing to the formation of unusual charge states at the interface, which are inaccessible in conventional thin films and bulk materials, may be realized, which will enhance the efficiency and performance of many electronic and optical devices. Thus, one motive of this study is to observe the effects of a high-mobility two-dimensional electron channel in multilayer ZnO-SnO 2 heterostructure TFTs such as a 2DEG in a heterointerface.
In this work, multilayered ZnO-SnO 2 heterostructure thin films were produced by alternating the pulsed laser ablation of ZnO and SnO 2 targets, and their structural and field-effect electronic transport properties were investigated as a function of the thickness of the ZnO and SnO 2 layers.
II. Experiments
Multilayered ZnO-SnO 2 heterostructure films were grown by the alternating deposition of ZnO and SnO 2 layers using pulsed laser deposition (PLD) on SiO 2 /Si and pre-patterned source-drain (ITO)/gate insulator (Al 2 O 3 )/gate electrode (ITO)/glass substrates. After a base pressure of lower than 1 × 10 −6 Torr was achieved, the ZnO and SnO 2 targets were ablated with a KrF excimer laser (λ = 248 nm) at a laser energy density of 2 J/cm 2 and a pulsed laser frequency of 2 Hz. The deposition process was carried out at room temperature under an oxygen pressure of 30 mTorr, and then annealed at 350°C in air. The crystallographic structure, microstructures, and elemental composition analysis of the multilayered ZnO-SnO 2 heterostructure films were investigated using glancing-angle X-ray diffraction (GXRD), a Cs-corrected scanning transmission electron microscope (STEM), and an electron dispersive spectroscopy (EDS) embedded in the STEM, respectively. To investigate the field-effect electronic transport properties of multilayered ZnO-SnO 2 heterostructure thin films, field-effect TFTs were fabricated, which have a bottom gate TFT configuration. A lithographically patterned 150 nm-thick indium tin oxide (ITO) film on a glass substrate was used as the bottom gate electrode (BG). A 176 nm-thick Al 2 O 3 film as a gate insulator (GI) was deposited at a temperature of 150°C by means of atomic layer deposition (ALD) with trimethylaluminum [TMA, Al(CH 3 ) 3 ] as precursors and H 2 O as the oxidant. A 150 nm-thick ITO as a source–drain (S/D) electrode was deposited by DC sputtering at room temperature, and then annealed at 200°C. After ITO (S/D) patterning, 30 nm-thick multilayered ZnO-SnO 2 heterostructure films, as a channel layer, were deposited using a shadow mask by PLD. The channel width ( W ) and length ( L ) were 40 μm and 20 μm, respectively. The field-effect transport properties were measured at room temperature in air using a Keithley 4200 semiconductor parameter analyzer.
III. Results and Discussion
The crystalline phase formation of multilayered ZnO-SnO 2 heterostructure thin films was analyzed using GXRD. Figure 1 shows the GXRD pattern of a 350°C annealed multilayered ZnO-SnO 2 heterostructure film stacked onto 1.5 nm-thick ZnO and 1.5 nm-thick SnO 2 layers grown on a SiO 2 /Si substrate. The total thickness of the film is 114 nm. The film exhibited no diffraction peaks related to the hexagonal wurtzite ZnO or tetragonal rutile SnO 2 phases, and exhibited only a broad diffraction peak, which indicates that the film is in an amorphous phase. These results indicate that ZnO-SnO 2 film has an amorphous multilayered heterostructure, consisting of amorphous ZnO and SnO 2 layers.
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GXRD patterns of multilayered ZnO(1.5 nm)-SnO2(1.5 nm) heterostructure thin film grown on SiO2/Si substrate.
Figure 2(a) shows a high-resolution cross-sectional STEM image of a multilayered ZnO-SnO 2 heterostructure film grown on a SiO 2 /Si substrate and annealed at 350°C. The film has a multilayer heterostructure in which the ZnO and SnO 2 layers are stacked periodically, and do not show any crystallinity. The thickness of the ZnO and SnO 2 layers was observed to be about 2.0 nm. The interface between the ZnO layer and SnO 2 layer cannot be clearly discerned. The inset of Fig. 2(a) shows the selected area electron diffraction (SAED) patterns of the film, which exhibited only broad diffuse diffraction rings, indicating the characteristics of an amorphous phase. Based on the XRD, STEM, and SAED results, we can confirm that multilayered ZnO-SnO 2 films annealed at 350°C have an amorphous heterostructure consisting of amorphous ZnO and SnO 2 layers. The chemical composition of the amorphous multilayered ZnO-SnO 2 heterostructure film was analyzed using an elemental line profile of EDS embedded in the STEM. Figure 2(b) shows the EDS results obtained for the direction normal to the surface. The inset in Fig. 2(b) is a bright field STEM image. It shows only peaks for oxygen, zinc, and tin elements, which show periodic peaks corresponding to ZnO and SnO 2 layers.
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(a) High-resolution cross-sectional STEM images and (inset) SAED patterns, and (b) elemental line profile of EDS for multilayered ZnO-SnO2 heterostructure film grown on SiO2/Si substrate.
To investigate the field-effect electronic transport properties of amorphous multilayered ZnO-SnO 2 heterostructure thin films, the bottom-gate TFTs were fabricated and electrically characterized at room temperature. To study how the thickness of the ZnO and SnO 2 layers influences the transistor properties, the amorphous multilayered ZnO-SnO 2 heterostructure films acting as channel layers were deposited by varying the thickness of the ZnO and SnO 2 layers. The following films were prepared: ZnO(0.5 nm)-SnO 2 (0.5 nm), ZnO(1.0 nm)-SnO 2 (1.0 nm), ZnO(1.5 nm)-SnO 2 (1.5 nm), ZnO(2.0 nm)-SnO 2 (2.0 nm), ZnO(2.5 nm)-SnO 2 (2.5 nm), and ZnO(3.0 nm)-SnO 2 (3.0 nm). For example, in the multilayered ZnO(1.5 nm)-SnO 2 (1.5 nm) heterostructure film, the thickness of the ZnO and SnO 2 layers was 1.5 nm. To obtain an active channel layer with a total thickness of 30 nm, 1.5 nm-thick ZnO and SnO 2 layers were alternately deposited ten times, and stacked to a total of 20 layers. Figure 3 shows the representative drain current versus drain-to-source voltage ( I ds V d ) output curves for a transistor with an amorphous multilayered ZnO(1.5 nm)-SnO 2 (1.5 nm) heterostructure film channel at various gate voltages ( V g ). The inset in Fig. 3 shows a schematic layout of the fabricated bottom-gate TFT structure. The n-type transistor behavior with a pinch-off and drain current saturation can clearly be seen from the output curve, which indicates that the electron transportation in the active channel is totally controlled by the gate and drain voltages as in conventional metal–oxide–semiconductor FETs.
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Representative drain current (Ids) vs. drain–source voltage (Vd) output curves of amorphous multilayered ZnO (1.5 nm)-SnO2(1.5 nm) heterostructure TFTs, and (inset) schematic layout of fabricated TFT structure.
The field-effect electronic transport properties of the amorphous multilayered ZnO-SnO 2 heterostructure thin films were investigated as a function of the ZnO and SnO 2 layer thickness. Figure 4(a) shows the transfer characteristics of the drain current versus gate voltage ( I ds V g ) at drain voltages ( V d ) of 0.1 V and 15 V of amorphous multilayered ZnO-SnO 2 nanostructure TFTs for various ZnO and SnO 2 layer thicknesses.
The total thickness of the ZnO-SnO 2 channel layer is 30 nm. All of the TFTs show typical transfer curves of well-behaved transistors. The TFT with the ZnO(1.5 nm)-SnO 2 (1.5 nm) channel layer exhibits the highest drain on-current ( I on ) at V d of 0.1 V and 15 V, and at V g of 30 V. The drain on-current ( I on ) shows a clearly decreasing trend with increasing ZnO and SnO 2 layer thicknesses. The drain off-current ( I off ) is in the range of 10 −13 A to 10 −15 A for all TFTs, which is below the maximum level of 10 −12 A for an FPD [5] . The drain current on-off ratio ( I on / I off ) derived from the transfer curve for a V d of 15 V was as high as approximately 10 10 for all TFTs, which is a superior property compared with those of the other reports for amorphous ZTO TFTs (approximately 10 8 ) [3] [4] , [13] [15] . These very low off currents and high on-off ratio may result from a small number of channel interface traps and mobile ions in an amorphous multilayered ZnO-SnO 2 heterostructure film. In addition, the turn-on voltage, which is the gate voltage at the onset of the initial sharp increase in current in the transfer curve, was in the range of 0 V to −1.5 V except for the ZnO(3.0 nm)-SnO 2 (3.0 nm) transistor, which was negatively shifted (−3 V). The negative V on shift is attributed to the increasing of free carrier concentration at the thicker ZnO and SnO 2 layers, which contributes to the channel conductivity. The performance parameters of the TFTs, including the field-effect saturation mobility ( μ sat ) and the threshold voltage ( V th ), were calculated from the transfer curves in the saturation region using I ds = ( WCi /2 L ) μ sat ( V g V th ) 2 , where W and L are the channel width and length, respectively; Ci is the capacitance per unit area of the Al 2 O 3 gate insulator, and V th is the threshold voltage. The saturation mobility ( μ sat ) was obtained through the transconductance in the saturation region of the I ds V g curves for a V d of 15 V. The threshold voltage ( V th ) was determined from the interception with the V g axis of the slope of the I ds 1/2 versus V g plot. In addition, the subthreshold swing (ss = d V g / d(log I ds )[V / decade]) was extracted from the linear part of the log ( I ds ) versus V g plot. Figure 4(b) shows the extracted saturation mobility ( μ sat ), threshold voltage ( V th ), and subthreshold swing (ss) as a function of the ZnO and SnO 2 layer thicknesses. The thickness of the ZnO and SnO 2 layers clearly influences the mobility of the transistors. It can be seen that the mobility is largely dependent on the ZnO and SnO 2 layer thickness in the channel layer. The mobility increased with the increased thickness of the ZnO and SnO 2 layers at up to 1.5 nm, and then significantly decreased with further thickness increases. The highest saturation mobility of 43 cm 2 /V·s was observed for the amorphous multilayered ZnO(1.5 nm)-SnO 2 (1.5 nm) heterostructure TFTs. This value is larger than those reported for conventional TFTs with an amorphous ZTO channel layer [3] [4] , [13] [15] . It is speculated that the high mobility of the TFTs is due to the effect of the interface layer related to a high-mobility electron channel formed in a ZnO-SnO 2 heterostructure. Three ZnO, SnO 2 , and ZnO/SnO 2 interface channels in amorphous multilayered ZnO-SnO 2 heterostructure TFTs can be formed. The cause of the decrease in mobility at the thicker ZnO and SnO 2 layers might be understood as the ZnO and SnO 2 layers playing a role as the dominant active channel in the TFTs, and that the number of ZnO-SnO 2 interface layers decreased with an increase in the ZnO and SnO 2 layer thicknesses at the same channel thickness of 30 nm. These results indicate that the mobility of the TFTs can be controlled by optimizing the thickness of the ZnO and SnO 2 layers. The subthreshold swing (ss) is an important parameter for determining the quality of a TFT. As shown in Fig. 4(b) , the ss did not show a specific trend according to the thickness of the ZnO and SnO 2 layers, and showed a value ranging from 0.18 V/dec. to 0.27 V/dec. for all transistors. These values are comparable or better than those reported for ZTO transistors [3] [4] , [13] [15] . The ss value is related to the total density of the trap states ( N t ) in the bulk channel layer ( N bulk ) and at the interface between the channel/dielectric layer ( N it ). From the ss, the density of the trap states ( N t ) can be calculated using N t = N bulk + N it = [{( q × ss ) / k B T } − 1] Ci / q , where q , k B , T , and Ci are the electron charge, the Boltzmann constant, absolute temperature, and capacitance of the dielectric layer, respectively [16] [18] . The calculated trap-charge density ( N t ) of the TFTs has a small value of 4.83 × 10 11 cm −2 to 8.44 × 10 11 cm −2 . In spite of the high mobility of the TFTs, a low subthreshold swing for all transistors is attributed to the low density of the trap states in the ZnO, SnO 2 , and ZnO-SnO 2 interface channel layer and at the interface between the channel and dielectric layer. In addition, the threshold voltage ( V th ), corresponding to the V g for which an accumulation layer is formed did not show a specific dependence on the thickness of the ZnO and SnO 2 layers. The threshold voltage V th has positive values between 0.35 V and 1.1 V for all transistors, indicating that the amorphous multilayered ZnO-SnO 2 heterostructure TFTs operate in enhancement mode on a positive bias.
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(a) Transfer IdsVg characteristics of amorphous multilayered ZnO–SnO2 heterostructure TFTs with various ZnO and SnO2 layer thicknesses, and (b) performance parameters including saturation mobility (μsat), subthreshold swing (ss), and threshold voltage (Vth) of TFTs as function of ZnO and SnO2 layer thicknesses.
Figure 5(a) shows the transfer I ds V g characteristics of amorphous multilayered ZnO-SnO 2 heterostructure TFTs with various ZnO layer thicknesses for a fixed SnO 2 layer thickness (1.5 nm). The I on showed a decreasing trend with increasing ZnO layer thickness. The minimum I off was generally in the range of 10 −13 A to 10 −14 A, which is below the maximum level of 10 −12 A. The I on / I off ratio derived from the transfer curves for V d of 15 V was as high as approximately 10 10 for all transistors. The turn-on voltage ( V on ) was in the range of 0 V to −1 V except for the ZnO(1.0 nm)-SnO 2 (1.5 nm) transistor, which was negatively shifted (−2.4 V). Figure 5(b) shows the extracted field-effect saturation mobility ( μ sat ), subthreshold swing (ss), and threshold voltage ( V th ) as a function of the ZnO layer thickness with a fixed SnO 2 layer thickness. The μ sat increased to a peak value of 43 cm 2 /V·s at ZnO(1.5 nm)-SnO 2 (1.5 nm) TFTs, and then significantly decreased at a higher thickness of the ZnO layer. It can be seen that the mobility is largely dependent on the ZnO layer thickness in the channel layer. The subthreshold gate swing (ss) did not show a specific trend according to the thickness of ZnO for a fixed SnO 2 layer thickness, and showed a value ranging from 0.17 V/decade to 0.27 V/decade for all transistors. In addition, the threshold voltage ( V th ) did not show a specific dependence on the thickness of ZnO for a fixed SnO 2 layer thickness, which has positive values between 0.36 V and 1.35 V for all transistors. Variation in the ZnO layer thickness with a fixed SnO 2 layer thickness clearly influenced the electrical parameters of the transistors. Several investigations have demonstrated that the mobility of ZTO TFTs depends on the Zn/Sn composition ratio in active materials. M.G. McDowell and others reported a decreasing trend of mobility with a decrease in the Zn/Sn ratio in a film formed using a sputtering method [15] . Recently, J.H. Heo and others reported on ZTO TFTs grown by repeating a deposition cycle of ZnO and SnO 2 layers using ALD [4] . It was shown that the mobility of ALD-based ZTO TFTs can be increased by increasing the number of ZnO layer deposition cycles with a constant SnO 2 layer thickness; it was concluded that a higher Zn content leads to a higher mobility when the Zn/Sn ratio is larger than one. Our results show that mobility decreases rapidly with an increase in the thickness of the ZnO layer, which contradicts the conclusions of previous works [4] , [15] reporting that the mobility was found to increase with an increase in the Zn/Sn ratio. The thickness of the ZnO layer in a ZnO-SnO 2 heterostructure channel significantly impacts on the electronic transport properties of the TFT. Based on these observations, it was concluded that a higher ZnO layer thickness leads to a lower mobility.
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Lager Image
(a) Transfer IdsVg characteristics of amorphous multilayered ZnO-SnO2 heterostructure TFTs with various ZnO layer thicknesses for fixed SnO2 layer thickness (1.5 nm), and (b) performance parameters including saturation mobility (μsat), subthreshold swing (ss), and threshold voltage (Vth) of TFTs as function of ZnO layer thickness for 1.5 nm thick SnO2 layer.
Figure 6(a) shows the transfer I ds V g characteristics of amorphous multilayered ZnO-SnO 2 heterostructure TFTs with various SnO 2 layer thicknesses for a fixed ZnO layer thickness (1.5 nm). As shown in Fig. 6(a) , the I on / I off ratio derived from the transfer curve for a V d of 15 V was as high as approximately 10 10 for all transistors. The turn-on voltage ( V on ) was in the range of 0 V to −1 V except for the ZnO(1.5 nm)-SnO 2 (2.5 nm) and ZnO(1.5 nm)-SnO 2 (3.0 nm) transistors, which were largely negatively shifted (−4.8 V and −9.2 V, respectively), dependent on the thickness of the SnO 2 layer, and shifted toward to the negative voltage with an increase in the thickness of the SnO 2 layer. Generally, the V on shift of oxide semiconducting TFTs can be explained by various factors, such as defects, carrier concentration, and charge trapping in oxide channel layers and interface between channel and gate dielectrics. The V on shifts of TFTs with thicker SnO 2 layer are attributed to the increase in the carrier concentration with an increase in the thickness of the SnO 2 layer, which contributes to the channel conductivity. Figure 6(b) shows the extracted saturation mobility ( μ sat ), subthreshold swing (ss), and threshold voltage ( V th ) as a function of SnO 2 thickness for a fixed ZnO layer thickness (1.5 nm). The μ sat increased to a peak value of 43 cm 2 /V·s at ZnO(1.5 nm)-SnO 2 (1.5 nm) TFTs, and then decreased at a higher thickness of the SnO 2 layer. The ss did not show a specific trend according to the thickness of the SnO 2 layer for a fixed ZnO layer thickness, and showed a value ranging from 0.12 V/dec. to 0.27 V/dec. for all transistors. However, the threshold voltage has a negative value for a high thickness of the SnO 2 layer (2.5 nm and 3.0 nm). The thickness of the SnO 2 layer in a ZnO-SnO 2 heterostructure channel significantly impacts on the performance parameters of the TFT, such as mobility and threshold voltage. Based on these results, it was concluded that a higher SnO 2 layer thickness leads to a lower mobility and a negative V th shift.
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Lager Image
(a) Transfer IdsVg characteristics of amorphous multilayered ZnO-SnO2 heterostructure TFTs with various SnO2 layer thicknesses for fixed ZnO layer thickness (1.5 nm), and (b) performance parameters including saturation mobility (μsat), subthreshold swing (ss), and threshold voltage (Vth) of TFTs as function of SnO2 layer thickness for 1.5 nm thick ZnO layer.
IV. Conclusion
In conclusion, amorphous multilayered ZnO-SnO 2 heterostructure thin films were produced using a pulsed laser ablation of ZnO and SnO 2 oxides targets, and their field-effect electronic transport properties were investigated as a function of the thickness of the ZnO and SnO 2 layers. The films have an amorphous multilayered heterostructure consisting of ZnO and SnO 2 layers. The thicknesses of the ZnO and SnO 2 layers have a significant impact on the electronic transport properties of the TFTs. Based on our observations, it was concluded that the mobility of the TFTs can be controlled by optimizing the thickness of the ZnO and SnO 2 layers. The highest field-effect mobility of 43 cm 2 /V·s, a subthreshold swing of 0.22 V/dec., a threshold voltage of 1 V, and a drain current on-to-off ratio of 10 10 were obtained for the amorphous multilayered ZnO (1.5 nm)-SnO 2 (1.5 nm) heterostructure TFTs. These results reflect the fact that the high mobility of a TFT is attributed to a unique electronic structure owing to the advantageous combination of three ZnO, SnO 2 , and ZnO-SnO 2 interface layers related to a high-mobility electron channel formed in a ZnO-SnO 2 heterostructure film. Our results suggest that an amorphous multilayered ZnO-SnO 2 heterostructure system as an oxide semiconductor can be a potential candidate for the fabrication of high-performance field-effect transistors. Future work is needed to investigate the proper device stability.
This work was supported by the ICT R&D Program of MSIP/IITP (10041416, the core technology development of light and space adaptable energy-saving I/O platform for future advertising service).
BIO
Corresponding Author leesujae@etri.re.kr
Su-Jae Lee received his BS degree in physics from Kyungsung University, Busan, Rep. of Korea, in 1986 and his MS and PhD degrees in physics from Pusan National University, Rep. of Korea, in 1988 and 1997, respectively. Since he joined ETRI in 1997, he has been involved in the development of ferroelectric thin-film/microwave tunable devices and oxide nanofiber electronics. His research interests include the development of new functional superlattice oxides, high mobility semiconducting oxides, and oxide TFTs for next-generation nano-oxide electronics and displays.
hwang-cs@etri.re.kr
Chi-Sun Hwang received his BS degree from Seoul National University, Rep. of Korea, in 1991 and his PhD degree from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1996, both in physics. From 1996 to 2000, he worked to make DRAM devices with 0.18 μm technology at Hyundai Semiconductor Inc., Incheon, Rep. of Korea. In the year 2000, he joined ETRI. Since then, his research has focused on display technology based on active-matrix flat-panel displays using TFTs, especially oxide TFTs. His recent research interests are environment adaptive displays, digital holography, and novel switching devices.
jepi@etri.re.kr
Jae-Eun Pi received his BS and MS degrees in electronic engineering from Konkuk University, Seoul, Rep. of Korea, in 2009 and 2011, respectively. In 2011, he joined the Smart I/O Control Device Research Section of ETRI. His main research interests include transparent and flexible electronics and the design of driving circuits for flat-panel and digital holographic displays.
delmo@etri.re.kr
Jong-Heon Yang received his BS degree in electrical engineering from the Korea Advanced Institute of Science And Technology, Daejeon, Rep. of Korea, in 2000 and his MS degree in electronic engineering from Pohang University of Science and Technology, Rep. of Korea, in 2002. He is currently a senior engineer with the Convergence Technology Research Division of ETRI.
cwbyun@etri.re.kr
Chun-Won Byun received his BS and MS degrees in electrical and computer engineering from Hanyang University, Seoul, Rep. of Korea, in 2002 and 2007, respectively. From 2007 to 2010, he worked for ETRI, and from 2011 to 2013, he worked for Samsung Display, Giheung, Rep. of Korea. Since 2013, he has returned to ETRI and is now working for their Smart I/O Control Device Research Section. His research interests include non-volatile memory devices and their applications; driving methods for new displays; and circuits for flat-panel displays.
hychu@etri.re.kr
Hye Yong Chu received her BS and MS degrees in physics from Kyung Hee University, Seoul, Rep. of Korea, in 1987 and 1989, respectively. She joined ETRI in 1989. She earned her PhD degree in information displays from Kyung-Hee University, in 2008. Her current research interests include novel device architectures in organic light-emitting devices and next-generation displays.
kicho@etri.re.kr
Kyoung-Ik Cho received his BS degree in materials science from the Ulsan Institute of Technology, Rep. of Korea, in 1979 and his MS and PhD degrees in material science and engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1981 and 1991, respectively. He joined ETRI in 1981. He has been working on the development of advanced display devices, and new electronic devices and materials. His current research interests include oxide TFTs and transparent displays; environment adaptable displays; and flexible electronic devices.
helloshcho@etri.re.kr
Sung Haeng Cho received his BS, MS, and PhD degrees from Seoul National University, Rep. of Korea, in 1996, 1998, and 2003, respectively, all in physical chemistry. From 2005 to 2012, he worked to develop LTPS TFTs on a Si backplane for gate driver integration and oxide semiconductor TFTs for large-sized high-resolution high-speed displays at Samsung Display, Giheung, Rep. of Korea. In 2012, he joined ETRI. His current research focusses on high-mobility and high-speed oxide TFT backplane technology for super high-resolution displays.
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