Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme

ETRI Journal.
2015.
Oct,
37(5):
972-978

- Received : May 13, 2014
- Accepted : January 02, 2015
- Published : October 01, 2015

Download

PDF

e-PUB

PubReader

PPT

Export by style

Article

Metrics

Cited by

TagCloud

This paper proposes an accurate tunable-gain 1/
x
circuit. The output voltage of the 1/
x
circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/
x
circuit is tuned by a 10-bit digital code. The 1/
x
circuit was fabricated using a 0.18 μm CMOS process. Its core area is 0.011 mm
^{2}
(144 μm × 78 μm), and it consumes 278 μW at
V
_{DD}
= 1.8 V and
f
_{CLK}
= 1 MHz. Its error is within 1.7% at
V
_{IN}
= 0.05 V to 1 V.
x
circuit is used in analog dividers, filters, fuzzy control, neural networks, and A/D converters
[1]
–
[6]
. Several circuits for the 1/
x
function have been proposed. A voltage-mode analog divider is accurate, but it needs a highly accurate wide-range voltage controlled oscillator
[1]
. A current-mode 1/
x
circuit using weak-inversion MOSFETs has low accuracy due to very low reference and input currents, which are only under a few nanoamperes
[2]
. A voltage-mode analog divider
[3]
, voltage-mode 1/
x
circuit
[4]
, and current-mode analog divider
[5]
have good accuracy; however, their outputs significantly change due to device parameters and temperature.
In this paper, an accurate tunable-gain 1/
x
circuit is proposed. The output voltage of the 1/
x
circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of process parameters, because all variations from active and passive devices are canceled out. In addition, the voltage gain of the 1/
x
circuit is tuned by a 10-bit digital input code.
The rest of this paper is organized as follows. Section II describes the proposed tunable-gain 1/
x
circuit. Section III shows the measurement results of the fabricated chip. Finally, conclusions are drawn in Section IV.
x
circuit generates an output voltage (
V
_{OUT}
) that is inversely proportional to the input voltage (
V
_{IN}
).
Figures 1
and
2
show the schematic and operation of the 1/
x
circuit, respectively. Initially, the capacitor
C
_{SH1}
samples and holds
V
_{IN}
by the reset signal so that the voltage of
C
_{SH1}
(
V
_{SH1}
) is updated to
V
_{IN}
. The reset signal also discharges the capacitors
C
_{A}
and
C
_{B}
to the ground. The input voltage
V
_{IN}
is converted to a current
I
_{IN}
by an operational amplifier, a resistor
R
_{A}
, and a current mirror. The current
I
_{IN}
charges capacitor
C
_{A}
during the capacitor charging time (
T
_{CHG}
) until the voltage of
C
_{A}
(
V
_{A}
) reaches the reference voltage (
V
_{REF}
). When
V
_{A}
=
V
_{REF}
, the charge stored in
C
_{A}
(
Q
_{A}
=
C
_{A}
×
V
_{REF}
) is equal to the product of
I
_{IN}
and
T
_{CHG}
.
Schematic of proposed 1/x circuit.
Operation of proposed 1/x circuit.
(1) $${V}_{\text{SH}1}={V}_{\text{IN}},$$
(2) $${I}_{\text{IN}}={V}_{\text{SH}1}/{R}_{\text{A}}={V}_{\text{IN}}/{R}_{\text{A}},$$
(3) $${Q}_{\text{A}}={C}_{\text{A}}\times {V}_{\text{REF}}={I}_{\text{IN}}\times {T}_{\text{CHG}}.$$
From equations (2) and (3), the capacitor charging time (
T
_{CHG}
) is expressed as follows:
(4) $${T}_{\text{CHG}}=\frac{{C}_{\text{A}}\times {V}_{\text{REF}}}{{I}_{\text{IN}}}=\frac{{R}_{\text{A}}\times {C}_{\text{A}}\times {V}_{\text{REF}}}{{V}_{\text{IN}}}.$$
A reference current (
I
_{REF}
=
V
_{REF}
/
R
_{B}
) is generated from the reference voltage (
V
_{REF}
) by an operational amplifier and a resistor
R
_{B}
. In the current-adjusting circuit in
Fig. 3
, the reference current (
I
_{REF}
) is multiplied by
M
for a current
I
_{B}
(=
M
×
I
_{REF}
) using a binary weighted current mirror and
N
-bit digital control code (CNT[1:
N
]).
Current-adjusting circuit.
(5) $${I}_{\text{B}}=M\times {I}_{\text{REF}}=M\times \frac{{V}_{\text{REF}}}{{R}_{\text{B}}},\text{\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}where\hspace{0.17em}\hspace{0.17em}}M={\displaystyle \sum}_{1}^{N}\frac{1}{{2}^{K}}\text{CNT}[K].$$
During
T
_{CHG}
, the switch (SW) turns on, and the current
I
_{B}
charges capacitor
C
_{B}
such that the charge stored in
C
_{B}
(
Q
_{B}
=
C
_{B}
×
V
_{B_MAX}
) becomes the product of
I
_{B}
and
T
_{CHG}
, where
V
_{B_MAX}
is the maximum voltage of
C
_{B}
after the capacitor charging operation.
(6) $${Q}_{\text{B}}={I}_{\text{B}}\times {T}_{\text{CHG}}={C}_{\text{B}}\times {V}_{\text{B}\_\text{MAX}}.$$
From equations (4), (5), and (6),
V
_{B_MAX}
is expressed as follows:
(7) $${V}_{\text{B}\_\text{MAX}}=\frac{{I}_{\text{B}}\times {T}_{\text{CHG}}}{{C}_{\text{B}}}=M\times \frac{{R}_{\text{A}}}{{R}_{\text{B}}}\times \frac{{C}_{\text{A}}}{{C}_{\text{B}}}\times \frac{{V}_{\text{REF}}^{2}}{{V}_{\text{IN}}},$$
where
R
_{A}
=
R
_{B}
and
C
_{A}
=
C
_{B}
;
V
_{B_MAX}
can be simplified as follows:
(8) $${V}_{\text{B}\_\text{MAX}}=M\times \frac{{V}_{\text{REF}}^{2}}{{V}_{\text{IN}}}.$$
Here,
V
_{B_MAX}
is inversely proportional to
V
_{IN}
, which is a function of 1/
x
. The tunable-gain 1/
x
circuit is achieved by changing the value of
M
of the current-adjusting circuit.
Although
V
_{B_MAX}
is inversely proportional to
V
_{IN}
,
V
_{B}
changes during the capacitor charging operation. A sampling circuit composed of a sampling switch and a capacitor is used for the continuous output voltage of the 1/
x
function. After every capacitor charging operation, the capacitor
C
_{SH2}
samples and holds
V
_{B_MAX}
by the SH (sample-and-hold) signal. If
C
_{SH2}
is much smaller than
C
_{B}
, then the voltage of
C
_{SH2}
(
V
_{SH2}
) becomes
V
_{B_MAX}
.
(9) $${V}_{\text{SH}2}={V}_{\text{B}\_\text{MAX}}.$$
An output-voltage generator with an operational amplifier, a current mirror, and two resistors (
R
_{SH}
and
R
_{OUT}
) is designed, because the minimum output voltage of the 1/
x
circuit is 0 V. The designed output-voltage generator makes 0 V easily by reducing the current going through the resistor
R
_{OUT}
. The output current (
I
_{OUT}
) is
K
-times larger than
I
_{SH}
(=
V
_{SH2}
/
R
_{SH}
). The output voltage (
V
_{OUT}
) is expressed as follows:
(10) $${V}_{\text{OUT}}=K\times \frac{{R}_{\text{OUT}}}{{R}_{\text{SH}}}\times {V}_{\text{SH}2}.$$
From equations (8), (9), and (10),
V
_{OUT}
is simplified as follows:
(11) $${V}_{\text{OUT}}=M\times \frac{{V}_{\text{REF}}^{2}}{{V}_{\text{IN}}},\text{\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}where\hspace{0.17em}}{R}_{\text{SH}}=K\times {R}_{\text{OUT}}.$$
When a resistive load is connected to the output node,
V
_{OUT}
changes in such a way that an additional voltage buffer is required. However, in many applications, the 1/
x
circuit has a high-impedance output; thus, no voltage buffer is required, because the 1/
x
circuit drives the other circuits in the same chip.
Figure 4
shows the waveforms of the 1/
x
circuit when the input voltage (
V
_{IN}
) changes. The current
I
_{IN}
charging the capacitor
C
_{A}
is proportional to
V
_{IN}
such that the charging time (
T
_{CHG}
) is inversely proportional to
V
_{IN}
when the voltage of
C
_{A}
(
V
_{A}
) reaches
V
_{REF}
. Therefore, the maximum voltage of
C
_{B}
(
V
_{B_MAX}
) is also inversely proportional to
V
_{IN}
, because
C
_{B}
is charged with a constant current
I
_{B}
during
T
_{CHG}
. The output voltage (
V
_{OUT}
) becomes a continuous voltage that is inversely proportional to
V
_{IN}
by sampling
V
_{B_MAX}
every clock cycle.
Waveforms of 1/x circuit.
From equations (7), (9), and (10), the output voltage of the 1/
x
circuit is expressed as follows:
(12) $${V}_{\text{OUT}}=M\times K\times \frac{{R}_{\text{OUT}}}{{R}_{\text{SH}}}\times \frac{{R}_{\text{A}}}{{R}_{\text{B}}}\times \frac{{C}_{\text{A}}}{{C}_{\text{B}}}\times \frac{{V}_{\text{REF}}^{2}}{{V}_{\text{IN}}}.$$
The 1/
x
circuit was implemented with a 0.18 μm CMOS process at
V
_{DD}
= 1.8 V. By applying the design parameters in
Table 1
, (12) can be simplified as follows:
(13) $${V}_{\text{OUT}}=\frac{\text{Gain}}{{V}_{\text{IN}}},\text{\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}\hspace{0.17em}where\hspace{0.17em}\hspace{0.17em}Gain}=\frac{M}{4}\times {V}_{\text{REF}}^{2}.$$

The gain is controlled by the parameters
M
and
V
_{REF}
. The parameter
M
can be changed between “0” and “1” by the 10-bit digital control code (CNT[1:10]), and the reference voltage
V
_{REF}
can be changed between 0.1 V and 1 V. Therefore, the allowable range of the gain of the 1/
x
circuit is from “0” to “1.”
Figures 5(a)
and
5(b)
show the simulation results of the 1/
x
circuit at
M
= 0.25 and
V
_{REF}
= 0.8 V. The 1/
x
circuit has errors less than 0.5% and 1.5% for
V
_{IN}
= 0.1 V to 0.8 V and
V
_{IN}
= 0.05 V to 0.8 V, respectively. The error increases when
V
_{IN}
is under 0.1 V, because the offset voltages of the amplifiers become the more dominant factors as
V
_{IN}
decreases.
Figure 5(c)
shows the gain variations of the 1/
x
circuit according to
M
at
V
_{REF}
= 0.8 V. The simulation results in
Table 2
show the high accuracy and wide input and output ranges of the 1/
x
circuit.
Simulation results of 1/x circuit at M = 0.25 and V _{REF} = 0.8 V: (a) V _{OUT} vs. V _{IN}, (b) accuracy of V _{OUT}, and (c) V _{OUT} vs. M .

In (12), the output of the proposed 1/
x
circuit is independent of the process parameters. However, the output is still affected by the mismatches of the devices. The main error sources are the offset voltages of amplifiers (AMPs), the mismatches of current mirrors, resistor mismatches (
R
_{A}
and
R
_{B}
,
R
_{OUT}
and
R
_{SH}
), and capacitor mismatches (
C
_{A}
and
C
_{B}
). In addition, the output is affected by the reference voltage (
V
_{REF}
). The reference voltage comes from either an internal bandgap reference (BGR) circuit or an external voltage source. In this design,
V
_{REF}
comes from an external voltage source so as to exhibit the variations of the 1/
x
circuit exactly.
Table 3
shows the Monte Carlo simulation results of the error sources in the implemented 1/
x
circuit with a 0.18 μm CMOS process. The standard deviation (
σ
) of the total error is 1.45%. The largest error comes from the AMPs (
σ
= 0.7%).

The maximum clock frequency (
f
_{CLK}
) for the voltage conversion of the 1/
x
circuit is determined by the capacitor charging time (
T
_{CHG}
=
R
_{A}
×
C
_{A}
×
V
_{REF}
/
V
_{IN}
) in (4). When
R
_{A}
= 40 kΩ,
C
_{A}
= 1 pF, and
V
_{REF}
= 0.8 V, the maximum capacitor charging time becomes 0.64 μs for the lowest allowable input voltage (
V
_{IN}
= 0.05 V). In the simulations and experiments, a clock frequency of 1 MHz was used to cover the 0.64 μs capacitor charging time. A higher clock frequency can be used by reducing the maximum capacitor charging time with the parameters
R
_{A}
,
C
_{A}
, and
V
_{REF}
. A lower clock frequency is recommended to save power consumption, because power consumption is proportional to the conversion frequency. The small capacitors (
C
_{A}
= 1 pF,
C
_{B}
= 1 pF, and
C
_{SH}
= 0.1 pF) are implemented to reduce power consumption and chip area, but they are weak from leakage currents and noises, which increase the error of the 1/
x
circuit. The larger capacitors,
C
_{A}
,
C
_{B}
, and
C
_{SH}
, can improve the accuracy of the 1/
x
circuit.
x
circuit was fabricated using a 0.18 μm CMOS process.
Figure 6
shows a microphotograph of the chip. The chip occupies an area of 0.011 mm
^{2}
(144 μm × 78 μm) and consumes 278 μW at
V
_{DD}
= 1.8 V and
f
_{CLK}
= 1 MHz.
Figure 7
shows the measured waveforms of
V
_{OUT}
according to
V
_{IN}
(= 0 V to 1 V) at
V
_{REF}
= 0.8 V and
M
= 0.5, 0.25, and 0.125. The function of the proposed 1/
x
circuit does not have any process parameters theoretically, but the output voltage of the proposed 1/
x
circuit is affected by process variations, such as the offset voltages of the AMPs; the switching delays of the AMPs; and the mismatches in capacitors, resistors, and current mirrors.
Figure 8
shows the measured distribution of
V
_{OUT}
for 20 untrimmed sample chips at
V
_{IN}
= 0.2 V,
M
= 0.25, and
V
_{REF}
= 0.8 V. The
V
_{OUT}
of each chip is measured at
V
_{IN}
= 0.2 V to show the distribution of
V
_{OUT}
according to process variations. Theoretically,
V
_{OUT}
= 0.2 V at
V
_{IN}
= 0.2 V, because the function of the 1/
x
circuit is
V
_{OUT}
= 0.04/
V
_{IN}
at
M
= 0.25 and
V
_{REF}
= 0.8 V. The mean (
μ
) and standard deviation (
σ
) of
V
_{OUT}
for 20 samples were 200 mV and 3.21 mV (1.61%), respectively. The measured 20 sample chips showed a maximum and minimum
V
_{OUT}
of 205.7 mV and 194.7 mV, respectively. Therefore, the maximum difference of
V
_{OUT}
(Δ
V
_{OUT}
) was 11 mV (5.48%). The change in
V
_{OUT}
due to the process variations can be trimmed by the current-adjusting circuit.
Figure 9
shows the measured accuracies of
V
_{OUT}
for 20 trimmed sample chips at
M
= 0.25 and
V
_{REF}
= 0.8 V. The 20 trimmed 1/
x
circuits have errors between +1.7% and −1.7% for
V
_{IN}
= 0.05 V to 0.8 V.
Microphotograph of chip.
Measured waveforms of V _{OUT} vs. V _{IN} (= 0 V to 1 V) at V _{REF} = 0.8 V: (a) M = 0.5, (b) M = 0.25, and (c) M = 0.125.
Measured distribution of V _{OUT} for 20 untrimmed sample chips at V _{IN} = 0.2 V, M = 0.25, and V _{REF} = 0.8 V.
Measured accuracies of V _{OUT} for 20 trimmed sample chips at M = 0.25 and V _{REF} = 0.8 V.
Various 1/
x
circuit chips are compared in
Table 4
. The proposed 1/
x
circuit has a larger normalized input/output range of 1 to 20 compared to other 1/
x
circuits (from 1 to 2.67 to 1 to 14). The normalized input/output range is the lowest value among the input and output ranges normalized with their minimum values. The previous 1/
x
circuits
[3]
–
[5]
have smaller errors of 1.7%. However, all previous 1/x circuits
[3]
–
[6]
have additional linearity errors due to PVT (process parameters, supply voltage, temperature) variations, as shown in
Table 5
. The additional linearity errors come from the parameters
K
(=
μC
_{OX}
W
/
L
),
g
_{m}
(=
V
_{T}
of the MOSFET. In the 0.18 μm CMOS process, the maximum process variations of
K
, g
_{m}
, and
V
_{T}
are 21%, 10%, and 20%, respectively. But, theoretically, the proposed 1/
x
circuit is not affected by the parameters (
K
, g
_{m}
, and
V
_{T}
) because all parameters are removed from the equation of its function. Therefore, the additional linearity errors with PVT variations in
[3]
–
[6]
will be much larger than the linearity errors (±1.7%) of the proposed 1/
x
circuit.

* Maximum bandwidth is equal to half of the sampling frequency, according to Nyquist theorem.

* K (= μC _{OX}W /L ) and ${g}_{\text{m}}\left(=\sqrt{2K{I}_{\text{D}}}\right)$ are the transconductance parameters of MOSFET, and V _{T} is the threshold voltage of MOSFET.
The proposed 1/
x
circuit is slower than previous circuits
[3]
and [5], because its operation is based on the signal sampling and the charge integration on capacitors. Its bandwidth (0.5 MHz) is considered to be half of the sampling frequency (1 MHz), according to Nyquist theorem. The bandwidth under 0.5 MHz is adequate for low-speed applications using the 1/
x
function. The analog dividers used in most instrumentation and control applications need a bandwidth of under 1 kHz
[1]
. A hearing-aid system
[2]
needs a bandwidth of 16 kHz.
x
circuit was proposed. The output voltage of the 1/
x
circuit is generated using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The 1/
x
circuit achieved low linearity errors and wide input and output voltages by using low offset amplifiers and by matching the capacitors, resistors, and current mirrors well. The voltage gain of the 1/
x
circuit is tuned by a 10-bit digital code. The 1/
x
circuit was fabricated using a 0.18 μm CMOS process. Its core area is 0.011 mm
^{2}
(144 μm × 78 μm), and it consumes 278 μW at
V
_{DD}
= 1.8 V and
f
_{CLK}
= 1 MHz. Its linearity error is within 1.7% at
V
_{IN}
= 0.05 V to 1 V.
This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2015R1D1A3A01017756). The chip fabrication was supported by the IC Design Education Center (IDEC).
bdyang@cbnu.ac.kr
Byung-Do Yang received his BS, MS, and PhD degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1999, 2001, and 2005, respectively. He was a senior engineer at the Memory Division, Samsung Electronics, Hwaseong, Rep. of Korea, in 2005, where he was involved in the design of DRAM. Since 2006, he has been at Chungbuk National University, Cheongju, Rep. of Korea, where he is now an associate professor. His research interests include analog circuits, memory circuits, and power IC designs.
Corresponding Author seoweon.heo@hongik.ac.kr
Seo Weon Heo received his BS and MS degrees in electronic engineering from Seoul National University, Rep. of Korea, in 1990 and 1992, respectively, and his PhD degree in electrical engineering from Purdue University, West Lafayette, IN, USA, in 2001. From 1992 to 1998, he was with the Digital Media Research Laboratory, LG Electronics Co., Ltd., Seoul, Rep. of Korea. From 2001 to 2006, he worked at the Telecommunication R&D Center, Samsung Electronics Co., Ltd., Hwaseong, Rep. of Korea. Since 2006, he has been an associate professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Rep. of Korea. His current research interests include signal processing, wireless communication, and embedded system design.

I. Introduction

The analog 1/
II. Proposed 1/xCircuit

The proposed 1/
PPT Slide

Lager Image

PPT Slide

Lager Image

PPT Slide

Lager Image

PPT Slide

Lager Image

Design and adjustable parameters of 1/xcircuit.

_{A} = 1 pF, _{B} = 1 pF, _{SH} = 0.1 pF | |

_{A} = 40 kΩ, _{B} = 160 kΩ | |

_{OUT} = 10 kΩ, _{SH} = 50 kΩ | |

_{REF} = 0.1 V–1 V | |

0–1 |

PPT Slide

Lager Image

Simulation results of 1/xcircuit.

0.18 μm CMOS | |

_{DD}) | 1.8 V |

_{CLK}) | 1 MHz |

_{IN}) | 0.05 V–0.8 V |

_{OUT}) | 0 V–1 V |

_{OUT} | − 0.5% < Error < 0.5% for _{IN} = 0.1 V–0.8 V |

− 1.5% < Error < 0.5% for _{IN} = 0.05 V–0.8 V | |

_{OUT} = 0.04/_{IN}@ _{REF} = 0.8 V |

Error sources of 1/xcircuit.

Source | Number | Standard deviation ( |
---|---|---|

Offset voltage of amplifier | 4 | 0.7% (1.4 mV @ _{IN} = 0.2 V) |

Mismatch of current mirror | 3 | 0.18% |

Resistor mismatch | 2 | 0.07% |

Capacitor mismatch | 1 | 0.07% |

Total error | N/A | 1.45% |

III. Measurement Results

The proposed 1/
PPT Slide

Lager Image

PPT Slide

Lager Image

PPT Slide

Lager Image

PPT Slide

Lager Image

2K I D

), and
Performance comparisons of various 1/xcircuit chips.

JSSC 1995 | IEICE 2003 | TCAS-II 2005 | MWCAS 2012 | This work | |
---|---|---|---|---|---|

Process | 2 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS | 0.5 μm CMOS | 0.18 μm CMOS |

_{DD} (V) | 5 | 1.5 | 1.5 | 1.5 | 1.8 |

_{SS} (V) | −5 | −1.5 | −1.5 | −1.5 | 0 |

Power (μW) | N/A | 240 | 220 | 80 | 278 |

Area (mm^{2}) | N/A | N/A | N/A | 0.032 | 0.011 |

_{IN} (V) | 0.3–0.8 | 0.1–1.5 | – | −0.4–0.4 | 0.05–1 |

_{OUT} (V) | 0.1–0.3 | 0.2–1.5 | 0.1–1.4 | −0.2–0.2 (sim.) | 0–0.9 |

_{IN} (μA) | – | – | 1–70 | – | – |

_{OUT} (μA) | – | – | – | −50–50 | – |

Bandwidth | 9 MHz (sim.) | N/A | 100 MHz | 175 kHz (sim.) | 0.5 MHz* |

Sampling frequency | – | – | – | – | 1 MHz |

Normalized input/output range | 1–2.667 | 1–7.5 | 1–14 | N/A | 1–20 |

Number of samples | 1 | 1 | 1 | 1 | 20 |

Linearity errors | ±1% (sim.) | ±1% | ±0.85% | N/A | ±1.7% |

Linearity error sources of PVT variations.

Function | Measurement conditions | Linearity error sources | |
---|---|---|---|

JSSC 1995 | _{C} = 0.5 V | _{A} (21%) _{m} (10%) | |

IEICE 2003 | _{C} = 10 μA–20 μA | _{N} (21%) | |

TCAS-II 2005 | _{N} = 0 μA–30 μA | _{P} (21%) _{N} (21%) _{T} (20%) | |

MWCAS 2012 | Δ_{N} = 0.3 | _{N} (21%) | |

This work | _{REF} = 0.8 V | - |

IV. Conclusion

An accurate tunable-gain 1/
BIO

Laopoulos T.L.
,
Karybakas C.A.
1991
“A Simple Analog Division Scheme,”
IEEE Trans. Instrum. Meas.
40
(4)
779 -
782
** DOI : 10.1109/19.85354**

van de Gevel M.
,
Kuenen J.C.
1994
“Simple Low-Voltage Weak Inversion MOS 1/x Circuit,”
Electron. Lett.
30
(20)
1639 -
1640
** DOI : 10.1049/el:19941170**

Liu S.-I.
,
Chang C.-C.
1995
“CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits,”
IEEE J. Solid-State Circuits
30
(9)
1025 -
1029
** DOI : 10.1109/4.406403**

Liu W.
,
Liu S.-I.
2003
“CMOS Tunable 1/x Circuit and its Applications,”
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
E86-A
(7)
1896 -
1899

Liu W.
,
Liu S.-I.
,
Wei S.-K.
2005
“CMOS Current-Mode Divider and its Applications,”
IEEE Trans. Circuits Syst. II: Exp. Briefs
52
(3)
145 -
148
** DOI : 10.1109/TCSII.2004.842041**

Padilla-Cantoya I.
“Compact Low-Voltage CMOS Analog Divider Using a Four-Quadrant Multiplier and Biasing Control Circuit,”
IEEE Int. Midwest Symp. Circuits Syst.
Boise, ID, USA
Aug. 5–8, 2012
502 -
505

Citing 'Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme
'

@article{ HJTODO_2015_v37n5_972}
,title={Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme}
,volume={5}
, url={http://dx.doi.org/10.4218/etrij.15.0114.0577}, DOI={10.4218/etrij.15.0114.0577}
, number= {5}
, journal={ETRI Journal}
, publisher={Electronics and Telecommunications Research Institute}
, author={Yang, Byung-Do
and
Heo, Seo Weon}
, year={2015}
, month={Oct}