Advanced
Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme
Accurate Tunable-Gain 1/x Circuit Using Capacitor Charging Scheme
ETRI Journal. 2015. Oct, 37(5): 972-978
Copyright © 2015, Electronics and Telecommunications Research Institute (ETRI)
  • Received : May 13, 2014
  • Accepted : January 02, 2015
  • Published : October 01, 2015
Download
PDF
e-PUB
PubReader
PPT
Export by style
Share
Article
Author
Metrics
Cited by
TagCloud
About the Authors
Byung-Do Yang
Seo Weon Heo

Abstract
This paper proposes an accurate tunable-gain 1/ x circuit. The output voltage of the 1/ x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of the process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The voltage gain of the 1/ x circuit is tuned by a 10-bit digital code. The 1/ x circuit was fabricated using a 0.18 μm CMOS process. Its core area is 0.011 mm 2 (144 μm × 78 μm), and it consumes 278 μW at V DD = 1.8 V and f CLK = 1 MHz. Its error is within 1.7% at V IN = 0.05 V to 1 V.
Keywords
I. Introduction
The analog 1/ x circuit is used in analog dividers, filters, fuzzy control, neural networks, and A/D converters [1] [6] . Several circuits for the 1/ x function have been proposed. A voltage-mode analog divider is accurate, but it needs a highly accurate wide-range voltage controlled oscillator [1] . A current-mode 1/ x circuit using weak-inversion MOSFETs has low accuracy due to very low reference and input currents, which are only under a few nanoamperes [2] . A voltage-mode analog divider [3] , voltage-mode 1/ x circuit [4] , and current-mode analog divider [5] have good accuracy; however, their outputs significantly change due to device parameters and temperature.
In this paper, an accurate tunable-gain 1/ x circuit is proposed. The output voltage of the 1/ x circuit is generated by using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of process parameters, because all variations from active and passive devices are canceled out. In addition, the voltage gain of the 1/ x circuit is tuned by a 10-bit digital input code.
The rest of this paper is organized as follows. Section II describes the proposed tunable-gain 1/ x circuit. Section III shows the measurement results of the fabricated chip. Finally, conclusions are drawn in Section IV.
II. Proposed 1/xCircuit
The proposed 1/ x circuit generates an output voltage ( V OUT ) that is inversely proportional to the input voltage ( V IN ). Figures 1 and 2 show the schematic and operation of the 1/ x circuit, respectively. Initially, the capacitor C SH1 samples and holds V IN by the reset signal so that the voltage of C SH1 ( V SH1 ) is updated to V IN . The reset signal also discharges the capacitors C A and C B to the ground. The input voltage V IN is converted to a current I IN by an operational amplifier, a resistor R A , and a current mirror. The current I IN charges capacitor C A during the capacitor charging time ( T CHG ) until the voltage of C A ( V A ) reaches the reference voltage ( V REF ). When V A = V REF , the charge stored in C A ( Q A = C A × V REF ) is equal to the product of I IN and T CHG .
PPT Slide
Lager Image
Schematic of proposed 1/x circuit.
PPT Slide
Lager Image
Operation of proposed 1/x circuit.
V SH1 = V IN ,
I IN = V SH1 / R A = V IN / R A ,
Q A = C A × V REF = I IN × T CHG .
From equations (2) and (3), the capacitor charging time ( T CHG ) is expressed as follows:
T CHG = C A × V REF I IN = R A × C A × V REF V IN .
A reference current ( I REF = V REF / R B ) is generated from the reference voltage ( V REF ) by an operational amplifier and a resistor R B . In the current-adjusting circuit in Fig. 3 , the reference current ( I REF ) is multiplied by M for a current I B (= M × I REF ) using a binary weighted current mirror and N -bit digital control code (CNT[1: N ]).
PPT Slide
Lager Image
Current-adjusting circuit.
I B =M× I REF =M× V REF R B ,    where  M= 1 N 1 2 K CNT[K].
During T CHG , the switch (SW) turns on, and the current I B charges capacitor C B such that the charge stored in C B ( Q B = C B × V B_MAX ) becomes the product of I B and T CHG , where V B_MAX is the maximum voltage of C B after the capacitor charging operation.
Q B = I B × T CHG = C B × V B_MAX .
From equations (4), (5), and (6), V B_MAX is expressed as follows:
V B_MAX = I B × T CHG C B =M× R A R B × C A C B × V REF 2 V IN ,
where R A = R B and C A = C B ; V B_MAX can be simplified as follows:
V B_MAX =M× V REF 2 V IN .
Here, V B_MAX is inversely proportional to V IN , which is a function of 1/ x . The tunable-gain 1/ x circuit is achieved by changing the value of M of the current-adjusting circuit.
Although V B_MAX is inversely proportional to V IN , V B changes during the capacitor charging operation. A sampling circuit composed of a sampling switch and a capacitor is used for the continuous output voltage of the 1/ x function. After every capacitor charging operation, the capacitor C SH2 samples and holds V B_MAX by the SH (sample-and-hold) signal. If C SH2 is much smaller than C B , then the voltage of C SH2 ( V SH2 ) becomes V B_MAX .
V SH2 = V B_MAX .
An output-voltage generator with an operational amplifier, a current mirror, and two resistors ( R SH and R OUT ) is designed, because the minimum output voltage of the 1/ x circuit is 0 V. The designed output-voltage generator makes 0 V easily by reducing the current going through the resistor R OUT . The output current ( I OUT ) is K -times larger than I SH (= V SH2 / R SH ). The output voltage ( V OUT ) is expressed as follows:
V OUT =K× R OUT R SH × V SH2 .
From equations (8), (9), and (10), V OUT is simplified as follows:
V OUT =M× V REF 2 V IN ,      where   R SH =K× R OUT .
When a resistive load is connected to the output node, V OUT changes in such a way that an additional voltage buffer is required. However, in many applications, the 1/ x circuit has a high-impedance output; thus, no voltage buffer is required, because the 1/ x circuit drives the other circuits in the same chip.
Figure 4 shows the waveforms of the 1/ x circuit when the input voltage ( V IN ) changes. The current I IN charging the capacitor C A is proportional to V IN such that the charging time ( T CHG ) is inversely proportional to V IN when the voltage of C A ( V A ) reaches V REF . Therefore, the maximum voltage of C B ( V B_MAX ) is also inversely proportional to V IN , because C B is charged with a constant current I B during T CHG . The output voltage ( V OUT ) becomes a continuous voltage that is inversely proportional to V IN by sampling V B_MAX every clock cycle.
PPT Slide
Lager Image
Waveforms of 1/x circuit.
From equations (7), (9), and (10), the output voltage of the 1/ x circuit is expressed as follows:
V OUT =M×K× R OUT R SH × R A R B × C A C B × V REF 2 V IN .
The 1/ x circuit was implemented with a 0.18 μm CMOS process at V DD = 1.8 V. By applying the design parameters in Table 1 , (12) can be simplified as follows:
V OUT = Gain V IN ,     where  Gain= M 4 × V REF 2 .
Design and adjustable parameters of 1/xcircuit.
Design parameters CA = 1 pF, CB = 1 pF, CSH = 0.1 pF
RA = 40 kΩ, RB = 160 kΩ
K = 5, ROUT = 10 kΩ, RSH = 50 kΩ
Adjustable parameters M = 0–1 for CNT[1:8]
VREF = 0.1 V–1 V
Gain 0–1
The gain is controlled by the parameters M and V REF . The parameter M can be changed between “0” and “1” by the 10-bit digital control code (CNT[1:10]), and the reference voltage V REF can be changed between 0.1 V and 1 V. Therefore, the allowable range of the gain of the 1/ x circuit is from “0” to “1.”
Figures 5(a) and 5(b) show the simulation results of the 1/ x circuit at M = 0.25 and V REF = 0.8 V. The 1/ x circuit has errors less than 0.5% and 1.5% for V IN = 0.1 V to 0.8 V and V IN = 0.05 V to 0.8 V, respectively. The error increases when V IN is under 0.1 V, because the offset voltages of the amplifiers become the more dominant factors as V IN decreases. Figure 5(c) shows the gain variations of the 1/ x circuit according to M at V REF = 0.8 V. The simulation results in Table 2 show the high accuracy and wide input and output ranges of the 1/ x circuit.
PPT Slide
Lager Image
Simulation results of 1/x circuit at M = 0.25 and VREF = 0.8 V: (a) VOUT vs. VIN, (b) accuracy of VOUT, and (c) VOUT vs. M.
Simulation results of 1/xcircuit.
Process 0.18 μm CMOS
Supply voltage (VDD) 1.8 V
Clock frequency (fCLK) 1 MHz
Input voltage (VIN) 0.05 V–0.8 V
Output voltage (VOUT) 0 V–1 V
Accuracy of VOUT − 0.5% < Error < 0.5% for VIN = 0.1 V–0.8 V
− 1.5% < Error < 0.5% for VIN = 0.05 V–0.8 V
Simulation conditions VOUT = 0.04/VIN@ M = 0.25, VREF = 0.8 V
In (12), the output of the proposed 1/ x circuit is independent of the process parameters. However, the output is still affected by the mismatches of the devices. The main error sources are the offset voltages of amplifiers (AMPs), the mismatches of current mirrors, resistor mismatches ( R A and R B , R OUT and R SH ), and capacitor mismatches ( C A and C B ). In addition, the output is affected by the reference voltage ( V REF ). The reference voltage comes from either an internal bandgap reference (BGR) circuit or an external voltage source. In this design, V REF comes from an external voltage source so as to exhibit the variations of the 1/ x circuit exactly. Table 3 shows the Monte Carlo simulation results of the error sources in the implemented 1/ x circuit with a 0.18 μm CMOS process. The standard deviation ( σ ) of the total error is 1.45%. The largest error comes from the AMPs ( σ = 0.7%).
Error sources of 1/xcircuit.
Source Number Standard deviation (σ)
Offset voltage of amplifier 4 0.7% (1.4 mV @ VIN = 0.2 V)
Mismatch of current mirror 3 0.18%
Resistor mismatch 2 0.07%
Capacitor mismatch 1 0.07%
Total error N/A 1.45%
The maximum clock frequency ( f CLK ) for the voltage conversion of the 1/ x circuit is determined by the capacitor charging time ( T CHG = R A × C A × V REF / V IN ) in (4). When R A = 40 kΩ, C A = 1 pF, and V REF = 0.8 V, the maximum capacitor charging time becomes 0.64 μs for the lowest allowable input voltage ( V IN = 0.05 V). In the simulations and experiments, a clock frequency of 1 MHz was used to cover the 0.64 μs capacitor charging time. A higher clock frequency can be used by reducing the maximum capacitor charging time with the parameters R A , C A , and V REF . A lower clock frequency is recommended to save power consumption, because power consumption is proportional to the conversion frequency. The small capacitors ( C A = 1 pF, C B = 1 pF, and C SH = 0.1 pF) are implemented to reduce power consumption and chip area, but they are weak from leakage currents and noises, which increase the error of the 1/ x circuit. The larger capacitors, C A , C B , and C SH , can improve the accuracy of the 1/ x circuit.
III. Measurement Results
The proposed 1/ x circuit was fabricated using a 0.18 μm CMOS process. Figure 6 shows a microphotograph of the chip. The chip occupies an area of 0.011 mm 2 (144 μm × 78 μm) and consumes 278 μW at V DD = 1.8 V and f CLK = 1 MHz. Figure 7 shows the measured waveforms of V OUT according to V IN (= 0 V to 1 V) at V REF = 0.8 V and M = 0.5, 0.25, and 0.125. The function of the proposed 1/ x circuit does not have any process parameters theoretically, but the output voltage of the proposed 1/ x circuit is affected by process variations, such as the offset voltages of the AMPs; the switching delays of the AMPs; and the mismatches in capacitors, resistors, and current mirrors. Figure 8 shows the measured distribution of V OUT for 20 untrimmed sample chips at V IN = 0.2 V, M = 0.25, and V REF = 0.8 V. The V OUT of each chip is measured at V IN = 0.2 V to show the distribution of V OUT according to process variations. Theoretically, V OUT = 0.2 V at V IN = 0.2 V, because the function of the 1/ x circuit is V OUT = 0.04/ V IN at M = 0.25 and V REF = 0.8 V. The mean ( μ ) and standard deviation ( σ ) of V OUT for 20 samples were 200 mV and 3.21 mV (1.61%), respectively. The measured 20 sample chips showed a maximum and minimum V OUT of 205.7 mV and 194.7 mV, respectively. Therefore, the maximum difference of V OUT V OUT ) was 11 mV (5.48%). The change in V OUT due to the process variations can be trimmed by the current-adjusting circuit. Figure 9 shows the measured accuracies of V OUT for 20 trimmed sample chips at M = 0.25 and V REF = 0.8 V. The 20 trimmed 1/ x circuits have errors between +1.7% and −1.7% for V IN = 0.05 V to 0.8 V.
PPT Slide
Lager Image
Microphotograph of chip.
PPT Slide
Lager Image
Measured waveforms of VOUT vs. VIN (= 0 V to 1 V) at VREF = 0.8 V: (a) M = 0.5, (b) M = 0.25, and (c) M = 0.125.
PPT Slide
Lager Image
Measured distribution of VOUT for 20 untrimmed sample chips at VIN = 0.2 V, M = 0.25, and VREF = 0.8 V.
PPT Slide
Lager Image
Measured accuracies of VOUT for 20 trimmed sample chips at M = 0.25 and VREF = 0.8 V.
Various 1/ x circuit chips are compared in Table 4 . The proposed 1/ x circuit has a larger normalized input/output range of 1 to 20 compared to other 1/ x circuits (from 1 to 2.67 to 1 to 14). The normalized input/output range is the lowest value among the input and output ranges normalized with their minimum values. The previous 1/ x circuits [3] [5] have smaller errors of 1.7%. However, all previous 1/x circuits [3] [6] have additional linearity errors due to PVT (process parameters, supply voltage, temperature) variations, as shown in Table 5 . The additional linearity errors come from the parameters K (= μC OX W / L ), g m (=
2K I D
), and V T of the MOSFET. In the 0.18 μm CMOS process, the maximum process variations of K , g m , and V T are 21%, 10%, and 20%, respectively. But, theoretically, the proposed 1/ x circuit is not affected by the parameters ( K , g m , and V T ) because all parameters are removed from the equation of its function. Therefore, the additional linearity errors with PVT variations in [3] [6] will be much larger than the linearity errors (±1.7%) of the proposed 1/ x circuit.
Performance comparisons of various 1/xcircuit chips.
JSSC 1995 [3] IEICE 2003 [4] TCAS-II 2005 [5] MWCAS 2012 [6] This work
Process 2 μm CMOS 0.5 μm CMOS 0.5 μm CMOS 0.5 μm CMOS 0.18 μm CMOS
VDD (V) 5 1.5 1.5 1.5 1.8
VSS (V) −5 −1.5 −1.5 −1.5 0
Power (μW) N/A 240 220 80 278
Area (mm2) N/A N/A N/A 0.032 0.011
VIN (V) 0.3–0.8 0.1–1.5 −0.4–0.4 0.05–1
VOUT (V) 0.1–0.3 0.2–1.5 0.1–1.4 −0.2–0.2 (sim.) 0–0.9
IIN (μA) 1–70
IOUT (μA) −50–50
Bandwidth 9 MHz (sim.) N/A 100 MHz 175 kHz (sim.) 0.5 MHz*
Sampling frequency 1 MHz
Normalized input/output range 1–2.667 1–7.5 1–14 N/A 1–20
Number of samples 1 1 1 1 20
Linearity errors ±1% (sim.) ±1% ±0.85% N/A ±1.7%
* Maximum bandwidth is equal to half of the sampling frequency, according to Nyquist theorem.
Linearity error sources of PVT variations.
Function Measurement conditions Linearity error sources
JSSC 1995 [3] V OUT = g m V C 4 K A V IN VC = 0.5 V KA (21%) gm (10%)
IEICE 2003 [4] V OUT = I C K N V IN IC = 10 μA–20 μA KN (21%)
TCAS-II 2005 [5] V OUT = 2 K P K N ( V DD V T ) I N I IN IN = 0 μA–30 μA KP (21%) KN (21%) VT (20%)
MWCAS 2012 [6] V OUT Δ V N K N Δ V IN ΔVN = 0.3 KN (21%)
This work V OUT =M V REF 2 V IN M = 0.25, VREF = 0.8 V -
* K (= μCOXW/L) and g m ( = 2K I D ) are the transconductance parameters of MOSFET, and VT is the threshold voltage of MOSFET.
The proposed 1/ x circuit is slower than previous circuits [3] and [5], because its operation is based on the signal sampling and the charge integration on capacitors. Its bandwidth (0.5 MHz) is considered to be half of the sampling frequency (1 MHz), according to Nyquist theorem. The bandwidth under 0.5 MHz is adequate for low-speed applications using the 1/ x function. The analog dividers used in most instrumentation and control applications need a bandwidth of under 1 kHz [1] . A hearing-aid system [2] needs a bandwidth of 16 kHz.
IV. Conclusion
An accurate tunable-gain 1/ x circuit was proposed. The output voltage of the 1/ x circuit is generated using a capacitor charging time that is inversely proportional to the input voltage. The output voltage is independent of process parameters, because the output voltage depends on the ratios of the capacitors, resistors, and current mirrors. The 1/ x circuit achieved low linearity errors and wide input and output voltages by using low offset amplifiers and by matching the capacitors, resistors, and current mirrors well. The voltage gain of the 1/ x circuit is tuned by a 10-bit digital code. The 1/ x circuit was fabricated using a 0.18 μm CMOS process. Its core area is 0.011 mm 2 (144 μm × 78 μm), and it consumes 278 μW at V DD = 1.8 V and f CLK = 1 MHz. Its linearity error is within 1.7% at V IN = 0.05 V to 1 V.
This research was supported by the Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2015R1D1A3A01017756). The chip fabrication was supported by the IC Design Education Center (IDEC).
BIO
bdyang@cbnu.ac.kr
Byung-Do Yang received his BS, MS, and PhD degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1999, 2001, and 2005, respectively. He was a senior engineer at the Memory Division, Samsung Electronics, Hwaseong, Rep. of Korea, in 2005, where he was involved in the design of DRAM. Since 2006, he has been at Chungbuk National University, Cheongju, Rep. of Korea, where he is now an associate professor. His research interests include analog circuits, memory circuits, and power IC designs.
Corresponding Author seoweon.heo@hongik.ac.kr
Seo Weon Heo received his BS and MS degrees in electronic engineering from Seoul National University, Rep. of Korea, in 1990 and 1992, respectively, and his PhD degree in electrical engineering from Purdue University, West Lafayette, IN, USA, in 2001. From 1992 to 1998, he was with the Digital Media Research Laboratory, LG Electronics Co., Ltd., Seoul, Rep. of Korea. From 2001 to 2006, he worked at the Telecommunication R&D Center, Samsung Electronics Co., Ltd., Hwaseong, Rep. of Korea. Since 2006, he has been an associate professor with the School of Electronic and Electrical Engineering, Hongik University, Seoul, Rep. of Korea. His current research interests include signal processing, wireless communication, and embedded system design.
References
Laopoulos T.L. , Karybakas C.A. 1991 “A Simple Analog Division Scheme,” IEEE Trans. Instrum. Meas. 40 (4) 779 - 782    DOI : 10.1109/19.85354
van de Gevel M. , Kuenen J.C. 1994 “Simple Low-Voltage Weak Inversion MOS 1/x Circuit,” Electron. Lett. 30 (20) 1639 - 1640    DOI : 10.1049/el:19941170
Liu S.-I. , Chang C.-C. 1995 “CMOS Analog Divider and Four-Quadrant Multiplier Using Pool Circuits,” IEEE J. Solid-State Circuits 30 (9) 1025 - 1029    DOI : 10.1109/4.406403
Liu W. , Liu S.-I. 2003 “CMOS Tunable 1/x Circuit and its Applications,” IEICE Trans. Fundam. Electron. Commun. Comput. Sci. E86-A (7) 1896 - 1899
Liu W. , Liu S.-I. , Wei S.-K. 2005 “CMOS Current-Mode Divider and its Applications,” IEEE Trans. Circuits Syst. II: Exp. Briefs 52 (3) 145 - 148    DOI : 10.1109/TCSII.2004.842041
Padilla-Cantoya I. “Compact Low-Voltage CMOS Analog Divider Using a Four-Quadrant Multiplier and Biasing Control Circuit,” IEEE Int. Midwest Symp. Circuits Syst. Boise, ID, USA Aug. 5–8, 2012 502 - 505