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250 mV Supply Voltage Digital Low-Dropout Regulator Using Fast Current Tracking Scheme
250 mV Supply Voltage Digital Low-Dropout Regulator Using Fast Current Tracking Scheme
ETRI Journal. 2015. Oct, 37(5): 961-971
Copyright © 2015, Electronics and Telecommunications Research Institute (ETRI)
  • Received : August 13, 2014
  • Accepted : January 02, 2015
  • Published : October 01, 2015
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About the Authors
Jae-Mun Oh
Byung-Do Yang
Hyeong-Ju Kang
Yeong-Seuk Kim
Ho-Yong Choi
Woo-Sung Jung

Abstract
This paper proposes a 250 mV supply voltage digital low-dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over-voltage and under-voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.
Keywords
I. Introduction
Recently, the high demand for handheld and portable devices with a long battery-runtime has driven research into low-voltage circuits, because the low-voltage operation of very-large-scale integration (VLSI) circuits is an effective method for reducing both dynamic and leakage power dissipation. The supply voltage of the VLSI circuits was reduced to a subthreshold voltage (for example, 180 mV FFT processor [1] and 200 mV SRAM [2] ).
For stable operations in such low-voltage circuits, a stable supply voltage needs to be provided. Analog low-dropout (LDO) regulators are used widely for supply voltage regulation due to their small area, low ripple voltage, and rapid transient response. The supply voltage of the analog LDO regulator was reduced to 650 mV [3] [6] . However, the supply voltage is still higher than the threshold voltage.
Digital LDO regulators were proposed for low-voltage regulation [7] [10] . The supply voltage was decreased to 380 mV. The digital LDO regulator supplies a current to the output load with all digital feedback control, as shown in Fig. 1 . The digital LDO regulator in [7] consists of a digital clocked comparator, a shift register–based controller, and a current switch array instead of an error amplifier and a power transistor in an analog LDO regulator. However, the shift register–based controller causes a large area and slow setting time of the output voltage.
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Block diagram of digital LDO regulator.
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Operations of digital LDO regulator with (a) voltage feedback control [7] and (b) proposed fast current tracking scheme.
In this paper, a 250 mV supply voltage digital LDO regulator using a fast current tracking scheme is proposed. The proposed LDO regulator consists of three comparators, a digital controller, and a current switch array. A comparator is used for the feedback control of the output voltage. The other comparators are used for the over-voltage and under-voltage detections to limit the overshoot (positive ripple) and undershoot (negative ripple) voltages of the output voltage. The controller with the fast current tracking scheme reduces the settling time of the output voltage by eliminating the ringing problem. The switch bias circuit in the current switch array reduces the size of the current switch array by applying a forward body bias voltage at low supply voltage. The proposed digital LDO regulator achieves a high current efficiency and low ripple voltage at 250 mV supply voltage.
The rest of this paper is organized as follows. Section II describes the architecture of the proposed digital LDO regulator. Section III shows the measurement results of the fabricated chip. Finally, conclusions are drawn in Section IV.
II. Proposed Digital LDO Regulator Architecture
- 1. Concept of Fast Current Tracking Scheme
Figure 1 shows a block diagram of a digital LDO regulator. The comparator compares the reference voltage ( V REF ) and the output voltage of the digital LDO regulator ( V OUT ). The digital controller determines the number of on-switches. The switch array supplies the current ( I SUPPLY ) from the power supply ( V IN ) to the output node with an external capacitor ( C EXT ) and a load current source ( I LOAD ).
Figure 2(a) shows the operations of the digital LDO regulator with the conventional voltage feedback control [7] . When I LOAD increases from I 1 to I 2 , V OUT decreases due to the current difference (Δ I ) between I LOAD (= I 2 ) and I SUPPLY (= I 1 ). The number of on-switches in the switch array continues to increase to supply more current ( I SUPPLY ). However, when V OUT = V REF , I SUPPLY becomes I 3 (= I 1 + 2 × Δ I ) and the current difference Δ I still exists. This causes the ringing problem in V OUT . In the simulation, when a variable current source is used for I LOAD , a ringing exists for a long time. When a variable resistor is used instead of the current source, a larger ringing exists but its magnitude decreases.
The proposed fast current tracking scheme provides the fast settling time of V OUT by eliminating the ringing problem, as shown in Fig. 2(b) . In this scheme, at every voltage crossing of V OUT and V REF , the update signal becomes “1” and the number of on-switches becomes the mean of the two on-switch numbers at the previous two voltage crossings. For example, when two voltage crossings occur at I 1 and I 3 , I SUPPLY becomes I 2 by averaging I 1 and I 3 . Therefore, the supply current rapidly follows the load current and the ringing of V OUT can be eliminated.
The operations of the proposed digital LDO regulator are performed by the digital controller in Fig. 3 . The 8-bit register #1 stores the present on-switch number. The adder/subtracter increases or decreases the on-switch number ( N ) by Δ N according to the comparator output (0 or 1), every clock cycle. The variable Δ N can be either “1” or “ K .” In Fig. 2(b) , Δ N = 1 because N changes one by one. In the case when Δ N = K , the operations are explained in Section II-2. The 8-bit register #2 stores the on-switch number at the previous voltage crossing of V REF and V OUT , as shown in Fig. 2(b) . When the update signal becomes “1” at a new voltage crossing of V REF and V OUT , multiplexer #1 (MUX1) selects the register #2 and multiplexer #2 (MUX2) selects L[9:2] instead of L[8:1] for 1-bit-shifting the summing result of the values in the two registers. As a result, the average of the two values at the previous and new voltage crossings, which are stored in registers #1 and #2, is calculated. The update signal remains at “1” during one clock cycle. The CLK2 pulse signal for register #2 is generated by the clock signal before the update signal returns to “0.” Register #2 stores the average value, which will be used at the next voltage crossing. Register #1 also stores the average value and then the adder/subtracter restarts to increase or decrease the on-switch number from the average value.
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Digital controller for fast current tracking scheme.
For example, when I LOAD changes from I 1 to I 2 (= I 1 + Δ I ) as shown in Fig. 2(b) , register #2 stores the on-switch number of I 1 at the previous voltage crossing. The adder/subtracter continues to increase the on-switch number of I SUPPLY in register #1 until a new voltage crossing happens when I SUPPLY becomes I 3 (= I 1 + 2 × Δ I ). At the new voltage crossing, the update signal becomes “1” so that the two multiplexers (MUX1 and MUX2) select their second inputs. The adder/subtracter adds two values stored in the registers #1 and #2 ( I 3 and I 1 ) by MUX1. The summing value ( I 1 + I 3 ) is 1-bit-shifted by MUX2 to make the average of I 1 and I 3 (= I 1 + 2 × Δ I ), which is the same as I 2 (= I 1 + × Δ I ). Registers #1 and #2 store the on-switch number of I 2 .
The digital controller has a circuit for keeping the on-switch number within a positive allowed number (0 to 255). The circuit is not shown in Fig. 3 .
- 2. Over-Voltage and Under-Voltage Detection Scheme
In a conventional digital LDO regulator, the on-switch number ( N ) changes in increments of one (Δ N = 1), as shown in Fig. 4(a) . Therefore, when the load current ( I LOAD ) changes rapidly, it takes many clock cycle times when I SUPPLY follows I LOAD . This causes large ripple voltages ( V R1 and V R2 ). The ripple voltages can be reduced by using the over-voltage and under-voltage detection scheme, as shown in Fig. 4(b) . In this scheme, if V OUT > V REF_H , then the on-switch number immediately becomes “0” and the LDO regulator stops supplying the current. Therefore, the positive ripple voltage is restricted by V REF_H . On the contrary, if V OUT < V REF_L , then the on-switch number changes by K instead of one (Δ N = K ). In Fig. 4(b) , K is set to four. The on-switch number changes rapidly (Δ N = K = 4) so that I SUPPLY follows I LOAD in a short time. This decreases the negative ripple voltage. When V OUT > V REF_L , Δ N returns to “1.” The on-switch number changes in increments of one (Δ N = 1) for the fine supply current control.
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Operations of digital LDO regulator (a) without and (b) with over-voltage and under-voltage detection scheme.
Figure 5 shows the voltage sensing circuit including the over-voltage and under-voltage detection. The voltage sensing circuit consists of three comparators, four resistors, and two capacitors. For the under-voltage protection, two resistors, R L1 and R L2 , make V REF_L , which is as follows:
V REF_L = R L2 R L1 + R L2 × V REF .
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Voltage sensing circuit.
For the over-voltage protection, two resistors, R H1 and R H2 , make V OUT_L instead of V REF_H , where V OUT_L is as follows:
V OUT_L = R H2 R H1 + R H2 × V OUT .
The comparator can determine if V OUT is larger than V REF_H , by comparing V OUT with V OUT_L . Assume that V OUT = V REF_H when V OUT_L = V REF . Then, V REF_H is as follows:
V REF_H = R H1 + R H2 R H2 × V REF .
In the simulation, V REF_H is set to be 5% higher than V REF , and V REF_L is set to be 2.5% lower than V REF . When V REF = 220 mV, V REF_H = 231 mV, and V REF_L = 214.5 mV (Δ V REF_H = 11 mV and Δ V REF_L = −5.5 mV).
Two capacitors, C 1 and C 2 , are used for supplying two stable voltages V REF_L and V OUT_L from the kickback noises of the comparators. The capacitors are implemented with the gate capacitances of NMOS transistors. In this design, the gate area ( W × L ) of the NMOS transistors for C 1 and C 2 is about 20 times larger than that of the input transistors of the comparators.
Figure 6 shows the simulated waveforms of the proposed digital LDO regulator. The LDO regulator was implemented using a 0.11 μm CMOS process. The simulations are performed at V IN = 0.25 V, V REF = 0.22 V, f CLK = 1 MHz, C EXT = 1 μF, and K = 8. The load current I LOAD is changed arbitrarily from 0 μA to 200 μA. After V REF is changed from 0 V to 0.22 V, the start-up time is 228 μs. The start-up time is improved by the under-voltage detection with K = 8. When the current changes between 20 μA to 200 μA, the undershoot (negative ripple) and overshoot (positive ripple) voltages are 5.9 mV and 6.8 mV, respectively. The undershoot voltage is reduced by the under-voltage detection with Δ V REF_L = −5.5 mV. The overshoot voltage is restricted by the over-voltage detection with Δ V REF_H = 11 mV.
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Simulated waveforms of proposed LDO regulator.
The undershoot voltage increases proportional to I LOAD and decreases proportional to I LSB , f CLK , and C EXT , where I LSB is the supply current difference of I SUPPLY when Δ N = 1. The I LSB is proportional to the sizes of the power switches, the supply voltage ( V IN ), and the voltage difference between V IN and V OUT (= V REF ). The larger K decreases the undershoot voltage by changing K × I LSB instead of I LSB when V OUT < V REF_L . The variable K is selected to take the value of “8” from the simulations in Fig. 7 . The value of K is fixed at the IC fabrication.
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Maximum undershoot voltage according to K.
The ripple voltages (the overshoot and undershoot voltages) are proportional to I LOAD and are inversely proportional to f CLK , I SUPPY,MAX , and C EXT . The proposed digital LDO regulator works at very low supply voltage under a subthreshold voltage, at which both f CLK and I SUPPY,MAX decrease significantly. The slow supply-current transitions due to the low f CLK and low I SUPPY,MAX cause a larger decoupling capacitor, which acts as a current buffer for the fast transient load current. Therefore, the proposed digital LDO regulator needs a much larger decoupling capacitor than the analog LDO regulators. Figure 8(a) shows the maximum ripple voltages when I LOAD = 20 μA to 200 μA, V IN = 250 mV, and V REF = 220 mV. The overshoot and undershoot voltages are 6.8 mV and 5.9 mV at C EXT = 1 μF, respectively. Figure 8(b) shows the maximum ripple voltages when I LOAD = 0.1 mA to 1 mA, V IN = 300 mV, and V REF = 250 mV. The overshoot and undershoot voltages are 11 mV and 14 mV at C EXT = 1 μF, respectively. In this design, the external decoupling capacitor ( C EXT ) is selected to 1 μF.
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Maximum ripple voltages when (a) ILOAD = 20 μA to 200 μA at VIN = 250 mV and VREF = 220 mV and (b) ILOAD = 0.1 mA to 1 mA at VIN = 300 mV and VREF = 250 mV.
Figure 9 shows the comparator circuit in the voltage sensing circuit, which is the sense-amplifier-type flip-flop. When the clock signal is “0,” the nodes S and R (set and reset) are “0.” When the clock signal changes to “1,” one of the nodes becomes “1.” This updates the SR latch storing the comparator output. The comparator output is used in the digital controller during the next clock cycle.
Figure 10 shows the minimum required supply voltage ( V DD ) of the comparator according to V REF at f CLK = 1 MHz. In the simulation, two input voltages ( V + and V −) of the comparator have the voltage difference of 2 mV and the common mode voltage of V REF . The minimum V DD is 238 mV at V REF = 140 mV. The lower V REF decreases the gate-source voltages and drain currents of the transistors N 1 and N 2 in the comparator in Fig. 9 . The reduced drain currents cause slow sensing operations in the comparator because the voltages of V 1 and V 2 change slowly. However, the higher V DD improves the sensing speed in the nodes V 1 and V 2 . To finish the sensing operation at f CLK = 1 MHz, the lower V REF needs the higher V DD . The reference voltage ( V REF ) can be lowered to 140 mV at V DD = 250 mV.
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Comparator.
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Minimum required VDD of comparator according to VREF at fCLK = 1 MHz when input voltage difference is 2 mV.
The voltage difference between V REF and V OUT of the LDO regulator comes from the input offset voltage of the comparator ( V offset ). The offset voltage is mainly affected by the process mismatches and variations. Figure 11 shows the Monte Carlo simulation results at V IN = 250 mV and V REF = 220 mV. The mean ( M ) and standard deviation ( σ ) of the offset voltage for 100 samples were 0.36 mV and 5.26 mV, respectively. The output voltage error due to the offset voltage can be adjusted by trimming V REF . Also, the two reference voltages ( V OUT_L and V REF_L ) for the over-voltage and under-voltage detections can be trimmed with the resistors R H1 , R H2 , R L1 , and R L2 to cancel the offset voltages of the comparators. If the reference voltage trimming is impossible, then Δ V REF_H (= V REF_H V REF ) and Δ V REF_L (= V REF V REF_L ) should be larger than the offset voltages.
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Monte Carlo simulation at VIN = 250 mV and VREF = 220 mV.
- 3. Switch Array
The digital LDO regulator uses 256 transistor switches for fine current control. In this design, the switch array uses eight binary weighted transistor switches instead of the same 256 transistor switches [7] [8] , to reduce the switch array area, as shown in Fig. 12 . The switch bias circuit is used to improve the current driving capability of the PMOS transistors in the switch array.
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Switch array.
When V IN = 0.25 V, the gate-source voltage of the turn-on PMOS transistor switches are in the subthreshold voltage regions. The current driving capability of the PMOS transistor is reduced significantly, so much so that large transistors are needed to flow the large load current. To improve the current driving capability, the forward bias voltage ( V FB = V IN V BIAS ) is applied to the PMOS transistors. The forward bias voltage must be well controlled to prevent the current flowing in the parasitic PN junction diode between P+ source and N-well. Figure 13 shows the bias voltage ( V BIAS ) according to V IN . The switch bias circuit generates the forward bias voltage ( V FB ) of 224 mV at V IN = 0.25 V. The forward bias voltage is much lower than the turn-on voltage of the PN junction diode (about 0.7 V). The switch bias circuit is safe for a wide range of V IN (0.25 V to 1.2 V).
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Bias voltage (VBIAS) according to VIN.
Figure 14 shows the maximum supply current ( I SUPPLY,MAX ) when all switches are turned on and the voltage difference between V IN and V OUT is 50 mV. The maximum supply current of the proposed switch array with the forward bias voltage (630 μA) is 3.1 times larger than that of the conventional switch array (204 μA) at V IN = 0.25 V. Therefore, the size of the switch array can be reduced in proportion to the current driving improvement.
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Maximum supply current of switch array (a) VIN = 0 V to 1 V and (b) VIN = 0.2 V to 0.35 V.
For the fast current tracking scheme, I SUPPLY,MAX needs be two times larger than I LOAD . For example, if I SUPPLY,MAX is 400 μA, then the recommended current of I LOAD is smaller than 200 μA. Of course, I LOAD can increase up to I SUPPLY,MAX . However, if I SUPPLY,MAX is smaller than 2 × I LOAD , then the current tracking time increases.
III. Measurement Result
The LDO regulator chip was fabricated using a 0.11 μm CMOS process. Figure 15 shows the chip microphotograph. Table 1 lists the characteristics of the LDO regulator chip. The chip core area is 7,700 μm 2 (110 μm × 70 μm). All measurements were performed at C EXT = 1 μF and f CLK = 1 MHz. The minimum voltages of V IN and V OUT are 250 mV and 140 mV, respectively. The maximum load currents at V IN = 0.25 V and V IN = 0.3 V are 0.2 mA and 1 mA, respectively. When V IN = 0.25 V, V REF = 0.22 V, and I LOAD = 0.2 mA, the current and power efficiencies are 99.45% and 87.52%, respectively. When the load current is changed from 20 μA to 200 μA, the ripple voltage of V OUT is 8 mV at V IN = 0.25 V.
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Chip microphotograph.
Characteristics of LDO regulator chips.
Technology 0.11 μm CMOS process
Area 7,700 μm2 (110 μm × 70 μm)
Ext. Cap. 1 μF
fCLK 1 MHz
VIN 0.25 V–1.2 V
VOUT 0.14 V–0.22 V 0.14 V–0.28 V
Max. ILOAD 0.2 mA @ VIN = 0.25 V 1 mA @ VIN = 0.3 V
Quiescent current 1.10 μA @ VIN = 0.25 V1.37 μA @ VIN = 0.3V
Current (power) efficiency 99.45% (87.52%) @ VIN = 0.25 V, VREF = 0.22 V, ILOAD = 0.2 mA 99.86% (83.22%) @ VIN = 0.3 V, VREF = 0.25 V, ILOAD = 1 mA
Line regulation 1.5 mV/V @ ILOAD = 0.2 mA 2.5 mV/V @ ILOAD = 1 mA
Load regulation 2 mV/mA @ VIN = 0.25 V VREF = 0.15 V 2 mV/mA @ VIN = 0.3 V VREF = 0.25 V
Ripple/overshoot/undershoot of VOUT 8 mV/5 mV/5 mV @ VIN = 0.25 V VREF = 0.22 V ILOAD = 20 μA–200 μA 13 mV/8 mV/8 mV @ VIN = 0.3 V VREF = 0.25 V ILOAD = 0.1 mA–1 mA
Figures 16(a) and 16(b) show the measured V OUT according to V IN at I LOAD = 0.2 mA and I LOAD = 1 mA, respectively. The digital LDO regulator can regulate V OUT from 140 mV to 220 mV at V IN = 250 mV and I LOAD = 0.2 mA. Also, it can regulate V OUT from 140 mV to 280 mV at V IN = 300 mV and I LOAD = 1 mA. The line regulations are 1.5 mV/V and 2.5 mV/V at I LOAD = 0.2 mA and I LOAD = 1 mA, respectively.
Figures 17(a) and 17(b) show the measured V OUT according to V IN at V REF = 150 mV and V REF = 250 mV, respectively. The current I LOAD is changed from 10 μA to 1 mA. The load regulation is 2 mV/mA. The minimum V IN can be as low as 230 mV at I LOAD = 0.2 mA and V REF = 150 mV. However, the minimum V IN for low voltage drop regulation is 250 mV, as shown in Fig. 16(a) .
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Measured VOUT according to VIN when VREF is changed (a) ILOAD = 200 μA and (b) ILOAD = 1 mA.
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Measured VOUT according to VIN when ILOAD is changed (a) VREF = 150 mV and (b) VREF = 250 mV.
Figure 18 shows the measured current efficiency and quiescent current of the digital LDO regulator according to I LOAD . These are measured at f CLK = 1 MHz. The constant current of 0.8 μA to 1 μA is drained through the resistor strings in the voltage sensing circuit and the switch bias circuit. When V IN = 250 mV, V REF = 150 mV, and I LOAD = 0.2 mA; the current efficiency, power efficiency, and quiescent current are 99.45%, 87.52%, and 1.10 μA, respectively. When V IN = 300 mV, V REF = 250 mV, and I LOAD = 1 mA, the current efficiency, power efficiency, and quiescent current are 99.86%, 83.22%, and 1.37 μA, respectively.
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Measured current efficiency and quiescent current according to ILOAD when (a) VIN = 250 mV and VREF = 150 mV and (b) VIN = 300 mV and VREF = 250 mV.
Figure 19(a) shows the measured transient waveforms of V OUT when I LOAD changes from 20 μA to 200 μA at V IN = 250 mV, and V REF = 220 mV. The ripple voltage of V OUT is 8 mV. Both the measured undershoot and overshoot voltages are 5 mV. Figure 19(b) shows the measured transient waveforms of V OUT when I LOAD changes from 0.1 mA to 1 mA at V IN = 300 mV, and V REF = 250 mV. The ripple voltage of V OUT is 13 mV. Both the measured undershoot and overshoot voltages are 8 mV.
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Measured transient waveforms of VOUT when (a) ILOAD changes from 20 μA to 200 μA at VIN = 0.25 V and VREF = 0.22 V and (b) ILOAD changes from 0.1 mA to 1 mA at VIN = 0.3 V and VREF = 0.25 V.
Figure 20 shows the measured transient waveforms of V OUT when V REF changes. In Fig. 20(a) , when V REF changes from 200 mV to 220 mV at V IN = 250 mV, I LOAD = 0.2 mA, and f CLK = 1 MHz, the rising and falling times of V OUT are 70 μs and 300 μs, respectively. The rising times of V OUT and V REF are similar. But, the falling time of V OUT is slower than that of V REF due to the small load current. In Fig. 20(b) , when V REF changes from 220 mV to 260 mV at V IN = 300 mV, I LOAD = 1 mA, and f CLK = 1 MHz, the rising and falling times of V OUT are both 90 μs. The transition times of V OUT are almost the same as those of V REF . The measurement shows that V OUT follows the voltage change in V REF rapidly.
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Measured transient waveforms of VOUT when (a) VREF changes from 200 mV to 220 mV at VIN = 0.25 V and ILOAD = 0.2 mA and (b) VREF changes from 220 mV to 260 mV at VIN = 0.3 V and ILOAD = 1 mA.
Figure 21 shows the measured waveforms of the bias voltage ( V BIAS ) according to V IN . The forward bias voltage ( V FB = V IN V BIAS ) improves the current driving capability of the PMOS switch transistors. The forward bias voltages are 250 mV and 268 mV at V IN = 0.25 V and V IN = 0.3 V, respectively. The forward bias voltage is under 280 mV for V IN = 0.25 V to 1.2 V, which is much lower than the turn-on voltage of the PN junction diode (about 0.7 V).
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Measured waveforms of bias voltage (VBIAS) according to VIN.
Table 2 compares low-voltage LDO regulator chips. The digital LDO regulators reduce the minimum power supply voltage ( V IN,MIN ) and the minimum output voltage ( V OUT,MIN ) compared with the analog LDO regulators. The proposed digital LDO regulator shows the better performances than the recently published low-voltage LDO regulators [3] [8] . This work achieves the lowest supply voltage, the lowest regulated output voltage, the smallest area, the smallest overshoot and undershoot voltages.
Performance comparisons of low-voltage LDO regulator chips.
EL 2006 [3] ISSCC 08 [4] JSSC 10 [5] JSSC 10 [6] CICC 10 [7] IET 2013 [8] This work
VIN = 0.25 V VIN = 0.3 V
Process 180 nm 350 nm 90 nm 90 nm 65 nm 90 nm 110 nm
LDO type Analog Analog Analog Analog Digital Digital Digital
Area (mm2) 0.122 0.053 0.155 0.019 0.042 0.026 0.0077
VIN (V) 0.65–0.95 1.05–3.5 0.95–1.4 0.75–1.2 0.5 0.38 0.25–1.2
VOUT (V) 0.5 0.9 0.7–1.2 0.5–1.0 0.45 0.12–0.32 0.14–0.22 0.14–0.28
ILOAD,MAX (mA) 50 4.04–164 100 100 0.2 1 0.2 1
IQuiescent (μA) 12.72 50 14 8 2.7 6.85 1.1 1.37
Current (power) efficiency (%) 99.9 (76.9) 99.7 (85.4) 99.9 (85.7) 99.9 (66.7) 98.7 (88.8) 99.3 (83.6) 99.45 (87.52) 99.86 (83.22)
Line regulation (mV/V) 0.23 1.06 N/A 3.78 3.1 2.9 1.5 2.5
Load regulation (mV/mA) 0.19 0.0614 0.4 0.1 0.65 0.11 2 2
Decoupling cap. No cap. 1 μF 6 pF 7 pF 0.1 μF 0.1 μF 1 μF 1 μF
Overshoot (mV) N/A N/A 70 114 30 50 5 8
Undershoot (mV) 300 6.6 70 73 40 65 5 8
IV. Conclusion
A 250 mV supply voltage digital LDO regulator was proposed. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The LDO regulator achieves a fast settling time of output voltage with a fast current tracking scheme and limits the overshoot and undershoot voltages using the over-voltage and under-voltage detection circuits. The size of the power switch arrary is reduced to 1/3 by applying the forward body bias voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.
This research was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (2015R1D1A3A01017756).
BIO
ace157@cbnu.ac.kr
Jae-Mun Oh received his BE and MS degrees in electronic engineering from Chungbuk National University, Cheongju, Rep. of Korea, in 2010 and 2012, respectively. He is currently working toward his PhD degree in semiconductor engineering at Chungbuk National Univesity. His research interests include analog circuits and power IC designs.
bdyang@cbnu.ac.kr
Byung-Do Yang received his BS, MS, and PhD degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1999, 2001, and 2005, respectively. He was a senior engineer at the Memory Division, Samsung Electronics, Hwaseong, Rep. of Korea, in 2005, where he was involved in the design of DRAM. Since 2006, he has been at Chungbuk National University, Cheongju, Rep. of Korea, where he is now an associate professor. His research interests are analog circuits, memory circuits, and power IC designs.
hjkang@kut.ac.kr
Hyeong-Ju Kang received his BS, MS, and PhD degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Rep. of Korea, in 1998, 2000, and 2005, respectively. From 2005 to 2006, he was with Magnachip Semiconductor, Cheongju, Rep. of Korea, where he participated in the development of a smart card controller. From 2006 to 2009, he worked for GCT Semiconductor, Seoul, Rep. of Korea to develop baseband modem chips for several digital mobile TV standards. Since 2009, he has been an assistant professor in the School of Computer Science and Engineering at Korea University of Technology and Education, Cheongju, Rep. of Korea. His current research interests include communication modem design, embedded processor design, and computer-aided design algorithms for formal verification.
kimys@cbnu.ac.kr
Yeong-Seuk Kim received his BS and MS degrees in electronics engineering from Seoul National University, Rep. of Korea, in 1980 and 1982, respectively and his PhD degree in electrical engineering from the University of Florida, USA, in 1990. From 1982 to 1985, he was with the Central Research Laboratories of Gold Star, Seoul, Rep. of Korea, where he designed analog and digital IC’s for consumer electronics. From 1990 to 1993, he joined the Advanced Products Research and Development Laboratory of Motorola, Austin, TX, USA, where he worked on the characterization and modeling of bipolar transistors; CMOS; and EEPROM technology development for advanced microcontrollers. Since 1993, he has been on the faculty of the Department of Semiconductor Engineering at Chungbuk National University, Cheongju, Rep. of Korea. His research interests include low-voltage analog and mixed-signal integrated circuit design for RF, baseband, and biomedical applications and dc-dc converters.
hychoi@cbnu.ac.kr
Ho-Yong Choi received his BS degree in electronics engineering from Seoul National University, Rep. of Korea, in 1980 and his MS degree in electrical and electronics engineering from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1982. He received his PhD degree in electronics engineering from Osaka University, Japan, in 1994. From 1982 to 1985, he worked as a design engineer in Samsung Semiconductor Co., Kiheung, Rep. of Korea, where he was involved in work on the design of custom IC and single-chip microcomputers. From 1985 to 1996, he was with the Department of Electronics Engineering, Pukyung National University, Busan, Rep. of Korea. In 1996, he joined the Department of Electronics Engineering, Chungbuk National University, Cheongju, Rep. of Korea, where he is now a professor. His primary interests include design and testing of integrated circuits and systems; design for testability; and test generation.
Corresponding Author wsjung@cbnu.ac.kr
Woo-Sung Jung received his BS and PhD degrees in computer science and engineering from Seoul National University, Rep. of Korea, in 2003 and 2011, respectively. He was a researcher in SK UBCare, Seoul, Rep. of Korea, from 1998 to 2002. He was a senior research engineer at Software Capability Development Center in LG Electronics, Seoul, Rep. of Korea, from 2011 to 2012. He is currently an assistant professor at the Department of Computer Engineering, Chungbuk National University, Cheongju, Rep. of Korea. His research interests include software evolution, software architecture, adaptive software systems, and mining software repositories.
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