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Electrothermal Analysis for Super-Junction TMOSFET with Temperature Sensor
Electrothermal Analysis for Super-Junction TMOSFET with Temperature Sensor
ETRI Journal. 2015. Oct, 37(5): 951-960
Copyright © 2015, Electronics and Telecommunications Research Institute (ETRI)
  • Received : March 11, 2015
  • Accepted : June 25, 2015
  • Published : October 01, 2015
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Young Hwan Lho
Yil-Suk Yang

Abstract
For a conventional power metal–oxide–semiconductor field-effect transistor (MOSFET), there is a trade-off between specific on-state resistance and breakdown voltage. To overcome this trade-off, a super-junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature-sensing structures — diode and resistive. In this paper, a diode-type temperature-sensing structure for a TMOSFET is designed for a brushless direct current motor with on-resistance of 96 mΩ·mm 2 . The temperature distribution for an ultra-low on-resistance power MOSFET has been analyzed for various bonding schemes. The multi-bonding and stripe bonding cases show a maximum temperature that is lower than that for the single-bonding case. It is shown that the metal resistance at the source area is non-negligible and should therefore be considered depending on the application for current driving capability.
Keywords
I. Introduction
Super-junction (SJ) metal–oxide–semiconductor field-effect transistor (MOSFET) [1] [2] power devices are well known for lower on-state resistance and gate charge. However, it is difficult to fabricate an exact balanced doping profile, and the impact of an imbalanced doping profile results in varying breakdown voltages (BVs). In the structure of an SJ MOSFET, heavily doped alternate P-N pillars act as a substitute for the lightly doped drift region of conventional power MOSFETs [3] .
In a conventional MOSFET, there exists a trade-off between specific on-state resistance and BV. An interesting trade-off curve between the specific on-resistance and the BV capability can be created by using a doping gradient in the drift region as a parametric variable. The specific on-resistance in a non-uniform trench MOSFET (TMOSFET) is lower than that in a conventional MOSFET as BV increases [3] .
A non-uniform SJ TMOSFET structure is used to overcome the specific on-resistance made in the drift region at the same BV. The BV of an SJ TMOSFET tends to increase as the length of the drift region increases and is independent of the doping concentration at the N-drift region. Then, the N-drift region can afford to be doped at a much higher concentration to reduce the on-state resistance of the drift region below that of the conventional structure without affecting the BV.
An SJ TMOSFET, on the other hand, has P and N pillars, which are of equal widths, W P and W N , respectively, and is based on an SJ DMOSFET [1] [2] . The doping concentrations of the P and N pillars in an SJ TMOSFET are denoted by N A and N D , respectively. The relationship between the doping concentrations and widths of the pillars is as follows:
N D W N =  N A W P ,
In this paper, a bipolar diode structure is used as a temperature sensor because of the linear dependency of its diode voltage on temperature [4] [5] . A temperature-dependent model with self-heating characteristics has been implemented and will be described in the next section.
The MOSFET chip is divided into a 5 × 5 array of cells, each of which is 1 mm × 1 mm in size. Each unit cell is connected to the source metal, and the equivalent subcircuit model is implemented and simulated by SPICE. The power dissipation is calculated, and the junction temperatures are found for the power dissipation at each cell by using a thermal impedance model. The temperature at each unit cell is also calculated by using ANSYS software.
The structure of our SJ TMOSFET with embedded diode-type temperature sensor is shown in Fig. 1 ; it is composed of alternate P-N pillars, each of which is of the same width, in the drift region.
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Structure of SJ TMOSFET.
II. SJ TMOSFET with Temperature Sensor
- 1. On-Resistance of SJ TMOSFET
The on-resistance of an SJ TMOSFET is determined by the resistance between the channel and drift regions. An increased doping concentration in the drift region enables a dramatic reduction of the drift region resistance, for a required BV. The on-resistance [3] can be obtained by currents flowing from the channel between the source and the drain electrodes, and is modelled as follows:
R ON =  R CS + R N + R CH + R D1 + R D2 + R CD ,
where R CS is the contact source resistance, R N is the source resistance, R CH is the channel resistance, R CD is the drain contact resistance, R D1 is the N-type drift region resistance, and R D2 is the substrate resistance. Figure 1 illustrates the various components of the SJ TMOSFET. Channel resistance and drift region resistance mainly affect on-resistance; the other types of resistance are significantly negligible and can be ignored in this paper.
A. Channel Resistance
The value of specific on-resistance from a channel in the non-uniform TMOSFET structure is the same as that for a uniform TMOSFET structure.
R CH,SP = L CH W cell 2 μ ni C OX ( V G V TH ) ,
where L CH is the channel length, W cell is the width of a unit cell, μni is the electron mobility, C OX is the gate capacitance, V G is the gate voltage, and V TH is the threshold voltage. The R on,sp from the channel in the non-uniform TMOSFET is 0.0184 mΩ·cm 2 when the gate bias is 10 V.
B. Drift Region Resistance
The resistance in the drift region consists of R D1,SP and R D2,SP . The analytical modeling of the drift region resistance is complicated by the non-uniform doping profile that contains an electron mobility that varies with doping concentration. The drift region resistance contribution from the mesa region (N-pillar region) can be obtained by considering a small segment (d y ) of the drift region at a depth y from the bottom of the gate electrode. The specific resistance [2] of the drift region is computed by
R D1,SP =( W cell W M ) 0 L D ρ D (y) dy,
where W M is the width of pillar N, and the resistivity ρ D ( y ) is a function of the position of y in the drift region. The resistivity of the drift region is given by
ρ D (y)= 1 q μ n (y) N D (y) ,
where q is the charge, μn ( y ) is the electron mobility, and N D ( y ) is the doping density of the drift region.
An additional resistance contribution of R D2,SP in the non-uniform TMOSFET structure is related to the buffer layer located below the bottom of the trenches. In this portion of the structure, the current density is uniform and current flow occurs across the entire cell width. The specific on-resistance [2] can be obtained from
R D2,SP =( W cell W M ) 0 L D 1 q μ n (y) N o e gy dy =( W cell W M ) 1 q μ n (y) N o g ( e g L D 1 ),
where No is the doping concentration at the top of pillar N, g is the exponential gradient doping profile, and L D is the drift length of pillar N.
The doping profile at the N-drift region decreases exponentially, in which the concentration at the top of the N pillar is 1 × 10 16 cm –3 and that at the bottom is 2 × 10 16 cm –3 in the case of a 120 V non-uniform SJ TMOSFET structure with a doping gradient of 2.75 × 10 3 cm –1 . In the structure, the P-base region has a doping profile with a peak doping concentration of 1.5 × 10 17 cm –3 . The specific on-resistance for the drift region is 67 mΩ·mm 2 , which satisfies design requirements.
- 2. Temperature Sensor
The diode-type temperature sensor is formed at the well region. As can be seen in Fig. 2(a) [6] , the upper P + layer surrounded by the N + cathode layer plays the role of reducing electron injection toward the drain at the bottom, in which the parasitic operation of the vertical NPN bipolar transistor is eliminated. Figure 3 represents the vertical doping profile for the cathode layer; here, it can be seen that the net doping at 1 μm has increased to 8 × 10 19 /cm 3 , which is enough to prevent an electron injection. In the P-N diode-type temperature sensor depicted in Fig. 4 , the cathode should possess a negative voltage so as to turn on the embedded diode. In the structure, most of the current flows horizontally at the surface from the cathode to the anode; however, about 10% of the current from the cathode flows to the substrate drain area, which reduces the unnecessary operation of the vertical NPN transistor formed between the cathode and the drain. The diode current at the surface of the SJ TMOSFET exponentially increases as the forward voltage increases. For the negative cathode voltage, the diode current (composed of both an anode and a cathode current) in the upper line in Fig. 5 linearly decreases at logarithmic scale. The current voltage characteristics for different temperatures of the diode, formed at the surface, are plotted in Fig. 6(a) . The subthreshold region below the turn-on voltage of 0.7 V is applicable to the temperature sensor. As the temperature increases in Fig. 6(b) , the voltage between the anode and the cathode linearly decreases at a rate of 1.74 mV/°C when a forcing current of 1 μA at the anode is measured.
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Diode temperature sensor: (a) structure and (b) cross-section.
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Vertical doping profile from top to bottom at center of cathode in Fig. 2: (a) along line A and (b) along line B.
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Current flow line when Vcathode = – 0.7 V.
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Diode currents vs. negative cathode voltage (logarithmic scale).
In the SJ TMOSFET structure, the diode-type temperature sensor is implemented toward the upper part for measuring V BE . In the temperature range of 300 K to 450 K, a linear fit is applied to the relationship between the forward voltage versus temperature (K), which is obtained for an emitter current, as shown in Fig. 6(b) . The diode-type temperature sensor’s forward voltage line linearly decreases as temperature increases under a constant bias current.
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Diode characteristics: (a) I-V characteristics for different temperatures and (b) forward voltage vs. temperature at current of 1 μA.
For temperature sensing, the temperature change of the base-emitter voltage ( V BE ) under a constant emitter current is measured. The forward voltage is a well-known electrical parameter for measuring the temperature of a semiconductor device. The relationship [3] between the current, voltage, and temperature of an ideal PN-junction is given by
I PN = I S ( e q V PN kT 1 ),
where I S is the saturation current of the diode, I PN is the current flowing through the PN-junction, V PN is the voltage across the junction, q is the electron charge, k is Boltzmann’s constant, and T is temperature. The saturation current [3] is described by
I S = I O T γ e E g kT ,
where γ is a constant equal to about a value of three, I O is a constant, and E g is the bandgap of Si (1.12 eV at T = 275 K).
The bipolar transistor is formed by the emitter (N + source), base (P-body), and collector (N epi) regions shown in Fig. 2 . The base-emitter voltage [5] depends on the temperature under a biased constant current, and the change of V BE under this biased constant current can be measured as follows:
V BE =  V BE ( T R )+ β V BE (T T R ),
where V BE ( T ) is the temperature-dependent base-emitter voltage, T R [K] is the reference temperature, and β VBE [V/K] is the temperature coefficient. The temperature coefficient of β VBE is measured as –2 mV/K [5] . The measurement temperature range is –60 °C to 180 °C. The structure of the SJ TMOSFET is composed of alternate P-N pillars. The doping concentration and pillar widths are determined to balance the charge distribution of the structure. The main characteristics of an SJ TMOSFET with bipolar sensor are shown in Table 1 .
Specifications of SJ TDMOSFET[2].
Device parameter Value Device parameter Value
Cell pitch 2.4 μm Trench depth 1.75 μm
N, P pillar doping concentration 1×1016/cm3 Trench depth 0.28 μm
Gate oxide thickness (tox) 500 Å N+ source width 0.25 μm
P well depth (Xj) 1.2 μm P+ body contact width 1.5 μm
- 3. Temperature Measurement
To measure the temperature of the chip, a constant current source is connected to the anode of the embedded diode-type temperature sensor [7] [8] , shown in Fig. 2 . A square wave is applied to the gate of the SJ TMOSFET, and the embedded diode-type temperature sensor is internally mounted to the source. When the constant current at the diode temperature sensor is flowing, the temperature can be converted to a corresponding transient variation of voltage with respect to time, and then measured. It is possible to check the sensing temperature of the SJ TMOSFET, as is depicted in Fig. 7 .
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Equivalent circuit for temperature measurement circuit.
The threshold voltage of the SJ TMOSFET [9] [10] decreases as the ambient temperature increases.
V th = V th0 ρ(T T 0 ) ,
μ n = μ 0 ( T T 0 ) m ,
where V th is the drain-source voltage, V th0 is the threshold voltage at room temperature, T is the junction temperature (K), T 0 is the reference temperature (300 K), ρ is a threshold voltage coefficient of –0.0046 (V/K), μn is the electron mobility (V/m 2 s), μ 0 is the electron mobility at room temperature, and m is an electron-mobility reduction model exponent of 1.5.
A thermal impedance model is designed (see Fig. 8 ). The relationship between power and temperature in this model is given by
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Thermal impedance model for package.
T=P× R th ,
where T indicates temperature, R th represents thermal resistance, and P represents power (in watts).
- 4. Self-Heating Electrothermal Model
In Fig. 8 , T c is case temperature, T j is junction temperature, and R of 10 GΩ is dummy resistance. The five combinations of both R th (thermal conductivity) and C th (heat capacity) are for modeling the transient thermal characteristics.
A thick aluminum layer (3 μm) is used to reduce the source resistance. An analysis of the distributed source resistance is needed, since this type of resistance is caused by the source metal in the case of low on-resistance.
As shown in Fig. 9 , the normalized on-resistance linearly increases at a rate of 1.51%/K as the temperature increases; this rate is used for the equivalent circuit model of I _ R on_temp in Fig. 10 .
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Normalized on-resistance vs. temperature.
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Temperature-dependent equivalent circuit model of unit cell with threshold voltage and on-resistance.
Figure 11 represents the relationship between the drain current, I d , and the voltage applied to the shorted gate and drain. The figure shows that the threshold voltage decreases as the temperature increases. In the case of a high temperature during the operation of the SJ TMOSFET, the current level is greatly degraded by the ohmic voltage drop. In other words, the threshold voltage applied at V th_temp (see Fig. 10 ) decreases at a rate of approximately 2.3 mV/°C as temperature increases (see Fig. 12 ).
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Id vs. voltage (Vd = Vg) for four different temperatures.
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Threshold voltage vs. temperature.
A model of a temperature-dependent MOSFET, in Fig. 10 , having a shift in threshold voltage is considered. The related reduction in threshold voltage is represented by V th_temp , which reflects the effect of temperature; the on-resistance, R ds,on , increases as temperature increases; and vice versa.
The power dissipated by the SJ TMOSFET is transferred into the “thermal impedance model for package” (see Fig. 8 ), and the junction temperature ( T j ) is then computed. Both the shift in threshold voltage and the on-resistance for the given temperature are transmitted to the equivalent circuit models of V th_temp and I _ R on_temp , respectively, in Fig. 10 . The thermal impedance for a unit cell of 1 mm 2 is assumed to be uniformly distributed.
To reduce the on-resistance of a TMOSFET of 100 V and 100 A for a BLDC motor, an SJ TMOSFET is designed and its design parameters verified. A new type of stripe bonding is applied to a thermal package, and the characteristics of this type of bonding are well analyzed.
III. Simulations and Analyses
Figure 13 shows electrothermal simulation flow [11] [12] . To carry out electrothermal simulation, a unit-cell SJ TMOSFET, a self-heating thermal model, connected with resistor arrays at the source is considered [13] . A SPICE simulation is executed to obtain a steady-state transient solution. The power dissipation at each unit cell of the SJ TMOSFET can be computed and transferred to an ANSYS model by using the heat-flow command described in this paper. Finally, the temperature distribution can then be obtained.
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Electrothermal simulation flow.
The current density in an SJ TMOSFET with ultra-low on-resistance ( R ds,on ) is greatly affected by the parasitic resistance at the source metal at the top layer (see Fig. 14 ). To secure the reliability of the SJ TMOSFET, it is important for the temperature at the chip (see Fig. 15 ) to be uniformly distributed. As the number of bonding wires increases, the peak temperature point at the chip can be widely distributed. Through a SPICE simulation, we can check whether the number of bonding wires and their relative positions affect the temperature at the chip. In the case of a single bonding wire (see Fig. 16 ), the maximum and minimum temperatures are measured as 67.1 °C and 40.1 °C, respectively. Similarly, for four bonding wires (see Fig. 17 ), we have 47 °C and 41 °C, respectively. These results are similar to those of the stripe bonding in Fig. 18 .
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Unit-cell structure of SJ TMOSFET.
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Equivalent resistance model for an SJ TMOSFET with 5 × 5 array meshes (distributed source resistance and MOSFET equivalent model with 5 × 5 array meshes).
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Temperature distributions at points for single bonding wire.
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Temperature distributions at points for four bonding wires.
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Temperature distributions at points for stripe bonding.
An electrothermal SPICE model for a power MOSFET is implemented. The thermal impedance models of TO220 and TO247 packages are referred to as a Fairchild MOSFET [12] .
The sheet resistance of aluminum, which is used for the source metal at the top layer, is 15 mΩ·mm 2 for a thickness of 2 μm. The area of the chip is 1 mm 2 , and the drift resistance between grid points is computed to be approximately 25 mΩ; the resistance of bonding wire is 0.1 mΩ. In the SJ TMOSFET equivalent resistance model (see Fig. 15 ) [12] , [14] , mesh resistance is caused by the source metal located at the upper-most area; the drift resistance at the SJ TMOSFET and resistance at the bonding is modeled as an array. Every node point at the resistor array located at the source metal (for a distributed resistance) is connected to the source (see Fig. 14 ). The simulation circuit is composed of 5 × 5 SJ MOSFETs and 4 × 4 resistor arrays.
The cross-section of a unit cell belonging to an SJ TMOSFET (based on Table 1 ) is shown in Fig. 14 . Here, R m is the distributed resistance at the source metal — dependent mainly on the thick aluminum found at the top layer.
After analyzing the power dissipation by using LTspice [15] , temperature characteristics were accomplished by using both SILVACO TCAD Atlas and ANSYS software [16] . It is shown that the power dissipation when V drain = 0.5 V is concentrated at the center; the peak points for a single bonding wire, four bonding wires, and stripe bonding are shown in Figs. 16 , 17 , and 18 , respectively.
The temperature dissipation becomes both widely and uniformly distributed as the number of bonding wires increases. The temperature dissipations for the various different bonding schemes are shown in Fig. 19 .
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Maximum, minimum, and difference values of temperature vs. different bonding schemes.
A SPICE self-heating electrothermal model for the TO220 package supplied by the Fairchild Semiconductor company is implemented, with an area of 25 (5 × 5) mm 2 for a chip, consisting of TMOSFETs and resistor arrays. The junction temperature, which affects the threshold voltage and on-resistance, is measured at each TMOSFET. Then, the operating voltage is determined by a SPICE simulation. Figures 20(a) and 20(b) show a single-bonding-wire structure and a stripe-bonding structure, respectively. The temperature distributions of both the single-bonding and stripe-bonding structures are simulated, as shown in Figs. 21(a) and 21(b) , respectively. The single-bonding-wire structure has a maximum temperature of 112.69 °C at the center of the chip and a minimum temperature of 24.759 °C at the end of its leg (see Fig. 20(a) ). Similarly, the stripe-bonding structure has a maximum temperature of 87.821 °C at the center of the chip and a minimum temperature of 24.781 °C at the end of its leg. These results indicate that the heat is more widely dispersed in the stripe-bonding-structure case. Both the SPICE simulation and the ANSYS package thermal simulation show similar temperature distributions. The former is considered in the design of the model for the self-heating circuit with threshold voltage and on-resistance for junction temperature (the distributions being obtained from either the chip temperature in ANSYS or the junction temperature in SPICE). For a power TMOSFET with ultra-low on-resistance [17] and high current application, temperature distributions along a vertical line through the center of the chip (see Fig. 20(b) ) are similar to those for the four-bonding-wire structure; however, the stripe-bonding structure has the added advantage of reducing the cost of package assembly. Thus, the stripe-bonding structure is recommended to disperse any concentrations of high temperature.
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Structure in ANSYS 3D model: (a) one bonding wire and (b) stripe bonding.
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Temperature distribution: (a) one bonding wire and (b) stripe bonding.
IV. Conclusion
The structure of an SJ TMOSFET with an embedded temperature sensor and a simulation for analyzing the characteristics of the diode-type temperature sensor were completely examined. It was found that the forward voltage of the diode-type temperature sensor linearly decreased as the temperature increased. To achieve a uniformly distributed power dissipation, distributed wire bonding with multiple wires should be used to accommodate heat at the bonding point where the current is concentrated.
When assembling the power MOSFET with ultra-low on-resistance, the number of bonding wires and their relative positions should be carefully considered so as to prevent localized current flowing. The MOSFET should be designed in consideration of both the junction temperature and the current distribution at each of the given bonding wires. Here, the appropriate number of bonding wires and schemes should be determined, considering the maximum power dissipation and the package type. The maximum temperature is limited to a certain value to guarantee the reliability of the chip. In addition, the stripe bonding scheme is strongly recommended for packaging a power MOSFET with ultra-low on-resistance.
This work was supported by Institute for Information & Communications Technology Promotion (IITP) grant funded by the Korea government (MSIP) (No. B0186-15-1001, Form factor-free Multi-input and output Power Module Technology for Wearable Devices).
BIO
Corresponding Author yhlho@wsu.ac.kr
Young Hwan Lho received his BS degree from Kyungpook National University, Daegu, Rep. of Korea, in 1982; his MS degree from the University of New Mexico, Albuquerque, USA, in 1988; and his PhD degree from Texas A&M University, College Station, USA, in 1993, all in electrical engineering. From November 1981 to December 1985, he was an engineer with LG Information Communication Co., Ltd., Seoul, Rep. of Korea, working on parts localization for electronic switching systems. From February 1994 to February 1995, he was a senior researcher with Korea Aerospace Research Institute, Daejeon, Rep. of Korea, working on satellite attitude control. Since March 1995, he has been with Woosong University, Daejeon, Rep. of Korea, where he is a professor. His research interests include power electronics design, power circuit design, and automatic controls for systems.
ysyang@etri.re.kr
Yil-Suk Yang received his BS, MS, and PhD degrees from the School of Electrical Engineering & Computer Science, Kyungpook National University, Daegu, Korea, in 1989, 1994, and 2008, respectively, all in electronics engineering. Before joining ETRI in 1999, he was with LG Semiconductor, Seoul, Rep. of Korea. Since 1999, he has worked at the Basic Research Laboratory, ETRI, where he has been engaged in the research of low power circuit design, high energy efficiency circuit design, and power electronics design.
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