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HV-SoP Technology for Maskless Fine-Pitch Bumping Process
HV-SoP Technology for Maskless Fine-Pitch Bumping Process
ETRI Journal. 2015. Jun, 37(3): 523-532
Copyright © 2015, Electronics and Telecommunications Research Institute (ETRI)
  • Received : May 13, 2014
  • Accepted : January 17, 2015
  • Published : June 01, 2015
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About the Authors
Jihye Son
Yong-Sung Eom
Kwang-Seong Choi
Haksun Lee
Hyun-Cheol Bae
Jin-Ho Lee

Abstract
Recently, we have witnessed the gradual miniaturization of electronic devices. In miniaturized devices, flip-chip bonding has become a necessity over other bonding methods. For the electrical connections in miniaturized devices, fine-pitch solder bumping has been widely studied. In this study, high-volume solder-on-pad (HV-SoP) technology was developed using a novel maskless printing method. For the new SoP process, we used a special material called a solder bump maker (SBM). Using an SBM, which consists of resin and solder powder, uniform bumps can easily be made without a mask. To optimize the height of solder bumps, various conditions such as the mask design, oxygen concentration, and processing method are controlled. In this study, a double printing method, which is a modification of a general single printing method, is suggested. The average, maximum, and minimum obtained heights of solder bumps are 28.3 μm, 31.7 μm, and 26.3 μm, respectively. It is expected that the HV-SoP process will reduce the costs for solder bumping and will be used for electrical interconnections in fine-pitch flip-chip bonding.
Keywords
I. Introduction
As miniaturization and the lightening of weight have become highly demanded facets in electronic equipment, flip-chip bonding technology has received attention in the packaging industry for satisfying high densification [1] . The solder bumping process was studied and developed, and it is necessary for electrical interconnections on flip-chip bonding [2] .
The bump pitch on substrates and devices is decreasing, and various kinds of solder bumping technologies have been investigated, including electro-plating, solder jetting, evaporation, micro-ball placement, and screen printing. Figure 1 shows various bumping methods in accordance with bumping pitch ranges. Yole stated that micro bumps can be formed by evaporating or plating [3] . Electro-plating and solder jetting methods are good for a fine pitch of less than 130 µm and create high-quality bumps, but these methods have a big disadvantage in terms of their high cost [4] . A screen printing method, which is more affordable, is widely used because of its simplicity [5] [6] . A general screen printing method uses a pattern-designed metal mask for printing solder paste. Normally, if the pitch of the metal pad is smaller than 130 µm, then the yield of the bumps is very low because the solder paste does not separate from the metal mask [7] . We can use a polymer mask, which can accommodate a fine pitch, but there is a drawback in terms of disposability. For this reason, we developed an easy, low-cost bumping method using screen printing with a stencil mask as a guide for a fine-pitch bumping process. A comparison of the conventional and novel processes is shown in Fig. 2 . In the conventional process, solder paste is printed on the substrate using a designed metal mask to satisfy various pads individually, as shown in Fig. 2(a) . In addition, a printed substrate goes through a reflow process. In the novel process, however, solder bumps are made by printing on the whole pad using a special material called solder bump maker (SBM) consisting of resin and solder powder without a mask, as shown in Fig. 2(b) [8] . This new method does not require a patterned metal mask or disposable polymer mask, and it takes advantage of screen printing, which is convenient and cost effective.
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Various bumping methods in accordance with bumping pitch ranges (Yole report [3]).
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Comparison of (a) conventional and (b) novel processes used to form a solder bump on a PCB substrate.
In previous studies, we developed a low-volume solder-on-pad (LV-SoP) technology that can be utilized on a PCB to flip-chip bond with a Cu pillar [9] [12] . LV-SoP [11] technology was developed for the fine-pitch interconnection between the device with Cu pillar and PCB substrate to avoid the electrical shortage between adjacent solder bumps due to the excessive amount of solder.
A flip-chip bonding process that is performed on a PCB that has solder bumps formed by LV-SoP technology and upper chips is done so by carefully aligning the position of each solder bump. In addition, for the bonding between a Cu pillar and LV-SoP, controlling the temperature and applying strong pressure during this process is essential to guarantee successive electrical interconnections. For the mass production of fine-pitch device packaging, the reflow process without applying strong pressure is conducted after the alignment process. Therefore, the height of solder bumps on a PCB intended for mass production should be higher than the thickness of solder resist so as to obtain a high-quality electrical interconnection on milder conditions.
LV-SoP indicates bumps of height lower or equal to the height of the solder resist ( δ sr ) of the PCB, as shown in Fig. 3 (a) . Thus, the height of a solder bump ( δ sb ) is similar with the height of the solder resist ( δ sr ), and LV-SoP is able to make an electrical interconnection between a fine-pitch device using a previously developed material [13] [18] for removing the oxide layer. In the present study, a high-volume solder-on-pad (HV-SoP) technology, as a low-cost process, is investigated for the flip-chip bonding between a device without Cu pillar and PCB substrate. The HV-SoP is defined by bumps having a height of about 10 µm higher than the solder resist on a PCB. In Fig. 3(b) , the height of the solder bumps ( δ sb ) is about 10 µm higher than the height of the solder resist ( δ sr ). Figure 3 shows the differences between an LV-SoP and HV-SoP. Various processing parameters were adjusted for HV-SoP technology, such as the oxygen concentration, guide mask design, and printing method.
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Comparison of (a) LV-SoP and (b) HV-SoP on a PCB substrate.
II. Materials and Experiments
- 1. Materials
To carry out the HV-SoP process, an SBM was used. An SBM is a mixture of a base resin, reductant, and solder powder. The base resin generates the reaction medium of the reductant and solder powder without causing a chemical reaction. Table 1 shows the functions and requirements of SBM. This unique material can minimize the occurrence of out-gassing in the bumping process because it does not use any solvent and is very stable. Sn/3.0Ag/0.5Cu type 7 solder powder was used for SBM, and the diameter of the type 7 solder powder is between 2 µm and 11 µm, as shown in Fig. 4 . All materials used in the experiments are commercially available. For the SBM paste, the amount of reductant was fixed as 10 parts per hundred (phr) based on the resin, and the mixing ratio of the resin and solder is 70:30 in volumetric percent. Additionally, the SBM paste was mixed using a paste mixer PDM-300 from KM Tech with a revolution and rotation method for one minute. Figure 5 shows an SEM image of a PCB substrate used in the HV-SoP process. PCB and solder powder were used as the same as those used in the previous study of LV-SoP technology [11] . In a PCB substrate with grid-patterned Cu pads, the solder resist opening, pitch of the pad, thickness of the solder resist, and total number of Cu pads are 70 µm, 130 µm, 17 µm, and 625 (25 × 25), respectively. The surface of the Cu pads was covered by an organic solderability preservative (OSP) to prevent the oxidation of a metal pad.
Functions and requirements of SBM.
Component Functions and requirements
Base resin - Carrying solder powder- Proper viscosity with temperature- Proper surface tensions
Reductant - Elimination of the oxide layer on the solder powder- Minimal chemical reactions- No out-gassing
Solder powder - Solder bump formation- Size distribution
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SEM image of Sn/3.0Ag/0.5Cu type 7 solder powder [11].
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SEM image of PCB substrate used [11].
- 2. Experiments
Figure 6 shows a process flow of the HV-SoP process using SBM paste. In step 1, a well-mixed SBM paste is printed on a PCB substrate using a stencil mask. The stencil mask is used as a guide to control the thickness of the applied paste and is designed in a square shape so as to cover all PCB pads including the solder resist and pads, as shown in step 1 of Fig. 6 . A 200-mesh stencil mask is used, and the thickness of the printed paste is adjusted to approximately 45 µm. Step 2 is a heating process for forming the bumps. In this step, the temperature of the SBM increases to 240°C with a heating rate of 1°C/s, which is higher than the melting point of the solder powder, and this is held for 30 s. Step 3 is carried out to clean the resin and solder powder residue. Acetone and methanol are used in an ultrasonic bath for 10 s. For the SoP process, an SMT reflow (SK-5000) is utilized to control the temperature and oxygen concentration, as well as to observe the process at high temperature. The SMT reflow used in the experiment, SK-5000 from Sanyo, is composed of a chamber that can contain the sample, observation cameras, oxygen analyzer, and cooler. Temperature increase is achieved through the halogen lamp in the chamber. For the HV-SoP process, a suitable oxygen concentration is studied by controlling the reaction atmosphere. The SMT reflow used in the experiments controls the oxygen level by allowing nitrogen gas to flow into the chamber. When the oxygen concentration reaches the setting level, the oxygen analyzer continuously maintains the concentration of oxygen in the reaction. To verify the effect of oxygen concentration in a bumping reaction, the results of the bump formation according to a diverse range of oxygen concentrations is observed. As in equation (1) below, the solder reaction ratio ( R s ) is calculated by dividing the weight of the solder after a reflow ( W saft ) by the weight of the solder in a printed SBM before a reflow ( W sbef ). The weights of the PCB with a printed SBM ( W sbef ), as shown in step 1 of Fig. 6 , and the PCB with a wetted solder after a reflow ( W saft ), as shown in step 2 of Fig. 6 , are measured, respectively.
R s = W saft W sbef ×100,
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Schematic diagrams of SoP process using SBM.
where R s is the solder reaction ratio, W saft is the weight of the solder after a reflow, and W sbef is the weight of the PCB with a printed SBM.
For HV-SoP technology, various process factors are controlled for uniform bumps. To select the appropriate mask for the HV-SoP process, several kinds of masks were designed, as shown in Table 2 . Because the novel process uses a whole PCB pad including a solder resist and Cu pads for the printing area, as shown in Fig. 7 , it is expected that there is a difference in the solder bumps depending on the printing area. Each mask used in the experiment has a margin 100 µm, 500 µm, 1,000 µm, and 2,000 µm from the edge, respectively.
Various margins of designed masks.
M1 M2 M3 M4
Lm (µm) 100 500 1,000 2,000
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Schematic of printing step using guide mask, with stencil mask.
To find the optimal processing condition for HV-SoP bumping, a double printing method, which is a modified method of single printing, is introduced, as shown in Fig. 8 . To form HV bumps that are of a uniform height, the LV-SoP process used in a previous study is supplemented [10] . The double-printing method is a process for forming an HV bump using the LV bump as a seed. As shown in Fig. 8 , the HV-SoP process is carried out using a PCB with an already formed LV solder bump. The height of the solder bumps is measured based on the principle of white-light scanning interferometry (WSI).
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Schematic diagrams of double printing method for HV-SoP.
To obtain a uniform height of the solder bumps, a coining process is performed using a flip-chip machine, as shown in Fig. 9 . The coining process is carried out by applying a force of 2.5 g/bump and a temperature of 200°C for 30 s.
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Schematic diagrams of coining process with load of 2.5 g/bump and temperature of 200°C for 30 s.
III. Results and Discussion
Initially, to obtain a lower deviation of bump height, the oxygen concentration was controlled, which is one of the important parameters of the SoP process, as shown in Fig. 10 . The SBM used in the experiment includes a reductant of 10 phr and a solder powder, of 30% in volume, as described in Section II-1. The PCB printed SBM using mask M3 (see Table 2 ) was reflowed at under 240°C with a heating rate of 1°C/s, and this was held for 30 s. After setting conditions such as mask, temperature, heating time, and printing method, the oxygen concentrations were controlled from 1,000 ppm to 210,000 ppm. We already know that the volumetric mixing ratio of the resin and solder powder in the SBM is 70:30, as described in Section II-1. Therefore, the solder reaction ratio can be easily calculated using equation (1). As shown in step 2 of Fig. 6 , the solder particles close to the Cu pad are involved in the formation of a solder bump, but the rest of the solder should be left to the end of the process without participating in the solder bumping reaction. Before the temperature reaches the melting point of the solder, the reductant is activated for removing the oxide layer of the solder powder, and the molten solder can be wetted on the Cu pads. Since the density of solder is higher than that of resin, molten solder sinks to the metal pads under the influence of gravity [19] . When the oxygen concentration is low, it can help to activate of the reductant. As a result, reductant can prevent solder powders and Cu pads from oxidation more efficiently. The wetting force of the solder will then increase [20] [21] . As shown in Fig. 10 , when the oxygen concentration is less than 10,000 ppm, the reactivity of the reductant contained in the SBM rapidly increases with excessive solder bumps, whereas an insufficient number of solder bumps are formed when the oxygen concentration is high. Thus, the formation of bumps and the reactivity of SBM can be adjusted by controlling the oxygen concentration. In this result, we split the oxygen concentration into two regions: 1) a linear region from 1,000 ppm to 10,000 ppm, which makes it difficult to control the reaction, and 2) a constant region of 10,000 ppm to 210,000 ppm, where it is easy control the reaction.
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Solder reaction ratio associated with changes in oxygen concentration.
To form a high volume of solder bumps, various process conditions and reaction factors, including the oxygen concentration, are adjusted, as shown in Table 3 and Figs. 11 19 .
Optimization of processing parameters forFigs. 12-18.
Figure Mask Oxygen concentration (ppm) Printing method
12-13 M1, M3 12,000 Single
14 M3 1,000, 12,000, 210,000 Single
14-18 M3 12,000 Single, double
As mentioned in Table 2 and Fig. 7 , we designed four guide masks to confirm the difference in the edge bumps according to the printing area, which is controlled by the design of the guide mask. Each mask used in the experiment has a margin of either 100 µm, 500 µm, 1,000 µm, or 2,000 µm from the edge. To confirm the edge effect according to the mask design, the bump height of 25 metal pads on the “edge side” in 625 pads (25 × 25) is measured, as shown in Fig. 11 . The bump height is measured from the base of the metal pad. Experimental results show that M3 and M4, which have margins of 1,000 µm and 2,000 µm, respectively, form more uniform bumps than the other narrow margins of M1 and M2. To compare the mask effect more clearly, two types of stencil mask, M1 and M3, with different designs are chosen to confirm the effect of the printing guide, as shown in Fig. 12 . Stencil masks M1 and M3 are designed for checking the difference in bumps between the center and edge portions.
The shape of the printed SBM crumbles during a reaction because the viscosity of SBM is decreased, as shown in Fig. 12 . Accordingly, a printed SBM has a noticeably flattened hemispherical shape based on the influence of low surface tension and gravity. For this phenomenon, the center of the PCB has a sufficient amount of solder, but the edge portion of the PCB has an insufficient amount. Thus, when mask M1, which has a narrow margin, is used as a guide, the edge side of the PCB has an insufficient amount of solder, as shown in Fig. 12(a) . For the experiment, SBM paste was prepared with a reductant of 10 phr and solder powder of 30% in volume. The SBM-printed PCBs were reflowed at 240°C with a heating rate of 1°C/s and held for 30 s at 12,000 ppm in an SMT machine. As expected, when using mask M1, bumps of the edge portion have an insufficient amount of solder, as shown in Fig. 11 . However, when using oversized mask M3, these defects are greatly reduced, and the bumps are more uniform with a sufficient amount of solder.
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Average, maximum, and minimum height of bumps along the different margins of masks from edge of pads.
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Schematic diagrams of solder bumps on PCB after SoP process with stencil masks (a) M1 and (b) M3.
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Optical photographs of solder bumps on PCB after SoP process with stencil masks (a) M1 and (b) M3.
To adjust the oxygen concentration, we tested the following three different conditions that were selected based on the results of the previous test shown in Fig. 10 : 1,000 ppm of the linear region, and 12,000 ppm and 210,000 ppm as the minimum and maximum values of the constant region. SBM paste with a reductant of 10 phr and solder powder of 30% in volume was used. The temperature was increased to 240°C, with a heating rate of 1°C/sec, and held for 30 s, as in the above conditions. Figure 14 shows the results of the bumping formation in accordance with the changes in oxygen concentration. For 1,000 ppm in the linear region, excessive solder bumps were made because of the vigorous activity of the reductant, as shown in Fig. 14(a) . However, as shown in Fig. 14(b) , when the oxygen concentration was adjusted to 12,000 ppm for the constant region, uniform solder bumps having a sufficient amount of solder were obtained. In addition, for 210,000 ppm in another constant region, insufficient solder bumps were formed, as shown in Fig. 14(c) . From this data, we can confirm that the oxygen concentration is an important factor of the bumping process. When the oxygen concentration is increased, the amount of reacted solder is decreased. An inert atmosphere minimizes the oxidations on the solder powder and metal pads to be wetted. The results in Fig. 14(b) show that the 12,000 ppm oxygen concentration is the most stable and that this is the most suitable concentration for forming uniform bumps on all pads.
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Optical photographs of solder bumps on PCB after SoP process with oxygen concentrations: (a) 1,000 ppm, (b) 12,000 ppm, and (c) 210,000 ppm.
To form HV-SoP using a single printing method, thick SBM printed on a PCB is required. The thickness of the paste should be increased to allow a sufficient amount of solder particles for the bumping reaction. However, as the thickness of the printed paste becomes thicker and thicker, the chance for the solder particles to form irregular-sized lumps, which will cause an excessive bump, also increases. Thus, by using the single-printing method, it is difficult to obtain a uniform height of the solder bumps, because it is hard to control this reaction. To resolve this problem, a double printing method was proposed. For the first step, the LV-SoP process was performed using seed bumps, and SBM was then reprinted on the low-volume bumps to create high-volume bumps, as shown in Fig. 8 .
Figures 15 18 show the differences in bump height between the single- and double-printed substrates. From the SEM images and measurements of the solder bump heights, it can be seen that the double printing method is the more suitable for making HV-SoP.
To form uniform LV-SoP and HV-SoP, a reliable mask, M2, and a 12,000 ppm oxygen concentration in a constant region are used. Figure 15(a) shows an SEM image of LV-SoP after single-printing. The average, maximum, and minimum heights of the LV solder bumps are 10.67 µm, 15.8 µm, and 6.3 µm, respectively, as shown in Fig. 15(b) .
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(a) SEM image of solder bumps after single printing method and (b) measured height of solder bumps.
Figure 16 shows a cross-sectional SEM image of LV-SoP. Uniform LV bumps with a lower height than the solder resist can be seen in Fig. 16 . Using LV-SoP as the seed, HV-SoP is formed by the double printing method, as shown in the second printing and second reflow in Fig. 8 . Figure 17(a) shows an SEM image of HV-SoP after double-printing. The average, maximum, and minimum heights of the HV solder bumps were measured as 33.1 µm, 44.8 µm, and 27.4 µm, respectively, as shown in Fig. 17(b) . The HV-SoP, which has solder bumps of height about 10 µm higher than the solder resist, can be confirmed through the cross-sectional SEM image shown in Fig. 18 . The coining process was carried out to reduce the distribution of height, as indicated in Fig. 9 . Figure 19 shows an SEM image of the high-volume bumps after the coining process. The average, maximum, and minimum heights of the solder bumps after coining were 27.44 µm, 28.2 µm, and 26.3 µm, respectively, as shown Fig. 19(b) . All of the bumps are higher than the solder resist. HV-SoP formed using the double printing method can develop an electrical interconnection through flip-chip bonding.
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Cross-sectional SEM image of solder bumps on PCB after SoP process single printing method.
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(a) SEM image of solder bumps after double printing method and (b) measured heights of solder bumps.
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Cross-sectional SEM image of solder bumps on PCB after SoP process with double printing method.
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(a) SEM image of solder bumps after coinning process and (b) measured heights of solder bumps.
In the near future, the flip-chip bonding process between a substrate with high-volume bumps and a device without a Cu pillar will be investigated.
IV. Conclusion
A novel HV-SoP technology for a fine-pitch substrate with Sn/3.0Ag/0.5Cu solder was developed. In this study, high-volume solder bumps on an entire Cu pad were achieved using SBM without a mask on a PCB. The average height of these solder bumps was 27.44 µm, which is higher than a solder resist by approximately 10 µm. HV-SoP is an appropriate technology to replace the expensive solder bumping process and is expected to be utilized universally in the semiconductor packaging process. In this paper, research was mainly focused on a feasibility identification of the HV-SoP process under a laboratory scale. In addition, the throughput (yield) issue based on the present research results should be precisely managed by collaboration with an industry partner for commercialization.
This work was supported by KEIT, IT R&D program of Daedeok Innopolis Foundation (Grant No. A2012DD002, the industrialization of package electrode ESP materials for smart phone), the IT R&D program of MKE/KEIT (Grant No. 10041416, the core technology development of light and space adaptable new mode display for energy saving on 7 inch and 2 W), and the R&D program of ISTK (development of an image-based, real-time inspection and isolation system for hyperfine faults) and Electronics and Telecommunications Research Institute (ETRI), Rep. of Korea.
BIO
Corresponding Author jhson87@etri.re.kr
Jihye Son received her BS and MS degrees in chemical engineering from the Department of Advanced Organic Materials and Textile System Engineering, Chungnam National University, Daejeon, Rep. of Korea, in 2010 and 2012, respectively. Since 2012, she has been working for the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea. Her research interests include design and synthesis of organic polymers and characterization of advanced polymers.
yseom@etri.re.kr
Yong-Sung Eom received his BS degree in aeronautical engineering from Korea Aerospace University, Hwajeon, Rep. of Korea and his MS degree in aeronautical engineering from the Department of Aerospace Engineering, Korea Advance Institute of Science and Technology, Seoul, Rep. of Korea, in 1988 and 1991, respectively. He worked at the Korea Institute of Aeronautical Technology, Korean Air Ltd., Seoul, Rep. of Korea, as a design and process engineer for the composite materials of the MD-11 Aircraft Spoiler from 1991 to 1995. In 1999, he received his PhD degree in material engineering from the Department of Material Science Engineering, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland. After returning to Korea, he worked at Hynix Semiconductor Ltd., Incheon, Rep. of Korea, as a packaging engineer for memory devices from 2000 to 2001. Since 2001, he has been with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, where he has been working as a packaging engineer. His research activities include the development of interconnection materials based on the polymer for an electronic packaging and process design for 3D-IC and MEMS packaging.
kschoi@etri.re.kr
Kwang-Seong Choi received his BS degree in material science and engineering from Hanyang University, Seoul, Rep. of Korea, in 1993; his MS degree in electronic material science and engineering in 1995; and his PhD degree in telecommunication engineering in 2008 from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea. From 1995 to 2001, he developed chip-scale and PoP packages, as well as designing high-speed electronic packages for DDR and Rambus, and RF devices for Hynix Semiconductor Ltd., Incheon, Rep. of Korea. He has been developing high-speed packaging technologies for optical devices such as modulators and receivers since 2001 at the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea. Currently, his research areas include the development of the materials and processes for 3D ICs with through silicon via, next-generation displays, and silicon photonics.
hlee435@etri.re.kr
Haksun Lee received his BS degree in electrical engineering from Purdue University, West Lafayette, IN, USA, in 2010 and his MS degree in electrical engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2012. Since 2012, he has been working with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, where he is involved in research on packaging processes. His research interests include multiphysics modeling of novel interconnections and packaging process design.
hcbae@etri.re.kr
Hyun-Cheol Bae received his BS and MS degrees in electrical engineering from Dongguk University, Seoul, Rep. of Korea, in 1999 and 2001, respectively. He joined the SiGe Research Team, Electronics and Telecommunications Research Institute (ETRI), Daejeon, Rep. of Korea, in 2001 and worked as a design and process engineer on MMIC and passive devices. He moved to the Packaging Research Group of ETRI in 2007 and has been working as a packaging engineer. In 2009, he received his PhD degree in electrical engineering from Chungnam National University, Daejeon, Rep. of Korea. His research interests include the design and fabrication of integrated passive devices, 3D stacked chip packaging using TSV, and wafer-level packaging for MEMS devices.
leejinho@etri.re.kr
Jin-Ho Lee received his BS degree in physics from Kyungpook National University, Daegu, Rep. of Korea, in 1980; his MS degree in physics from Korea University, Seoul, Rep. of Korea, in 1982; and his PhD degree in physics from Kyungpook National University, in 1998. Since 1982, he has been with the Electronics and Telecommunications Research Institute (ETRI), Daejeon, Rep. of Korea, where he has been involved in the development of semiconductor devices and advanced flat panel display devices, such as memory devices, TFTs, flexible devices, and power devices. He is currently the managing director of the IT Components and Materials Industry Technology Research Department, ETRI.
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