Many methodologies for clock mesh networks have been introduced for two-dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three-dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through-silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits. The CMOS technology process is continuing to decline, and as the design of its integrated circuits becomes more complex, the capability to optimize performance is fast approaching the limit. Three-dimensional integrated circuits (3D ICs) using through-silicon vias (TSVs) have attracted considerable attention as an important technology; these are continuing the decreasing technology process trend that Moore predicted [1] . A 3D IC connects multiple dies that are vertically stacked on top of each other. The TSVs are used to connect the vertically stacked dies. A TSV is a via through the dies. This 3D stacking technology can significantly reduce mean and maximum wirelength; power consumption; chip area; and signal delay [2] – [3] . The methods of reducing the wirelength with TSVs in 3D ICs can also be applied to clock distribution networks [4] – [6] . A clock distribution network functions to propagate a clock signal from a clock source to clock sinks. The clock skew is defined as the maximum difference of a clock signal’s arrival time from a clock source to all of the clock sinks. A high clock skew directly affects the maximum frequency and timing of circuits, which leads to a degradation of chip performance. According to the International Technology Roadmap for Semiconductors projection [7] , the clock skew is generally required to be less than 3% to 4% of a clock period in a clock network design. To reduce the clock skew variation, many methods have been studied including variation-aware buffer and wire sizing [8] , variation-aware routing [9] , link insertion in clock trees [10] , and leaf-level mesh [11] – [12] . Among these different methods to reduce clock skew variation, the leaf-level mesh with a top-level tree demonstrates highly effective results in several commercial chips [11] . The clock mesh network connects the clock sinks to the metal wires by intersecting vertical and horizontal metal wires. The clock signal is distributed from a clock source with a top-level tree to the clock sinks through the mesh driver located on the vertical and horizontal metal wire intersection. The clock mesh network requires more resources, including wirelength and power, than the clock tree network [11] . In addition, in a 3D clock mesh network, the wirelength is increased in proportion to the number of dies. For this reason, clock trees is more actively researched than clock mesh. However, a clock mesh network guarantees a global skew variation, while a clock tree network guarantees a local skew variation. Well known for having a low global skew variation, the clock mesh network is mainly used in microprocessor design for high performance. With this in mind, researches on 3D clock mesh networks focus on reducing resources such as wirelength and power. Because of the advantages of a clock mesh network, many studies related to mesh synthesis and optimization have been conducted [12] – [20] . The work of [13] proposed to remove only mesh wires that did not significantly impact on the clock skew of the mesh. The authors in [13] also suggest the method of buffer placement and sizing. The work of [14] aims at connecting clock sinks to mesh wires using a Steiner tree avoiding individually connecting clock sinks to mesh wires in an effort to reduce the stub wire of the mesh. A method is proposed in [12] to determine the buffer driver insertion and sizing and to remove the mesh wire for power consumption. In [15] , the authors consider a timing delay on the path of the combinational circuits to determine the size of the initial mesh, by considering the timing when the clock mesh is constructed. A non-uniform clock mesh grid is proposed in [16] – [17] to reduce power consumption. A method is proposed in [18] to generate the clock mesh grid wires using an integer linear programming formulation to minimize the wirelength of the mesh. The works of [19] and [20] propose methods to simultaneously reduce the wires of a mesh grid and the stub wires of the mesh by placing the mesh grid wires close to the clock sinks. A method is proposed in [21] – [22] to determine the initial mesh size by considering the clock skew and wirelength. They also proposed a method for buffer placement, sizing, and wire sizing. In these works with 2D clock mesh networks, the clock signal is propagated to clock sinks in the x - and y -direction. However, in a 3D clock mesh network, the designs are more complicated because the clock signal is propagated to the clock sinks in three directions ( x -, y -, and z -direction) using clock TSVs. In this sense, conventional 2D clock mesh network methods [12] – [22] did not consider the method of clock TSV insertion for propagating the clock signal on multiple dies. When a conventional 2D clock mesh network is directly applied to a 3D IC by using clock TSVs regularly inserted at nodes of the mesh, the low skew variation is guaranteed but wirelength is increased. The wirelength is directly affected by the position and number of clock TSVs, and any unnecessary increases in wirelength can cause thermal issues on a 3D IC consisting of multiple vertically stacked dies. In addition, if a conventional 2D clock mesh network is directly applied to a 3D IC without using TSV insertion, then the reliability of the chip is decreased. Also, this method will not guarantee the global clock skew variation and will lead to a decrease in chip performance. For these reasons, it is necessary to study 3D ICs consisting of 3D clock mesh networks with clock TSVs. In this work, we present an effective method to reduce the clock skew and wirelength using clock TSVs in a 3D clock mesh network. The contributions of this paper are as follows: The rest of the paper is organized as follows. In Section II, we discuss the preliminary research and background for the 2D clock mesh design. In Section III, the proposed 3D clock mesh design methodology is explained in detail. In Section IV, the simulation results are presented. The paper ends with concluding remarks in Section V. The most important elements in clock mesh design are the wirelength and clock skew. In a clock mesh network, because of a wire’s resistance and capacitance, wirelength affects power consumption. A high clock skew degrades the maximum operating frequency of the chip and causes a signal timing issue. We present stub and mesh grid wires, which are affected by the mesh size in a 2D clock mesh network (see Section II-1). In Section II-2, clock skew and the size of the mesh in a 2D clock mesh network are discussed. In a 2D clock mesh network, the total wirelength L _total is calculated as follows: (1) $$L_{\text{total}}=L_{\text{top}}+L_{\text{mesh}}+L_{\text{stub}},$$ where L _top is the wirelength of the top-level tree, L _mesh is the wirelength of the mesh grid wire, and L _stub represents the stub wirelength of the stub wire, which is the wire connecting the mesh grid to the clock sink (see Fig. 1 ). The stub and mesh grid wires implicitly affect the power consumption of the circuit. As the wirelength increases, the entire capacitance and power consumption of the circuit are increased. Consequently, to reduce power consumption in the clock mesh network, we need to reduce both the length of the stub wires and the mesh grid wires. In this paper, to reduce L _mesh , we select the smallest possible mesh size such that the selected mesh has a lower clock skew than the clock skew constraint . We simply insert clock TSVs to reduce L _stub . In [13] , the global clock skew t _skew is estimated as follows: (2) $$t_{skew}=t_{skew}^{\text{buf}}+D_{\text{mesh}}(d_{\max })+D_{\text{stub}}(L_{\text{stub}}^{\text{max}}),$$ where   is the skew introduced by the difference in the maximum and minimum delay on the mesh driver, D _mesh ( d _max ) is the maximum delay from the mesh drivers to the points where the stub wires meet with the mesh grid wires, and is the maximum delay from the points where the stub wires meet with the mesh grid wires to the clock sinks. In (2), D _mesh ( d _max ) and must be reduced to decrease the clock skew. As we move to the right in Fig. 1 , the size of the mesh is increased and t _skew is reduced, because the D _mesh ( d _max ) and are reduced. However, as the size of the mesh increases, the number of horizontal and vertical metal wires increases. Therefore, in this paper, we suggest a method to construct a clock mesh network that considers both L _total and t _skew . The flow of the proposed method is presented in Fig. 2 . The first step is the selection of the mesh size. The uniform size of the mesh on each die is selected when the size of the mesh has both the minimal total wirelength and a lower clock skew than the clock skew constraint. After the size of the mesh is selected, the buffer-inserted top-level tree is constructed to simultaneously transfer the clock signal from a clock source to all of the clock sinks. A clock TSV at the center of die 1 is inserted to transfer the clock signal from die 1 to die 2 with minimum wirelength. After the initial mesh construction, clock TSVs are inserted and the local mesh–sizing algorithm is performed to reduce . In the last step, the buffer assignment, the buffers are inserted to reduce the delay that occurs in the imbalanced L _stub . As mentioned in Section II, the size of the mesh affects both the wirelength and the clock skew. In Fig. 1 , it can be seen that the denser the clock mesh, the lower the value of L _stub . The global clock skew t _skew of a 3D IC is represented below (3) $$t_{skew}=t_{skew}^{\text{buf}}+D_{\text{mesh}}(d_{\max })+D_{\text{stub}}(L_{\text{stub}}^{\text{max}})+D_{\text{TSV}},$$ where the variable D _TSV is the delay caused by inserting the clock TSVs between die 1 and die 2. The total wirelength L _total is represented as (4) $$L_{\text{total}}=L_{\text{top}}+L_{\text{mesh}}+L_{\text{stub}}+L_{\text{TSV}},$$ where the variable L _TSV is the total wirelength of the inserted clock TSVs. We assume that the all clock TSVs have the same wirelength. After the clock signal is instantaneously transferred to each mesh node, the mesh that has a lower L _mesh and L _stub also has a lower t _skew . However, through (4), the sparser mesh has a lower total wirelength than the denser mesh. Therefore, we need to select the size of the mesh by considering both the total wirelength and the clock skew. There are many works that consider the above elements when selecting the mesh size in a two-dimensional integrated circuit. A method is proposed in [23] to select the minimum mesh size so as to reduce both the wirelength and the clock skew on each voltage domain. In [21] , the constraints of the clock skew and wirelength are considered when the initial mesh is constructed so that the total wirelength is lower than L _const and the clock skew is lower than . The proposed mesh size selection algorithm expands upon the initial mesh sizing method of [21] for a 3D clock mesh network with clock TSVs. To select the mesh size of minimal wirelength, we select a candidate mesh size and insert clock TSVs using our proposed method of clock TSV insertion. After the above procedure, we select the mesh size of minimum wirelength by calculating the clock skew. In this paper, we assume that the vertical metal wire m and horizontal metal wire n for the clock mesh are of the same value. In physical IC design, a uniform clock mesh is generally preferred since the mesh grid can be placed between uniform power rails to prevent crosstalk [17] . The detailed proposed mesh size–selection algorithm is presented in Fig. 3 . The proposed mesh size–selection method selects the mesh size having minimum total wirelength when the clock skew of the selected mesh is lower than clock skew constraint. The inputs of the proposed mesh size–selection algorithm are the location of the clock sinks on each die, the clock skew constraint, and the maximum number of TSVs (TSV _max ). We select the minimum candidate mesh size so as to obtain the minimum total wirelength (line 2 of Fig. 3 ). The delay from the clock source to the clock sinks on each die is calculated using (5) and (6) with the Elmore delay model (line 3 of Fig. 3 ). The delay D _sink∈die1 from the clock source to the clock sink located on die 1, where it is directly connected with the clock source, is represented as (5) by Elmore delay modeling. (5) $$D_{\text{sink}\in \text{die}1}=R_{\text{d}}\left(C_{\text{w}}+C_{\text{s}}\right)+R_{\text{w}}\left(\frac{C_{\text{w}}}{2}+C_{\text{s}}\right)+D_{\text{sd}}+D_{\text{d}}.$$ In (5), R _d and R _w are the resistance of the mesh driver and the resistance of the wire, respectively. The variables D _d , D _sd , C _w , and C _s are the intrinsic delay of the mesh driver, the delay from the clock source to the mesh driver, the capacitance of the wire, and the capacitance of the clock sink, respectively. The delay D _sink∈die2 from the clock source to the clock sink located on die 2, where the clock signal is transferred from the clock source to the clock sink through the clock TSVs, is represented as (6) by Elmore delay modeling. (6) $$\begin{array}{l}{D}_{\text{sink}\in \text{die2}}=R_{\text{d}}(C_{\text{TSV}}+C_{\text{d}})+R_{\text{TSV}}(\frac{C_{\text{TSV}}}{2}+C_{\text{Tb}})\\ +D_{\text{Tb}}+R_{\text{Tb}}(C_{\text{w}}+C_{\text{s}})+R_{\text{w}}(\frac{C_{\text{w}}}{2}+C_{\text{s}})\\ +D_{\text{sd}}+D_{\text{d}}.\end{array}$$ The variables R _TSV and R _Tb are the resistance of the clock TSV and the resistance of the clock TSV buffer, respectively. The variables C _TSV , C _d , C _Tb , and D _Tb are the capacitance of the clock TSV, mesh driver, clock TSV buffer, and the intrinsic delay of the clock TSV buffer, respectively. The delay models of the wire, clock TSV, and clock buffer are shown in Fig. 4 . To calculate the delay from the mesh driver on die 1 to the clock sinks on dies 1 and 2, we use the delay model illustrated in Fig. 4 . If the calculated t _skew is higher than , then clock TSVs are inserted to reduce t _skew (lines 4–7). The insertion of the clock TSVs is performed using Algorithm 2 (introduced in Section III-4). If t _skew is higher than after the maximum number of TSVs is inserted, then the above process is repeated by increasing the size of the mesh by one (lines 8–10). During this iteration, the size of the mesh is selected when the clock skew is less than clock skew constraint set by the designer (lines 12–13). After the candidate mesh size is selected, an initial clock TSV needs to be inserted to transfer the clock signal from die 1 to die 2. This is inserted at the center of die 1 so as to propagate the clock signal from die 1 to die 2 with minimum wirelength. In this step, clock TSVs are inserted on die 1 so that the clock signal is propagated to the clock sinks on die 2. We calculate the delay from the clock source to the clock sink with (5) and (6). To obtain a clock skew value that is less than the clock skew constraint, a clock TSV is inserted near to the clock sink having the largest delay from the clock source located in die 2. Figure 5 shows the clock TSV insertion process with a three-step search, and Fig. 6 shows the detailed procedure of the clock TSV insertion method. We assume that the clock sink with the largest delay from the clock source — namely, the target sink — is located at ( x_s , y_s , z_s ) on die 2 (see Fig. 5(a) ). The candidate location of a clock TSV ( x_k , y_k , z_s ) is determined so as to be on the same die as the target sink. The detailed procedure for inserting a clock TSV is as follows. The variables i and n are the number of steps and the number of horizontal (and also vertical) metal wires, respectively. A. Step. 1 ( i = 1) We select the center of each mesh grid as a candidate location for the insertion of a clock TSV (( x_k , y_k , z_s ), line 1). To insert a clock TSV close to the target sink ( x_s , y_s , z_s ), the distance between the candidate locations and the location of the target sink are compared using (line 2) (7) $$\begin{array}{l}\text{dist}=\Vert (x_s-x_k),(y_s-y_k),(z_s-z_k)\Vert \\ \left\{s,k\right\}\in N,N=\left\{1,2,\dots ,n^2\right\}.\end{array}$$ As the distances between ( x_k , y_k , z_s ) and ( x_s , y_s , z_s ) decrease in length, so the wirelength between the target sink and a clock TSV will also decrease. We select the candidate location ( x_i , y_i , z_s ) for the insertion of a clock TSV by using the lowest value from the results of (7) (line 4). B. Step. 2 ( i = 2) The mesh grid that is selected in Section III-4-A, including a candidate location from the result of Section III-4-A, is bisected in both the vertical and horizontal directions by the candidate location. Each center location of the resulting four regions then becomes a new candidate location for a clock TSV ( x_k , y_k , z_s ); these TSVs can be inserted using (8) $$\begin{array}{l}(x_k,y_k,z_k)=(x_{i-1},x_{i-1},z_s)-M_T\frac{1}{n}(\frac{x}{2^i},\frac{y}{2^i},0),\\ t_0=(1,1,0),\\ t_1=(1,-1,0).\end{array}$$ In (8), T is the set consisting of the center locations t ₀ , t ₁ , t ₂ , and t ₃ , of the four regions, divided in both the vertical and horizontal directions by the clock TSV location ( x _i–1 , y _i–1 , z_s ). The location of the clock TSV ( x_i , y_i , z_s ) in Section III-4-B is the lowest value from the results of (7) (lines 7–8 and 4). C. Step. 3 ( i = 3) In this step, the process performed in Section III-4-B is repeated. Through these processes, the candidate location of the clock TSV( x ₃ , y ₃ , z ₃ ) that is selected in this step may not be the closest location to the target sink. In other words, the distance from the target sink to the selected location in this step may not be closer than the same corresponding distances found in the previous steps. Therefore, to insert the clock TSV at the closest possible location to the target sink, the results of all three steps are compared (lines 11–12). The clock signal will be propagated to die 2 through a clock TSV from die 1 when the clock TSV is vertically inserted. After the clock TSV is connected to a mesh node on die 1, the clock signal is transferred simultaneously to both the mesh nodes, where the clock TSV is connected, and the other mesh nodes on die 2. However, the proposed clock TSV insertion algorithm may not situate the clock TSV at the position of the mesh node on die 1. To solve the above issue, we proposed a method to locally increase the size of the mesh on die 1. When the size of the mesh is locally increased, the mesh nodes are added. The clock TSV is inserted at the added mesh node on die 1 (line 13). The method for locally increasing the size of the mesh on die 1 is described in Fig. 7 below. The vertical and horizontal mesh wires are generated at the clock TSV location on die 1 and expand in the vertical and horizontal directions of the points until the uniform mesh grid wires are connected. Figure 7(a) shows the location of a clock TSV determined in step 1, and Figs. 7(b) and 7(c) show the locally increased size of the mesh on die 1 when a clock TSV is inserted. Figure 8 shows an example of the increased size of mesh on die 1. The clock TSVs that are inserted close to the target sinks, by Algorithm 2, affect the delay from the clock source to not only the target sink but also the other clock sinks. Therefore, the clock skews are recalculated by using (5) and (6). The clock TSV insertion is repeated until the clock skew is less than the clock skew constraint. The iteration is completed when the maximum number of clock TSVs (# TSV _max ) have been used. Figure 8(a) shows the inserted clock TSVs on the clock mesh. Figure 8(b) shows an example of the clock TSV on die 2 that connects not only to the target sink but also to other clock sinks; they are connected at the clock TSV if the distance from the clock TSV is closer than the nearby mesh nodes. The stub wirelength on die 2 is relatively longer than that on die 1 because the size of the mesh on die 1 is larger than that of die 2. As the wirelength is increased, the signal delay from the clock source to the clock sinks is generally increased since both the capacitance and resistance of the wire are increased [24] . In this step, we propose a method to assign buffers to reduce the delay from the longer stub wirelength. The method to insert buffers to reduce the delay is well studied in [24] – [25] . The proposed method in [25] assumes that the distance from the source to the nearest buffer is x and that the distance between each buffer is y . However, the delay equations proposed in [25] are complex and have a lot of variables. In [24] , the authors assume that the distance between each buffer is x ; therefore, the delay equations are more simple than in [25] . In this paper, we proposed a buffer assignment method to find the optimized number of buffers using the simple delay equation presented in [24] , which can reduce the delay. We assume that all of the wire parameters, such as the capacitance per unit length and the resistance per unit length, are the same; although these parameters are in fact different. We assume that a number of buffers, k , are inserted between either the clock TSV on die 2 or the mesh driver on die 1 and the clock sink. To insert the buffers on the highly delayed wire, the buffers are selected in the buffer library. To find k , the minimum delay D _m is obtained by (9) $$\begin{array}{l}{D}_{\text{m}}=R_{\text{Tb}}\left(c_{\text{w}}x+C_{\text{b}}\right)+D_{\text{Tb}}+\frac{1}{2}{r}_{\text{w}}{c}_{\text{w}}{x}^2+r_{\text{w}}x{C}_{\text{b}}\\ +\left(k-1\right)\left[R_{\text{b}}\left(c_{\text{w}}x+C_{\text{b}}\right)+D_{\text{b}}+\frac{1}{2}{r}_{\text{w}}{c}_{\text{w}}{x}^2+r_{\text{w}}{c}_{\text{w}}{C}_{\text{b}}\right]\\ +R_{\text{b}}\left[c_{\text{w}}\left(L-kx\right)+C_{\text{s}}\right]+D_{\text{b}}+\frac{1}{2}{r}_{\text{w}}{c}_{\text{w}}{\left(L-kx\right)}^2\\ +r_{\text{w}}\left(L-kx\right)C_{\text{s}}.\end{array}$$ In (9), R _Tb , R _b , r _w , and c _w are the resistance of the buffer with the clock TSV, the resistance of the buffer, the resistance per unit length of wire, and the capacitance per unit length of wire, respectively. The variables C _b , C _s , D _Tb , and D _b are the capacitance of the clock buffer, clock sink, the intrinsic delay of the buffer with the clock TSV, and clock buffer, respectively. We assume that the clock buffers are inserted at the position where the wirelength L from a clock TSV buffer to a clock sink is divided by k + 1. According to this assumption, the distance between each buffer is x = ( k + 1) ⁻¹ . We assign x to (9), and the delay D _m is represented as follows: (10) $$D_{\text{m}}=\left(k+1\right)\left[R_{\text{b}}\left(C_{\text{w}}\frac{1}{k+1}+C_{\text{b}}\right)+D_{\text{b}}+\frac{r_{\text{w}}{c}_{\text{w}}{L}^2}{2{\left(k+1\right)}^2}+\frac{r_{\text{w}}{c}_{\text{w}}L}{k+1}\right].$$ According to the method in [25] , it is effective to insert a buffer when the delay from the buffer insertion is less than the delay without the buffer. This method is generalized as follows: (11) $$D_{\text{m}}\left(k-1\right)>D_{\text{m}}\left(k\right).$$ Equation (10) is assigned to (11), and the result is represented as follows: (12) $$R_{\text{b}}{C}_{\text{b}}+D_{\text{b}}+\frac{r_{\text{w}}{c}_{\text{w}}{L}^2}{2(k+1)}-\frac{r_{\text{w}}{c}_{\text{w}}{L}^2}{2k}<0.$$ Rearranging (12) in terms of k we have (13) $$k^2+k-\frac{r_{\text{w}}{c}_{\text{w}}{L}^2}{2\left(R_{\text{b}}{C}_{\text{b}}+D_{\text{b}}\right)}<0.$$ Then, the solution of (13) is as follows: (14) $$k<\frac{-1+\sqrt{1+2\frac{r_{\text{w}}{c}_{\text{w}}{L}^2}{(R_{\text{b}}{C}_{\text{b}}+D_{\text{b}})}}}{2}.$$ We are able to obtain the optimal number of buffers k with the minimum delay D _m by using (14). The clock skew t _skew is then calculated. If the calculated clock skew is greater than the clock skew constraint, then the above procedure is repeated for the highly delayed wire until the clock skew is lower than the clock skew constraint. The algorithms were implemented in C++, and simulations were run on a Linux workstation with 2 GB of RAM. The proposed methods were verified using experiments performed on the ISCAS89 and ISPD 2010 benchmark circuits. The proposed method uses an existing placement result as the input. We compared our result with the result from the 2D clock mesh network in [21] and [22] because the clock mesh network in a 3D IC has not yet been presented. The study in [21] and [22] only constructed a 2D clock mesh network. We expand the results from [21] and [22] to a 3D clock mesh network. To do this, we stacked the same two dies vertically. The nominal skew constraint is 75 ps, which is the same as in [21] . We used 12 different buffer sizes with a maximum-capacitance limit ranging from 60 fF to 300 fF; this is the same as in [21] . We used buffer sizes with a maximum-capacitance limit ranging from 60 fF in the proposed Algorithm 3. The clock skew constraint used in Algorithms 1 and 2 is 50 ps. The clock skew constraint used in Algorithm 3 is 35 ps. We also used the same 65 nm technology parameters, transistor model from [21] , and a similar set of benchmark circuits. In this paper, the resistance of the clock TSV is 0.053 Ω, and the capacitance of the clock TSV is 27.9 fF. The variation parameters considered are the buffer channel lengths, power supply variation, and sink load capacitance variation. These parameters are varied with a 5% standard deviation from their nominal value. We model the effects of the variation in the top-level tree in a similar way as [21] by modeling the input arrival time for the mesh drivers with a random variable. We used a range of ±25 ps for the clock skew between two mesh drivers and used the same slew for all of the mesh buffers. The methods used in the simulation are presented as follows: Table 1 shows the results of the 3D clock mesh network with the maximum clock skew of ±50 ps between mesh drivers and a slew of 50 ± 10 ps on ISCAS benchmarks. The parameters in Table 1 are “BA” for the buffer area, “WL” for the total wirelength, “ μ _skew ” for the mean deviation of the clock skew, and “σ _skew ” for the standard deviation of clock skew. The parameters μ _skew and σ _skew are obtained through a Monte Carlo simulation in HSPICE. The columns under “Ratio” are the relative value with respect to “Proposal.” For the ISCAS benchmarks, the proposed buffer assignment method, denoted by “ [21] _EX with buffer,” shows the clock skew results reduced by 11.31% and the clock skew variation reduced by 30.02%, on average, compared to the method in [21] . However, the buffer area is generally increased when the clock buffers are inserted. Our proposed buffer assignment method increases the buffer area by 8.92%, on average, by inserting the buffers. The method with the iterative deletion of the buffer, which is proposed in [22] , shows better performance than our buffer insertion algorithm. However, our proposed method with Algorithms 1 and 2, as well as the buffer assignment, shows a better performance in terms of buffer area, wirelength, and clock skew variation. Table 2 shows the results of the 3D clock mesh network on ISPD 2010 benchmarks. Our proposed algorithm shows the clock skew results reduced by 4.2% and the wirelength reduced by 12.2%, on average, compared to the method in [22] , which is expanded to the 3D clock mesh network. Table 3 shows the effects of variation on the top-level tree by modeling the input arrival time for the mesh drivers. The different parameter in Table 3 is the skew variation, which represents the clock skew difference between the mesh drivers. We obtained the reduced total wirelength and clock skew shown in Table 1 and Table 2 . These results show the effectiveness of our proposed methods. When we assign the variation of skew to the buffers constructing the top-level tree, the buffer area is increased by approximately 2.48%, on average, more than the conventional method in [21] that was expanded to 3D However, instead of a buffer area increased by 2.48%, our methods reduce the total wirelength by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. In this paper, we presented effective methods, used in the construction of a 3D clock mesh network, for the selection of mesh size, TSV insertion, local mesh sizing, and buffer assignment. From the simulation results, we verified that our proposed mesh size selection, clock TSV insertion, and local mesh sizing methods can reduce the total wirelength and that the proposed buffer assignment method can reduce the clock skew and clock skew variation. The simulation results show that the total wirelength is reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%; this is compared with the conventional method in [21] that was expanded to 3D with the same number of clock TSVs as used in the proposed methods. These advantages are possible with the buffer area increased by 2.49% on the benchmark circuits. The above results show that our proposed method can construct an effective and powerful 3D clock mesh network. ruddls1116@gmail.com Kyungin Cho received his BS degree in electronics engineering from the school of Electronics Computer Engineering, Inha University, Incheon, Rep. of Korea, in 2010. From 2010 to 2012, he was a researcher at the HE Department of LG Electronics, Pyeongtaek, Rep. of Korea. Since 2013, he has been with the Department of Electronics Computer Engineering, Hanyang University, Seoul, Rep. of Korea, where he is currently pursuing his MS degree. His main research interest is SoC design methodology, including the physical design and automation of 3D ICs. jangcj@hanyang.ac.kr Cheoljon Jang received his BS and MS degrees in electronics and computer engineering from the school of Electronics Computer Engineering, Hanyang University, Seoul, Rep. of Korea, in 2011 and 2013, respectively. He is currently pursuing his PhD degree in nanoscale semiconductor engineering at Hanyang University. His main research interest is SoC design methodology, including the physical design and automation of 3D ICs. Corresponding Author  jchong@hanyang.ac.kr Jong-wha Chong received his BS and MS degrees in electronics engineering from Hanyang University, Seoul, Rep. of Korea, in 1975 and 1979, respectively and his PhD degree in electronics and communication engineering from Waseda University, Shinjuku-ku, Tokyo, Japan, in 1981. Since 1981, he has been a professor of the Department of Electronics Engineering, Hanyang University. From 1979 to 1980, he was a researcher at the C&C Research Center of Nippon Electronics Company, Shiba Minato, Tokyo, Japan. From 1983 to 1984, he was a visiting researcher at the Korean Institute of Electronics & Technology, Seongnam, Rep. of Korea. Between 1986 and 2008, he was a visiting professor at the University of California, Berkeley, USA. He was the chairman of the CAD & VLSI society of the Institute of the Electronic Engineers of Korea in 1993. In 2007, he was the president of the IEEK, and from 2009 to 2010, he was the president of the KIEEE. He is currently the chairman of the Fusion SoC Forum. His main research interests are SoC design methodology; including memory centric design and the physical design and automation of 3D ICs; indoor wireless communication SoC design for ranging and location; video systems; and power IT systems.