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3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters
3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters
ETRI Journal. 2014. Oct, 36(6): 924-930
Copyright © 2014, Electronics and Telecommunications Research Institute(ETRI)
  • Received : February 18, 2014
  • Accepted : August 05, 2014
  • Published : October 01, 2014
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About the Authors
Yongho Seo
Youngkyun Cho
Seong Gon Choi
Changwan Kim

Abstract
This paper presents a 0.13 μm CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of –1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.
Keywords
I. Introduction
In high-data-rate wireless systems, such as 3GPP Long-Term Evolution (LTE) and Worldwide Interoperability for Microwave Access (WiMAX), tremendous efforts to enhance power amplifier (PA) efficiency have led to new transmitter architectures employing a particular 1-bit encoder, such as delta-sigma modulation (DSM) or pulse-width modulation (PWM) [1] [4] . However, due to such encoders having low coding efficiency, excessive power loss and efficiency degradation cannot be avoided. To enhance the cording efficiency of an encoder, we previously proposed the new transmitter architecture [5] shown in Fig. 1 . In Fig. 1 , a multilevel envelope delta-sigma modulation (ML-EDSM) scheme is used to enhance the coding efficiency using a 3-level (zero, A ( t ) max /2, and A ( t ) max ) envelope signal instead of a conventional 2-level signal. However, 3-level envelope modulation can degrade the PA efficiency, as the PA cannot operate in a saturated region under a single supply voltage for a middle-level envelope signal A ( t ) max /2. To overcome this problem, a dual-supply injection method is applied in the PA, as shown in Fig. 1 . For the maximum-level envelope signal, A ( t ) max , the PA operates in the saturated region under a high supply voltage of V DD1 . However, when A ( t ) max becomes A ( t ) max /2, the dual-supply network switches V DD1 ( V DD1 > V DD2 ) to the low supply voltage of V DD2 concurrently. Accordingly, the PA can always operate in the saturated region for the 3-level envelope signal, avoiding any degradation of its efficiency. Finally, the proposed transmitter can achieve high encoding efficiency without degradation of the efficiency of the PA, leading to a new alternative for the implementation of high-efficiency transmitters.
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Block diagram of proposed transmitter in [5].
This paper proposes a 2.6 GHz 3-level EDSM RF signal generator for the previously proposed PA architecture in [5] , which is implemented in 0.13 μm CMOS technology. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a differential-to-single-ended signal converter (D2S), and a Class AB wideband driver amplifier (DA). In Fig. 1 , the envelope signal, a ( t ), is converted to a 3-level PWM signal by an ML-EDSM for higher coding efficiency, while the baseband I-Q phase signals, cos ϕ ( t ) and sin ϕ ( t ), are up-converted into a pure phase-modulated 2.6 GHz signal by an I-Q phase modulator. Using these two signals, an up-conversion mixer and D2S generate a 3-level EDSM RF signal centered at 2.6 GHz. The 3-level EDSM RF signal is further amplified by a DA and then delivered to a PA. This is the first paper to describe a 3-level EDSM RF signal generator for high-efficiency transmitters.
II. Circuit Design
In Fig. 2 , the baseband I-Q phase signals, cos ϕ ( t ) and sin ϕ ( t ), which are generated from our Coordinate Rotation Digital Computer (CORDIC), are up-converted into a 2.6 GHz phase-modulated signal by the proposed I-Q phase modulator. The 2.6 GHz phase-modulated signal is used to turn on and turn off the switching transistors of the following up-conversion mixer. The 2.6 GHz quadrature LO tones for the I-Q phase modulator are provided from an internal divide-by-two circuit. The proposed I-Q phase modulator adopts a double-balanced quadrature passive mixer topology to minimize LO leakage and so as to have low distortion. However, due to no reverse isolation in the passive mixer, an I-Q crosstalk problem occurs since one mixer switch from the I channel and the other mixer switch from the Q channel are simultaneously operating at any given moment [6] [7] . To mitigate the I-Q crosstalk problem, instead of an LO-2LO mixer [6] or a 25% duty-cycle passive mixer [7] , a passive mixer topology (described in [8] ) has been modified and then used in this work. The LO-2LO mixer and 25% duty-cycle mixer need additional circuits, such as LO buffers and LO clock generators. This leads to additional dc current consumption and chip area. In the proposed mixer, shown in Fig. 2 , for conventional 50% duty-cycle LO clocks, two switches are connected in series to form an AND function to achieve an effective 25% duty-cycle switching. Thus, I and Q channels cannot be connected at the same time, which is the same condition of the 25% duty-cycle mixer. Accordingly, the proposed passive mixer can eliminate the I-Q crosstalk problem without additional circuit blocks or dc power consumption.
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Schematic diagram of proposed 3L-EDSM RF signal generator.
To drive the up-conversion mixer effectively, the phase-modulated signal is further amplified by a wideband buffer, which has a 3-bit gain-control function. Since the phase-modulated signal has a constant envelope, the proposed wideband buffer is Class B biased, which leads to low dc power consumption. In addition, to preserve fast phase transitions in the output waveform, the wideband buffer uses an RLC resonant load to achieve a bandwidth of 1.5 GHz centered at 2.6 GHz.
In Fig. 2 , the second stage is the up-conversion mixer ( M a , M b , M c , and M d ), which synthesizes the 3-level EDSM RF signal by using two input signals: a single - ended 3-state (0 V, 0.25 V, and 0.5 V) PWM signal from the ML-EDSM circuit and a differential 2.6 GHz phase-modulated signal from the I-Q phase modulator. To minimize LO leakage, the up-conversion mixer is designed on a double-balanced passive mixer topology, as shown in Fig. 2 . However, since the 3-level PWM input signal is provided as a single-ended signal in our transmitter, one input is connected to the output of the ML-EDSM, but the other is connected to a 50 Ω resistor for circuit balancing, which is equal to the output impedance of the ML-EDSM circuit. In Fig. 2 , for the 3-level (0 V, 0.25 V, and 0.5 V) PWM input signal, to achieve an accurate 3-state envelope level in the up-mixer output waveform, the magnitude from the first level (0 V) to the second level (0.25 V), A , and the magnitude from the second level (0.25 V) to the third level (0.5 V), B , should be equal. To ensure that the ratio A / B is equal to one, the relation between the gate dc-bias level of the up-mixer ( M a , M b , M c , and M d ), V LO,dc , and the magnitude of the LO amplitude, V LO,pp , has been evaluated, as shown in Fig. 3 . Figure 3 shows the ratio A / B becomes one at V LO,dc = 0.66 V for LO amplitudes from 500 mV PP to 1 V PP , which can be practically achieved from the proposed wideband buffer. Even if V LO,pp is smaller than 500 mV PP , the ratio A / B = 1 can be maintained by digitally controlling V LO,dc . Finally, by adopting V LO,dc = 0.66 V, the ratio A / B = 1 can be guaranteed in the proposed up-conversion mixer.
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Relationship between LO bias level and LO amplitude.
In Fig. 2 , to achieve a single-ended 3-level EDSM RF signal, the differential output signal of the up-conversion mixer should be extracted by a D2S. The D2S can be located at the output of the up-conversion mixer or at the output of the DA. If the D2S is located at the output of the DA, then large signals amplified by the DA cannot be accommodated in the D2S. As a result, the 3-state envelope level can be seriously distorted at the D2S output. In addition, the DA should be designed as a differential topology, which consumes twice the dc power consumption and die area compared to the single-ended DA. Accordingly, the proposed D2S directly follows the up-conversion mixer in this work, as shown in Fig. 2 . The proposed D2S is made up of a combination of a common-drain (CD) amplifier, M 2 , and a common-source (CS) amplifier, M 1 , where M 1 and M 2 are realized using thick-oxide MOSFETs to permit a high voltage swing under a 2.5 V supply voltage. To make the 3-level EDSM RF signal fully symmetric up and down at the D2S output, the voltage gains of the two amplifiers are made almost the same by optimizing the size of their input transistors, M 1 ( W / L = 60 μm/0.35 μm) and M 2 ( W / L = 50 μm/0.35 μm). The proposed DA is a single-ended Class AB cascode CS amplifier ( M 3 and M 4 ) with a 1 dB output compression point (OP 1dB ) of +10 dBm. It can provide an average output power level of +0 dBm due to a peak-to-average power ratio (PAPR) of 10 dB. In Fig. 2 , the input transistor M 3 is Class AB biased for high efficiency, and the cascode transistor M 4 is realized in thick-gate NMOS for high output voltage swing. To prevent any phase-transition distortion or spectral regrowth, the DA has been designed to achieve both enough bandwidth and high linearity [9] . Our simulation results show that the required bandwidth is more than four times the ML-EDSM’s sampling frequency of 522.24 MHz.
Previously reported wideband amplifiers are dominated by three different topologies: shunt-feedback, shunt-peaking, and distributed amplifiers. The shunt-feedback amplifier [10] provides respectable wideband matching and flat gain but suffers from large dc power dissipation. The shunt-peaking amplifiers [11] [12] can also provide flat gain over a wide frequency band, but they cannot provide high output power due to a voltage drop across a resistive load. The distributed amplifiers [13] [14] tend to consume a large amount of dc current due to the distribution of multiple amplifying stages. In Fig. 2 , to achieve broadband gain characteristics and 50 Ω output matching to an external PA, the proposed DA adopts a second-order band-pass filter (BPF) as its load, which consists of L P , C P , L S , and C S . Here, L S and L p are realized by a bonding wire inductance and on-chip spiral inductor, respectively, and C S is an off-chip capacitor. The parasitic capacitance by the output pad is included in C P . For clarity, Fig. 4(a) shows the small-signal equivalent circuit for the output part of the overall DA, where − g m3 v in and R D represent the small-signal output current and resistive load of the DA, respectively, and R L = 50 Ω represents an input impedance of the following PA. As Fig. 4(a) demonstrates, the small-signal equivalent circuit for the output of the DA is exactly the same as the second-order BPF topology. Figure 4(b) shows the theoretical values of the BPF parameters and simulated frequency-response curves according to various values of R D for a targeted −3 dB bandwidth of 2.5 GHz (that is, 1.5 GHz to 4 GHz) for R L = 50 Ω. In Fig. 4(b) , when R D = 50 Ω, the BPF shows the best wideband gain curve ( S 21 ) and broadband 50 Ω matching ( S 22 ). In addition, since the quality factor Q of the BPF is small due to R D = 50 Ω, the output voltage swing at the drain of M 4 is small, which leads to improvement of the DA linearity. However, to achieve an OP 1dB of +10 dBm, the transconductance g m3 of the input transistor M 3 should be increased due to the small value of R D , which leads to high dc power consumption. Thus, considering dc power consumption, wideband characteristics, and linearity, the R D of 100 Ω has been chosen for the proposed DA. As shown in Fig. 4(b) , though R D = 100 Ω is not matched to R L = 50 Ω, S 21 still shows a −3 dB bandwidth from 1.5 GHz to 4 GHz and S 22 is less than −10 dB over the same frequency range. In addition, because the output voltage swing at the DA is not very wide due to R D = 100 Ω, the cascode transistor M 4 can operate in the saturation region while the proposed DA delivers its maximum output power of +10 dBm. The proposed DA, under maximum-power operation, draws a dc current of 13.5 mA from a 2.5 V supply voltage. Finally, the proposed DA with the second-order BPF can achieve high output power, flat gain, and broadband output matching, while consuming moderate dc power consumption.
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Characterization of DA: (a) small-signal equivalent circuit and (b) theoretical values of the BPF parameters and simulated curves according to the various values of RD (50 Ω, 75 Ω, 100 Ω, 200 Ω, and 500 Ω). Here, RD represents the resistive load of DA.
Although the proposed BPF can provide a wide bandwidth at the DA output, a gain reduction may occur at a high frequency range due to unexpected parasitic capacitances. To mitigate this problem, a series-peaking on-chip spiral inductor, L G , is used to tune out the gate-source capacitance, C gs , of M 3 at 3.5 GHz to give more amplification to the input signal. Finally, the proposed DA provides an overall bandwidth of 3 GHz centered at the 2.6 GHz carrier frequency.
III. Measurement Results
The proposed 3-level EDSM RF signal generator has been implemented in 0.13 μm CMOS technology, as shown in Fig. 5 . The I-Q phase modulator and wideband buffer consume 6.5 mA from a 1.2 V supply, and the other circuits (up-conversion mixer, D2S, and DA) consume 20.5 mA from a 2.5 V supply.
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Chip photograph (core area is 2 mm2).
The fabricated chips were packaged and then mounted on a test board. To apply a 3G LTE input signal to the test board, its phase and envelope signals were separately generated; the baseband I-Q phase signal is provided from a vector signal generator and the 3-level EDSM signal from an ML-EDSM chip, which is not described in this paper but which is also implemented in 0.13 μm CMOS technology. The 2.6 GHz quadrature LO tones for the I-Q phase modulator are provided from an internal divide-by-two circuit by using an external 5.2 GHz signal.
Figures 6 , 7 , and 8 show the measured results of the fabricated chip having a 3G LTE input signal with a channel bandwidth of 10 MHz/20 MHz. The sampling rate of the ML-EDSM is 522.24 MHz. Figure 6 shows the measured time-domain waveforms of the 3-level EDSM RF signal at the DA output. Due to sufficient bandwidth for all the signal paths and an optimized LO biasing level for the up-conversion mixer, the output waveforms have a sharp phase transition in each envelope level and horizontally symmetrical 3-level envelope variation. Figure 7 gives the measured output power spectrums. In Fig. 7(a) , an average output power of −1 dBm (cable loss of 2 dB is calibrated) and an adjacent channel leakage ratio (ACLR) of more than 40 dBc at a 10 MHz offset have been measured for the input 3G LTE signal with a channel bandwidth of 10 MHz. Figure 7(b) shows a measured 20 MHz channel power of −1.5 dBm and ACLR of more than 29.6 dBc at a 20 MHz offset. The ACLR can be further improved by increasing the ML-EDSM’s sampling frequency. The measured EVM of 3.89% for both two-channel bandwidths is shown in Fig. 8 . The measured results with the 3G LTE signals are summarized in Table 1 .
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Probed 3L-EDSM RF signal waveforms for (a) channel bandwidth of 10 MHz and (b) channel bandwidth of 20 MHz.
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Output power spectrums for (a) channel bandwidth of 10 MHz and (b) channel bandwidth of 20 MHz.
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Measured EVM constellation for (a) channel bandwidth of 10 MHz (EVM = 3.89%) and (b) channel bandwidth of 20 MHz (EVM = 3.89%).
Performance summary.
RF carrier frequency 2.6 GHz
Chip core area 2 mm2
Technology 0.13 μm CMOS
Total dc power consumption 60 mW
Supply voltage 1.2 V/2.5 V
3G LTE channel-BW 10 MHz 20 MHz
Channel power (dBm) −1* −1.5*
ACLR (dBc) Lower band −40.4 −29.6
Upper band −40.7 −30.5
EVM of 64 QAM (%) 3.89 3.89
*Cable loss of 2 dB has been calibrated.
IV. Conclusion
This paper has presented a 3-level envelope delta-sigma modulation (3L-EDSM) RF signal generator, which is implemented in 0.13μm CMOS technology. The measurement results demonstrate that the proposed 3-level EDSM RF signal generator can be adopted for the new PA architecture described in [5] . Finally, the proposed PA architecture with the 3-level EDSM RF signal generator can serve as an alternative for the implementation of high-efficiency transmitters, which are required in high-data-rate wireless systems, such as LTE/LTE-Advanced picocell base station and user equipment, WiMAX, wireless local area network, and so on.
This work was supported by National Research Foundation of Korea Grant funded by the Korean Government (2009-0065311) and also supported by the ICT R&D Program of MSIP/IITP (14-000-04-001, Development of 5G Mobile Communication Technologies for Hyper-connected Smart Services).
BIO
syh3039@hanmail.net
Yongho Seo received his BS and MS degrees in electronics engineering from Dong-A University, Busan, Rep. of Korea, in 2009 and 2011, respectively. He is currently working toward his PhD degree at Radio Frequency Integrated Circuit laboratory, Dong-A University. His main research interests are wideband/multiband CMOS RF transceiver design for wireless local area networks and cellular applications.
ykcho@etri.re.kr
Youngkyun Cho received his BS degree from Ajou University, Suwon, Rep. of Korea, in 2001 and his MS degree from Pohang University of Science and Technology, Pohang, Rep. of Korea, in 2003, both in electrical and electronics engineering. He is currently with the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea, as a senior researcher. His research interests are novel devices; mixed signal circuits; Nyquist; and oversampling rate ADCs and transceivers. He was the recipient of the best paper award at the IEEE Nanotechnology Materials and Devices Conference in 2006 and was twice awarded the prize at the National Semiconductor Design Contest in 2009 and 2014.
sgchoi@cbnu.ac.kr
Seong Gon Choi received his BS degree in electrical engineering from Kyungpook National University, Daegu, Rep. of Korea, in 1990 and his MS and PhD degrees from the Korea Advanced Institute of Science and Technology, Daejeon, Rep. of Korea, in 1999 and 2004, respectively. Currently, he is an associate professor at the College of Electrical & Computer Engineering, Chungbuk National University, Cheongju, Rep. of Korea. His main research interests are mobile communications; green networks; smart grids (future power grid); and high-speed network architectures and protocols.
Corresponding Author  cwkim@dau.ac.kr
Changwan Kim received his BS degree in electrical engineering from the School of Electrical Engineering and Computer Science, Kyungpook National University, Daegu, Rep. of Korea, in 1997 and his MS and PhD degrees in electronic engineering from the Information and Communications University, Daejeon, Rep. of Korea, in 2003 and 2006, respectively. From 2006 to 2007, he worked for the Electronics and Telecommunications Research Institute, Daejeon, Rep. of Korea. Since 2007, he has been with the Department of Electronic Engineering, Dong-A University, Busan, Rep. of Korea, where he is now an associate professor. His main research interests are wideband/multiband CMOS RF transceiver design and system-level integration of transceivers.
References
Wang Y. 2003 “An Improved Kahn Transmitter Architecture Based on Delta-Sigma Modulation,” IEEE MTT-S Int. Microw. Symp. Dig. Philadelphia, PA, USA June 8–13 2 1327 - 1330    DOI : 10.1109/MWSYM.2003.1212615
Nielsen M. , Larsen T. 2007 “A Transmitter Architecture Based on Delta-Sigma Modulation and Switch-Mode Power Amplification,” IEEE Trans. Circuits Syst. II, Exp. Briefs 54 (8) 735 - 739    DOI : 10.1109/TCSII.2007.899457
Berland C. 2006 “A Transmitter Architecture for Nonconstant Envelope Modulation,” IEEE Trans. Circuits Syst. II, Exp. Briefs 53 (1) 13 - 17    DOI : 10.1109/TCSII.2005.854594
Choi J. 2007 “A Delta-Sigma-Digitized Polar RF Transmitter,” IEEE Trans. Microw. Theory Techn. 55 (12) 2679 - 2690    DOI : 10.1109/TMTT.2007.907137
Kim J.H. “60% High-Efficient 3G LTE Power Amplifier with Three-Level Delta Sigma Modulation Assisted by Dual Supply Injection,” IEEE MTT-S Int. Microw. Symp. Dig. Baltimore, MD, USA June 5–10, 2011 1 - 4
Sowlati T. “Single-Chip Multiband WCDMA/HSDPA/HSUPA/EGPRS Transceiver with Diversity Receiver and 3G Digital RF Interface without SAW Filters in Transmitter 13G Receiver Paths,” ISSCC Dig. Tech. Papers San Francisco, CA, USA Feb. 8–12, 2009 116 - 117
He X. , Sinderen J.V. “A 45 nm Low-Power SAW-less WCDMA Transmit Modulator Using Direct Quadrature Voltage Modulation,” IEEE Int. Solid-State Circuits Conf. San Francisco, CA, USA Feb. 8–12, 2009 120 - 121    DOI : 10.1109/ISSCC.2009.4977337
Tillman F. , Troedsson N. , Sjland H. “A 1.2 Volt 1.8 GHz CMOS Quadrature Front-End,” Symp. VLSI Circuits Dig. Techn. Papers June 17–19, 2004 362 - 365    DOI : 10.1109/VLSIC.2004.1346616
Razavi B. 1998 RF Microelectronics Prentice Hall PTR New Jersey, USA 91 - 93
Kobayashi K.W. 2012 “An 8 W 250 MHz to 3 GHz Decade- Bandwidth Low-Noise GaN MMIC Feedback Amplifier with > +51 dBm OIP3,” IEEE J. Solid-State Circuits 47 (10) 2316 - 2326    DOI : 10.1109/JSSC.2012.2204929
Bevilacqua A. , Niknejad A.M. “An Ultrawideband CMOS LNA for 3.1 to 10.6 GHz Wireless Receiver,” IEEE Int. Solid-State Circuits Conf. Dig. Techn. Papers San Francisco, CA, USA Feb. 15–19, 2004 382 - 383
Sapawi R. 2012 “Low Group Delay 3.1–10.6 GHz CMOS Power Amplifier for UWB Applications,” IEEE Microw. Wireless Compon. Lett. 22 (1) 41 - 43    DOI : 10.1109/LMWC.2011.2176475
Hsiao C.-Y. , Su T.-Y. , Hsu S.S.H. 2013 “CMOS Distributed Amplifiers Using Gate-Drain Transformer Feedback Technique,” IEEE Trans. Microw. Theory Techn. 61 (8) 2901 - 2910    DOI : 10.1109/TMTT.2013.2271614
Moez K. , Elmasry M. “A 10 dB 44 GHz Loss-Compensated CMOS Distributed Amplifier,” IEEE Int. Solid-State Circuits Conf. Dig. Techn. Papers San Francisco, CA, USA Feb. 11–15, 2007 548 - 549