Quantitative Evaluation Method for Etch Sidewall Profile of Through-Silicon Vias (TSVs)
Quantitative Evaluation Method for Etch Sidewall Profile of Through-Silicon Vias (TSVs)
ETRI Journal. 2014. Jun, 36(4): 617-624
Copyright © 2014, Electronics and Telecommunications Research Institute(ETRI)
  • Received : September 04, 2013
  • Accepted : January 02, 2014
  • Published : June 01, 2014
Export by style
Cited by
About the Authors
Seung-Nam Son
Sang Jeen Hong

Through-silicon via (TSV) technology provides much of the benefits seen in advanced packaging, such as threedimensional integrated circuits and 3D packaging, with shorter interconnection paths for homo- and heterogeneous device integration. In TSV, a destructive cross-sectional analysis of an image from a scanning electron microscope is the most frequently used method for quality control purposes. We propose a quantitative evaluation method for TSV etch profiles whereby we consider sidewall angle, curvature profile, undercut, and scallop. A weighted sum of the four evaluated parameters, nominally total score (TS), is suggested for the numerical evaluation of an individual TSV profile. Uniformity, defined by the ratio of the standard deviation and average of the parameters that comprise TS, is suggested for the evaluation of wafer-to-wafer variation in volume manufacturing.
I. Introduction
With the advent of nanoscale integrated circuits, plasmaassisted etching became a more important technology for the microelectronics manufacturing industry. Advanced packaging technologies, such as three-dimentional integrated circuits (3D-ICs) and 3D packaging, are continuously growing to meet such high specification and quality demands. 3D-ICs consist of multiple layers of active transistors vertically stacked in a single chip; 3D packaging can help reduce die-to-die spacing in a package by stacking such chips.
The benefits of such advanced packaging technologies are smaller footprint, heterogeneous integration, shorter interconnection, and low power consumption in their interconnection; however, the technologies still hold technical challenges in design, manufacturing yield, testing procedures, and issues of reliability [1] . One of the common issues in 3D chip packaging integration is vertical interconnection using through-silicon vias (TSVs). TSV provides smaller footprint, increased chip-to-chip or layer-to-layer interconnection density, reduced signal-delivery delay with shorter interconnection, and heterogeneous integration [1] [2] . Traditional plasma etching may suffer from high aspect ratios arising from the etching process; however, deep reactive-ion etching (DRIE), using either the Bosch process or the non- Bosch process, can alleviate such a concern in TSV etching [3] . The Bosch process is performed through the alternation of two phases: the deposition of a passivation layer and etching of vias. This process is also known as gas-chopping etching or time-multiplexed etching. The non-Bosch process is referred to as the conventional etch process. Recently, non- Bosch TSV etching with magnetically enhanced reactive-ion etching was successfully applied to 300 mm 3D logic integration [4] .
Both sidewall profile and within-wafer uniformity (WWU) are used in the Bosch and non-Bosch silicon etching processes. For process development and quality control (QC), it is crucial to evaluate the sidewall profile and WWU via patterned results on wafer. Analysis of scanning electron microscope (SEM) images is widely employed in manufacturing; however, this is too dependent upon an evaluator’s background experience. To establish a more objective evaluation criterion in TSV etching, a group of researchers from Samsung Electronics Company suggested a matrix scoring method for the development of new plasma etch equipment by consulting experts and weighting factors-of-interest such as profile, uniformity, and contamination [5] . The matrix scoring method is an objective and quantitative strategy for optimized recipe setup in the early stages of process development and tool qualification; however, the cost of evaluating etch results using the matrix scoring method may increase manufacturing costs. Considering QC, it is more desirable to establish a more practical quantitative method to intuitively understand the etch result. It is not an overstatement to say that such an evaluation strategy should be developed for operators in the QC sector for successful manufacturing. In addition, TSV images may appear bowed in an SEM image when the sample cut of a TSV is not exactly perpendicular. Unlike with line and space patterns, in the case of a cylindrical via it cannot be simply assumed that the sample cut will be one-hundred-percent accurate.
This paper suggests an improved method for etch-profile evaluation in TSVs. We first introduce a method to check whether a sample SEM image is properly prepared. We also introduce another method to correct any imperfections found in sample SEM images; herein it will be referred to as compensation method (CM). We also define the following four factors of interest:
  • Angle match (AM) — this shows how the tapered sidewall angle meets the perpendicular cut.
  • Degree of undercut (DoU) — this shows how much undercut etching took place underneath the etch mask.
  • Degree of scallop (DoS) — this shows how the scallop is developed in the Bosch process.
  • Curvature profile (CP) — the amount of sidewall bowing that occurs.
Our paper is organized as follows. The geometrical definition and mathematical derivations for TSV analysis are presented in section II, and the verification and validation of the suggested methodology is presented in section III. This is followed by the conclusion in section IV. Additionally, symbols used in the mathematical derivation are presented in the Appendix.
II. Characterization of TSV Etch Profile
- 1. CM
Although non-destructive testing of a TSV array structure by 3D X-ray computed tomography has been reported [6] , the destructive method is still the most commonly used in the characterization and failure analysis of TSV by way of the techniques of focused ion beam (FIB) and SEM. During sample preparation for cross-sectional images, TSVs require more attention than that of line and space patterns because of their cylindrical shape. When a sample cut does not pass through the center of a via, a distorted geometric appearance may occur. When a sample cut is slanted away from a wafer surface, one may observe a slightly bowed etch profile in the sidewall even though no actual bowing resides in the sample. We herein define such a misleading as illusion bowing effect (IBE) — the bowed appearance of the etch profile due to the angled cut in a cylindrically shaped TSV. The IBE is illustrated in Fig. 1 . IBE induced from θ 1 in Fig. 1 (a) and θ 2 in Fig. 1 (b) can be corrected by θ comp , which is derived as follows. The required variables and geometric measurements are presented in Fig. 2 .
PPT Slide
Lager Image
Illustration of misled TSV analysis; (a) θ1 occurs due to the difference in the diameter of front and back sides and (b) θ2 occurs due to a slanted cut.
PPT Slide
Lager Image
Points of measurement used for numerical evaluation.
The amount of etch bias along a cylindrical TSV, as indicated by the angle θ 1 in Fig. 1 , can be calculated as follows:
θ 1 = tan 1 Depth 2( R b   R t ) ,  where  R b = D b 2   and   R t = D t 2  .
When a sample cut is not taken perpendicular to the wafer surface, the measured diameters of the top and bottom of the TSV will be misleading. We define Kt and Kb to help us find the observed angle θ 2 from a sample that was not cut perpendicular to a wafer surface as follows:
K t = R t ± R t 2   ( w t 2 ) 2 ,   when   R t < K t   or   R t > K t
K b =  R b ± R b 2   ( w b 2 ) 2 ,   when   R b < K b   or   R t > K t .
Now, we define
θ 2  =  tan −1 Depth ( R t −  R b )−( K t − K b ) .
Once we have found θ 1 and θ 2 , the bases of the triangles featured in Figs. 1(a) and 1(b) — that is, b 1 ( x ) and b 2 ( x ), respectively — are calculated and used in the modification factor Δ d ( x ). This modification factor is defined as the difference between the measured diameter of the via at a location x and the diameter of the via when it is perpendicularly cut, as shown in Fig. 1(b) . Depending on x , the radius r ( x ) is computed as follows:
r(x)= (2 R t + b 1 (x)) 2 ,
b 1 (x)= w(x) tan( θ 1 ) ,   w b < w(x)< w t ,  and    b 2 (x)= w(x) tan( θ 2 ) .
Δd(x)=r(x) K t + b 2 (x)+ b 1 (x) 2 .
By examining the cross-sectional via width at x , w ( x ) in Fig. 1(b) , we can validate whether the TSV under evaluation is actually bowed or whether it just appears to be so. The compensated radius r comp ( x ) is calculated as follows:
r comp (x)≡   ( w(x) 2 ) 2 +Δd (x) 2 ,
Based on the measured values w ( t ) and w ( b ), shown in Appendix Table A1, θ 4 is calculated, and α , the difference between θ 3 and θ 4 , is defined to indicate the lopsidedness of the etched via profile.
θ 4  =90° tan 1 ( w( t ) w( b ) 2×Depth ), α =  | θ 3   θ 4 |.
To eliminate the influence of IBE from the SEM image under investigation, Δ d ( b ) and Δ d ( t ) are set to be equal to eliminate the influence of θ 2 .
Δ d ( b ) ≡ Δ d ( t ) = Rt − Kt ,
w (b) comp =2× R b 2 Δd (b) 2 .
Thus, the compensated angle to eliminate IBE, θ comp , can be found as follows:
θ comp =( 90° tan 1 ( w(t)w (b) comp 2×Depth ) )+α.
- 2. Parameters for Evaluation
AM indicates how closely the measured TSV’s vertical etch profile matches with the designed or expected etch profile. The sidewall angle is an important geometric parameter in TSV etching because it may affect the degree of agglomeration in the processes of linear dielectric and barrier metal deposition for copper interconnection [7] . It is reported that the angle of via is related with electrical characteristics in frequency response and that a specific angle is required for each different purpose of a device’s usage [8] . To verify whether the etch process result satisfies the required or designed angle within Errϕ , which can be interpreted by process/design engineers as error tolerance, the allowed process margin at the bottom side of a TSV is defined as
β( Err )= tan 1 ( Err Depth ),
γ =k( α  β ),
-∞ ≦ k ≦ 4.605 ∀ designs k ,
V=100 e γ ,
=1 |ϕ θ comp | Er r ϕ ,
AM  =  V×.
Using the parameter α in (2) and the allowed process margin β , the vertical etch profile of TSVs is found by Errϕ . The proportional constant k is determined by process/design engineers for initial setup. For instance, in a Cu filling process, a TSV etch profile is desired to be tapered to efficiently fill-in vias with Cu.
Undercutting tge can influence the rest of the etching process. As shown in Fig. 2 , the depth of undercut ( Mu ) is usually less than or equal to the depth of scallop ( Md ) in a successful Bosch process. We herein define undercut as the ratio of the depth of undercut ( Mu ) and the depth of scallop ( Md ). In addition, we note that the DoU is developed by employing the engineering constant k .
u =   M u M d t,
DoU(u)=100 e (u×k) .
The aforementioned Bosch process includes multiple cycles of isotropic silicon etch and via sidewall passivation deposition to prevent sidewall etching in etch cycles, and the formation of scallop is inevitable in this cyclic process. Smaller sidewall scallop helps the Cu filling process by electrochemical plating [9] . The scallop factor, s , is defined by the ratio of the depth of the scallop ( Md ) and the height of the scallop ( Mh ), and DoS is calculated by the following:
s =   M d M h ,
DoS(s)=100 e (s×k) .
We previously defined IBE as being caused by a sample cut that is taken in such a way so as not to be perpendicular to a cylindrical TSV; however, the bowed etch profile needs to be cross-checked to verify that it is not induced by the localization of reactive ions or radicals in plasma during the deep silicon via etching. To alleviate this concern, we defined the previously mentioned parameter CP as follows:
μ=90° tan 1 ( a x ),   where   a= R t r comp (x),
σ=90° tan 1 ( b Dephtx ),  where  b= r comp (x) R b ,
CP(π)=100 e (π) ,  where  π=  |μσ|.
The amount of existing curvature in a TSV is determined by the difference between μ and σ , where μ shows the profile angle formed between the top of the via and the TSV and σ shows that of the angle between the bottom of the via and the TSV. When μ and σ are the same, there is no bowing evident in the vertical profile of a TSV.
Combining the four evaluation parameters, AM, DoU, DoS, and CP, a simplified performance index (PI) is suggested in the form of a weighted sum of the four parameters. Depending on the type of application of via etching, the weights of the required TSV geometry can be determined by an engineer; however, in all cases their sum is to always equal one.
PI  =  AM× g 1 +DoU× g 2 +DoS× g 3 +CP× g 4 , where    i g i =1.
Considering a 300 mm manufacturing environment, the global metrology of an entire wafer and the local metrology of a TSV are important. Conventional wafer metrology of wafer uniformity relies on wafer geometry maps constructed from the measurements of multiple locations. In this paper, we also propose WWU for QC purposes to address both wafer-to-wafer and lot-to-lot control. The suggested PI and WWU will contribute to establishing the statistical process control required for manufacturing effectiveness.
WWU  =   Stde v PI Av g PI ×100.
III. Validation and Verification
Verification of the suggested method for the TSV profile evaluation is performed on possible cases of etched profiles. Various shapes of TSVs with 1:5 aspect ratios are considered, as shown in Fig. 3 , and their reference measurements according to Fig. 2 are listed in Table 1 . We assume a situation where bowed TSVs are observed from slanted sample cuts, although there are no actually bowed via profiles. Crosssectional SEM images for TSVs are shown in two ways depending on the location of a sample cut: scenario 1 is where the size of the removed portion is less than half of the via’s initial size, and scenario 2 is where the size of the remaining portion (after a cut has been made) is less than half of the via’s initial size. In scenario 1, the cross-sectional views show smaller geometrical characteristics than in reality; in scenario 2, the opposite is depicted. Both cases of misleading can be compensated by employing the suggested CM; the results of which are shown in Tables 2 and 3 , respectively.
PPT Slide
Lager Image
Various etched TSV models for the verification of CM.
It is possible to recognize whether real bowing in a TSV has occurred by examining the difference between r ( x ) and r comp ( x ). Table 2 shows that almost no bowing appears in scenario 1. The corrected vertical angle of the TSV profile, θ comp , in scenario 2, is presented in Table 3 . It is shown that the CM can assess IBE depending on θ 1 , and θ 2 , and real bowing to improve reliability in the measurement of a cross-sectional image. It is confirmed that the amount of real bowing could be evaluated through the CP parameter.
Geometric measurements of etched TSV models shown inFig. 3.
Parameters A B C D E
Depth 5 5 5 5 5
θ3 90 87.93 92.12 90 90
wt 0.87 0.87 0.51 0.51 0.87
wx 0.87 0.70 0.70 0.87 0.51
wb 0.87 0.51 0.87 0.51 0.87
x 2.50 2.50 2.50 2.50 2.50
Dt 1 1 0.70 0.70 1
Db 1 0.70 1 0.70 1
Compensation results of scenario 1 withθ2= 90°,Err= 10, andErrф= 4.
Parameters A B C D E
Dt 1 1 0.70 0.70 1
Db 1 0.70 1 0.70 1
r(x) 0.50 0.43 0.43 0.35 0.50
rcomp 0.50 0.43 0.43 0.50 0.35
Measured rcomp 0.50 0.43 0.42 0.50 0.35
w(b)comp 0.87 0.50 0.88 0.51 0.87
θcomp 90 87.87 92.16 90 90
Compensation results of scenario 2 withθ2= 90°,Err= 10, andErrф= 4.
Parameters A B C D E
θ3 89.06 86.87 90.74 88.58 89.18
w(b)comp 0.98 0.67 0.99 0.68 0.98
Measured w(b)comp 0.98 0.67 0.98 0.67 0.98
θcomp 90.08 88.25 91.87 90.01 90.04
Measured θcomp 90 88.29 91.80 90 90
Once we validated the usefulness of the suggested method, the verification was carried out with both Bosch and non- Bosch processed TSV cross-sectional sample images, which are shown in Figs. 4 and 5 , respectively. Prior to the verification, the sidewall angle of the Bosch process is set to be 90° (in the case of the non-Bosch process, it is set to be 87°), under the assumption of θ 2 = 0° .
PPT Slide
Lager Image
TSV SEM images from Bosch process: (a) center of the wafer and (b) edge of the wafer.
PPT Slide
Lager Image
TSV SEM images of non-Bosch process: (a) center of the wafer and (b) edge of the wafer.
In the Bosch process, shown in Fig. 4(a) , the formation of the scallop on the sidewall is mostly well distributed and the evaluation scores related to the scallop, DoS, were satisfactory. It seems that no significant curvature was observed with high CP score in Table 4 . However, TSVs located at the edge area of the wafer showed undercutting on the right-hand side; thus, lowering their AM evaluation scores. As shown in Table 4 , overall, the TSVs at the center of the wafer were satisfactory, but TSVs at the edge of the wafer showed less than satisfactory process results. Continuing now to the verification of the non-Bosch TSV examples shown in Fig. 5 , it is apparent that no significant evidence of a sidewall CP exists except at the top corners of TSVs. In this verification, the desired sidewall angle was set at 87°, and the corrected angles were 86.38° and 70.18° at the center and at the edge of the wafer, respectively. Based on the desired parameter settings for the TSV process, the overall result is presented in Table 5 .
Scores of Bosch process profile at the center of the wafer and the edge of the wafer.
Parameters Scores at center Scores at edge
AM 66.82 14.56
DoU 96.84 90
DoS 97.29 97.22
CP 98.77 97.64
PI 85.45 62.84
(θ2 = 0°, ϕ = 90°, Errϕ = 2°, Err = 10 μm, g = 4:2:1:3)
Scores of Bosch process profile at the center of the wafer and the edge of the wafer.
Parameters Scores at center Scores at edge
AM 86.38 70.18
CP 0 0
PI 51.83 42.18
(θ2 = 0°, ϕ = 87°, Errϕ = 2°, Err = 10 μm, g = 6:4)
Satisfactory verification and validation results were achieved. Time-consuming geometry metrology can be simplified through the use of a graphic user interface (GUI) for easier calculations of the TSV etch process evaluation, as shown in Fig. 6 . Users are asked to simply enter a few measurements through a series of option menus, after which the calculated outputs are then displayed and recorded in the data base. Adding features of pattern recognition for automated TSV image loading and image processing for convenient metrology can be an additional benefit for higher throughput in metrology.
PPT Slide
Lager Image
GUI of the TSV profile evaluation software system (university in-house built prototype).
IV. Conclusion
A quantitative evaluation method for TSV etch profiles, including sidewall angle, scallop, and undercut curvature profile, is presented in this paper. As no notable method is currently known for the evaluation of TSV etch profiles, other than the method of matrix scoring by Samsung, the suggested technique allows TSV etch engineers to make more quantitative-based decisions based on an assessment of a TSV’s attributes. IBE was defined so as to avoid any potential misleading from a slated cut of a TSV sample, and we suggested how to compensate IBE in geometric calculations. Four attributes of TSVs — angle match, degree of undercut, degree of scallop, and curvature profile — are suggested to evaluate an etched TSV profile. Validation of the suggested method was performed under two hypothetical scenarios; the suggested method also being verified with the cross-sectional SEM image taken from two cases of the TSV etching process. Finally, a GUI is demonstrated for the potential consideration of its practical usage in a manufacturing environment.
Definition of CM parameters.
Variable Definition
x Depth at measured point
α Difference between calculate angle and measured angle
b1(x) Base of the triangular view from θ1
b2(x) Base of the triangular view from θ2
Dt Diameter at top side
Db Diameter at bottom side
Δd(x) Variation length depends on θ1 and θ2
Δdb Difference between radius and length of cut section at bottom side
Δdt Difference between radius and length of cut section at top side
Kt Length of cut section at top side
Kb Length of cut section at bottom side
k(x) Length of cut section at x
Rt Radius at top side
Rb Radius at bottom side
r(x) Radius at x
rcomp(x) Compensated radius based on w(x)
θ1 Calculated angle based on difference in diameter between top and bottom side
θ2 Calculated angle based on difference in cut section between top and bottom side
θ3 Measured angle
θ4 Calculated angle based on w(t) and w(b)
wt Width of cross section at top side
wx Width of cross section at x
wb Width of cross section at bottom
w(b)comp Compensated width at bottom to get away IBE
θcomp Compensated angle
Definition of AM parameters.
Variable Definition
β(Err) Convert length of error tolerance to angle
Difference between measured angle and designed angle
Err Length of error tolerance by engineer
Errϕ Angle of error tolerance by engineer
γ Ratio of theoretical to error tolerance
k Constant value
ϕ Designed angle by engineer
V Degree of vertical
AM Score of AM parameter
Definition of DoU parameters.
Variable Definition
Md Scallop depth
Mu Under cut depth
u Ratio of scallop depth to under cut
DoU(u) Score of DoU parameter
Definition of DoS parameters.
Variable Definition
Mh Scallop height
s Ratio of scallop depth to scallop height
DoS(s) Score of DoS parameter
Definition of CP parameters.
Variable Definition
a Difference radius between Rt and rcomp(x)
b Difference radius between rcomp(x) and Rb
μ Calculated profile angle between top and x
π Difference between μ and σ
σ Calculated profile angle between x and bottom
CP(π) Score of CP parameter
Definition of uniformity parameters.
Variable Definition
gi Weight constant of each parameter
PI Performance index of AM, DoU, DoS, and CP parameters depending on weight
AvgPI Average of PI
StdevPI Standard deviation of PI at every measured position of wafer
Seung-Nam Son received his BS and MS degrees in electronic engineering from Myongji University, Seoul, Rep. of Korea, in 2010 and 2012 and is currently employed as a package development engineer at Amkor Korea, Seoul, Rep. of Korea. Prior to joining Amkor Korea, he served for a leadership at the Microelectronics Manufacturing Technology Lab, Myoungji University, Seoul, Rep of Korea. He is currently working on high volume manufacturing in TSV technology.
Sang Jeen Hong received his BS in electrical computer engineering from Myongji University, Seoul, Rep. of Korea, in 1992 and his MS and PhD in electrical computer engineering from the Georgia Institute of Technology, Atlanta, USA, in 2001 and 2003, respectively. He is currently a professor in the Department of Electronic Engineering at Myongji University, where he serves as a director of the Semiconductor Process Diagnosis Research Center. His research interests are in situ sensor–based advanced process/equipment and tool data-driven fault detection and classification, including process modeling and optimization in high-volume semiconductor manufacturing. He holds 15 domestic and international patents and more than 60 archival journals related to semiconductor manufacturing. He was appointed as a member of the Expert Consulting Group with Samsung Display in the area of AEC/APC. He was awarded the ECE fellowship from the Georgia Institute of Technology, Atlanta, USA, in 2011 and the JSPS fellowship in 2004.
“3D TSV Processes and its Assembly/Packaging Technology,” IEEE Int. Conf. Syst. Integr. San Francisco, CA, USA Sept. 28-30, 2009 1 - 5    DOI : 10.1109/3DIC.2009.5306535
Nowak E. “Intrinsic Fluctuations in Vertical NAND Flash Memories,” Symp. VLSI Technol. Honolulu, HI, USA June 12-14, 2012 21 - 22    DOI : 10.1109/VLSIT.2012.6242441
Rao V.S. “TSV Interposer Fabrication for 3D IC Packaging,” Electron. Packag. Technol. Conf. Singapore Dec. 9-11, 2009 431 - 437    DOI : 10.1109/EPTC.2009.5416509
Teh W.H. “Magnetically-Enhanced Capacitively-Coupled Plasma Etching for 300 mm Wafer-Scale Fabrication of Cu Through-Silicon-Vias for 3D Logic Integration,” IEEE Int. Interconnect Technol. Conf. Sapporo, Japan June 1-3, 2009 53 - 55    DOI : 10.1109/IITC.2009.5090338
Han K.P. 2010 “Matrix Scoring Method for the Evaluation of TSV Development Using a Magnetically Enhanced Plasma Etcher,” ECS Meeting Las Vegas, NV, USA
Sekhar V.N. “Non-destructive Testing of a High Dense Small Dimension Through Silicon Via (TSV) Array Structures by Using 3D X-ray Computed Tomography Method (CT scan),” Electron. Packag. Technol. Conf. Singapore Dec. 8-10, 2010 462 - 466    DOI : 10.1109/EPTC.2010.5702683
Bär E. , Lorenz J. , Ryssel H. 2002 “Simulation of the Influence of Via Sidewall Tapering on Step Coverage of Sputter-Deposited Barrier Layers,” Microelectron. Eng. 64 (1-4) 321 - 328    DOI : 10.1016/S0167-9317(02)00805-5
Xu Z. , Lu J.-Q. 2011 “High-Speed Design and Broadband Modeling of Through-Strata-Via (TSVs) in 3D Integration,” IEEE Trans. Compon. Packag. Manuf. Technol. 1 (2) 154 - 162    DOI : 10.1109/TCPMT.2010.2101693
Olmen J.V. “3D Stacked IC Demonstrator Using Hybrid Collective Die-to-Wafer Boding with Copper Through Silicon Vias (TSV),” IEEE Int. Conf. 3D Syst. Integr. San Francisco, CA, USA Sept. 28-30, 2009 1 - 5    DOI : 10.1109/3DIC.2009.5306600