When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current (I
), on current (I
), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.
The improvement of device performance is a vital goal of the microelectronics community, and this can be done by scaling down the device dimensions
. However, as the technology scaling enters into the nanometer regime, the device exhibits various serious problems, such as low on current, increased leakage current, low reliability, and increase in manufacturing cost. To overcome these problems, various innovations in device structures have been researched and introduced. This has resulted in different structures with gate engineering, such as the Dual Material Gate (DM), Dual Insulator (DI) Gate, Gate Stack (GS), and channel engineering as graded channel (GC)
. Previously, Cheng et al.
have shown the impact of high-k gate dielectrics on the device short channel parameters. They have studied various short channel parameters, by taking gate stack engineering (i.e. one thick layer of high-k dielectric over one thin layer of low-k dielectric). Colinge
discussed the drive current and short channel effects (SCEs) for a SOI Multiple Gate MOSFET (MuGFET). From the simulation results, he concluded that SOI MuGFETs offer higher drive current, as well as better immunization to SCEs, than the conventional MOSFETs. Subramanian
presented a review paper on MuGFETs. He discussed the physics and technology of these devices, and their advantages and disadvantages. In Sharma et al.
, different gate engineering and channel engineering under DG-MOSFET technology are discussed, and also a comparison of various parameters among DG-DM, DG-GC, DG-GS-DM and DG-GS-GC is highlighted. Aouaj et al.
and Bendib et al.
discussed the concept of GC and GS on the double gate platform. In this work, we presented three types of device structures, DG-FD, DG-GC and DG-DI, by keeping speed in mind, as well as power consumption. The important parameters, like sub threshold swing (SS), drain Induced Barrier Lowering (DIBL), on current (I
), off current (I
), transconductance (g
), output conductance (g
) and Gain (g
) are extracted, and a comparison is made among these three devices.
- 2.1 Device structures
The schematic structures of DG-FD, DG-GC, and DG-DI MOSFETs are shown in
. In all structures, the channel length (L) is fixed at 40 nm, as well as the Source/Drain length (L
). The silicon thickness (t
) is 10nm, and a uniform density of ND as 10
is considered. The channel is doped (N
) of 1018 cm
in DG-FD and DG-DI. Whereas for DG-GC, the high-low profile of doping is taken as 10
and 1017 cm
. The oxide thickness tox = 2 nm, for all structurestructures a low-k spacer (Si
) is considered, for improvement of the device performance. The work function for the gate materials is assumed to be 4.8 ev.
- 2.2 Simulation
To obtain accuracy of simulation, the mobility degradation that occurs inside inversion layers is accounted for. The degradation normally occurs as a result of higher surface scattering near the semiconductor-to-insulator interface. So in the simulation, the inversion-layer Lombardi constant voltage and temperature (CVT) mobility model is activated, which takes into account the effect of transverse fields, along with doping and temperature dependent parts of the mobility. These components are combined using Matthiessen’s rule, as follows:
is the surface mobility by scattering with acoustic phonons.
is the surface roughness factor.
is the mobility by scattering with optical inter valley phonons.
The Shockley-Read-Hall (SRH) model simulates the leakage currents that exist due to thermal generation. Auger recombination models for minority carrier recombination have been used. In SOI technology, the potential in the channel is commonly referred to as “floating”. Furthermore, we chose Gummel’s method (or the decoupled method), which performs Gummel iteration for the Newton solution
3. RESULTS AND DISCUSSION
transfer characteristics are shown on a linear scale and log scale (Inset Figures) for three different device structures, and are compared for V
= 10 mV and 1.2 V. The DGDI MOSFET provides a larger drain current, as compared to the other two MOSFETs. This is because of the inclusion of higher dielectric material in the gate oxide, according to the relationship I
The Sub threshold Slope (SS) is the major parameter for calculating the off state current. Furthermore, SS is calculated as:
where, the logarithm is in base 10, I
is the drain current, and V
is the gate voltage. The SS is always expressed in millivolts per decade. The typical value for the SS of Multigate MOSFET is 60 mV /decade, i.e. a 60 mV change in gate voltage brings about a tenfold change in drain current. The SS is extracted by calculating the inverse of maximum slope of V
versus log (I
) curve, as shown in TABLE I. From the table, it is clear that the SS value is lower for DG-DI MOSFET, and again from equation (2)
, the off state current is directly related to the SS. So, the off state current is also minimum for the DG-DI MOSFET, as compared to
Schematic structure of DG-FD.
Schematic structure of DG-GC.
Schematic structure of DG-DI.
The drain current (ID) as a function of the gate voltage (VGS), onlinear and log scales (inset) at VDS = 10 mv, for the three structures.
the other MOSFETs, and as shown in
Again, the off state current (I
) is extracted, by calculating the drain current (I
) at V
= 0 and V
. The I
for all the three device structures is summarized in
. It is important to keep I
very small, in order to minimize the static power dissipation when the device is in off state.
The drain current (ID) as a function of the gate voltage (VGS), onlinear and log scales (inset) at VDS = 1.2 V, for the three structures.
where, W : width of the channel, L : Channel Length, Q : Electronic Charge, V
: Gate to Source Voltage, V
: Threshold Voltage, K: Boltzman Constant, T: Temperature in Kelvin, SS: Sub threshold Slope, and η : Body factor, which is proportional to the change in gate voltage with a change in channel potential, i.e.
From equation (4)
, the threshold voltage (V
) is also a very important parameter for higher on state current, which improves the circuit speed. The V
is extracted by calculating the maximum slope of the I
curve, finding the intercept with the xaxis, and then subtracting half of the applied drain bias, as given in Tables 1 and 2, for drain bias of 0.1 V & 1.2 V. The DG-GC shows a lower V
, because of the high-low doping profile taken for the Graded Channel, and according to equation (6)
is directly related to the doping profile. However, the doping profile being the same for DG-DI and DG-FD MOSFETs, the DG-DI MOSFET exhibits a lower V
than DG-FD MOSFET, which enables its speed of operation.
characteristics are compared for all the three device structures in
. The DG-DI MOSFET shows a higher value of transconductance, when compared with the other two MOSFETs. As we know:
So, the value of g
is extracted by taking the derivative of the I
curve, the values of which are summarized in
. From the extracted data, it can be examined that the DGDI MOSFET gives a higher g
value, and also a higher drain current. According to the relation in equation 7, g
is directly related to the drain current (I
). As far as analog circuits are concerned, g
is the most important parameter, because the value of g
Variation of the transconductance (gm) with VGS for the threedifferent structures, at VDS = 10 mV (inset figure) and 1.2 V.
Extracted parameters at VD= 0.1 V.
Extracted parameters at VD = 0.1 V.
Extracted parameters at VD= 1.2 V.
Extracted parameters at VD = 1.2 V.
directly related to the gain of the device (g
shows the output characteristics (I
) and output conductance (inset figure) for various DG configurations, at a gate voltage of 1.2 V. The DG-DI MOSFET gives an almost flat characteristic in saturation, and also exhibits high drain current, in comparison with the other DG configurations. In order to demonstrate the SCEs, the simulated output conductance is given in the inset figure. In the saturation region, the DG-DI MOSFET exhibits the lowest value of g
, but it exhibits the highest value of gd in the linear region. The Ion/I
ratio and DIBL are given in
for all of the three device structures. The value of DIBL is calculated as per the relation given in equation 8.
The DIBL calculation is taken for V
= 0.1 V and V
= 1.2 V. Both DG-GC and DG-DI MOSFETs give nearly equal values of DIBL, which is better, as compared to the DG-FD MOSFET. This is because of the high-low doping profile in GC, and the inclusion of high-k dielectric material in the DI structure. The I
ratio is much higher for the DG-DI MOSFET than for the other two structures, which is a very important parameter for both speed and standby power consumption. For circuit speed application, I
should be more, and for low power consumption application, I
should be less. So, there is always a tradeoff between I
The leakage current (I
) is calculated by considering V
= 0 for all the device structures, and is plotted in Fig. 6. It can be noticed that the DI architecture exhibits a very low leakage current, in comparison with the other two architectures. This is because the
Variation of the drain current (ID) and output conductance (gd)(Inset) with VDS, for the three different structures, at VGS = 1.2 V.
ID as a function of VDS for the different structures, at VGS = 0 V.
physical thickness of the gate dielectric is more, due to the highk dielectric material used in the DI structure. On the other hand, from equation 3, I
is related in the ratio of V
and SS. The DGDI architecture shows a higher value for the ratio of V
and SS, as compared to the others, according to
. Hence, it gives a lower I
, due to the exponential decaying nature of equation 3.
According to the International Technology Roadmap for Semiconductors, the SOI MOSFETs allow reduction of short channel effects. In order to study these new structures, numerical simulations are carried out. This work gives a close comparison of various design engineering, namely the FD, GC and DI of the DG-SOI. In this paper, the performance comparison for all the structures is limited to DC analysis only. Furthermore, the AC analysis can be done by investigating the analog and RF performance of the devices. The DG-DI MOSFET shows a significant
Extracted and calculated parameters.
Extracted and calculated parameters.
improvement in device characteristics, such as on current (I
), off current (I
, SS and DIBL. Hence, DG-DI MOSFET is a suitable candidate for both high speed and low power consumption application. This paper verifies all the relations, through extractive data obtained from the simulation results.
Mohapatra S. K.
Pradhan K. P.
Sahu P. K.
“Nanoscale SOIn-MOSFETs With Different Gate Engineering Having BiaxialStrained Channel - A Superlative Study”
Journal of Electron Devices
“Challenges for Nanoscale MOSFETs and EmergingNanoelectronics”
Transactions On Electrical And Electronic Materials
DOI : 10.4313/TEEM.2010.11.3.093
Sharma R. K.
Gupta R. S.
“TCAD Assessment ofDevice Design Technologies for Enhanced Performance of NanoscaleDG MOSFET”
IEEE Transactions On Electron Devices
Voorde P. V.
Greene W. M.
Stork J.M. C.
Zeitzoff P. M.
Woo J. C. S.
“The Impact ofHigh- Gate Dielectrics and Metal Gate Electrodes on Sub-100nm MOSFET’s”
IEEE Transactions on Electron Devices
DOI : 10.1109/16.772508
“Multiple Gate Field Effect Transistor for futureCMOS Technologies”
IETE Technical Review
DOI : 10.4103/0256-4602.72582
“Dual Material Gate-Graded Channel-Gate Stack (DMG-GC-Stack) surrounding gateMOSFET: Analytical threshold voltage (Vth) and subthresholdswing (S) models”
IEEE International Conference on Multimedia Computing and Systems - ICMCS
“Subthreshold behavior optimizationof nanoscale Graded Channel Gate Stack Double Gate(GCGSDG) MOSFET using multi-objective genetic algorithms”
J Comput Electron
DOI : 10.1007/s10825-011-0349-8
“Modern Semiconductor Devices for Integrated Circuits”