Advanced
Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide
Pillar Type Silicon-Oxide-Nitride-Oxide-Silicon Flash Memory Cells with Modulated Tunneling Oxide
Transactions on Electrical and Electronic Materials. 2013. Oct, 14(5): 250-253
Copyright ©2013, The Korean Institute of Electrical and Electronic Material Engineers
This is an open-access article distributed under the terms of the Creative Commons Attribution Non-Commercial License (http://creativecommons.org/licenses/by-nc/3.0) which permits unrestricted noncommercial use, distribution, and reproduction in any medium, provided the original work is properly cited.
  • Received : January 01, 2013
  • Accepted : August 08, 2013
  • Published : October 25, 2013
Download
PDF
e-PUB
PubReader
PPT
Export by style
Share
Article
Author
Metrics
Cited by
TagCloud
About the Authors
Sang-Youl Lee
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Seung-Dong Yang
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Ho-Jin Yun
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Kwang-Seok Jeong
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Yu-Mi Kim
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Seong-Hyeon Kim
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Hi-Deok Lee
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
Ga-Won Lee
Department of Electronics Engineering, Chungnam National University, Daejeon 305-764, Korea
gawon@cnu.ac.kr
Jae-Sub Oh
Division of Silicon on Insulator Technology, National Nanofab Center, Daejeon 305-806, Korea
Abstract
In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of N 2 ion implantation (N 2 I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage (V T ) of 0.13 V, and a higher g m.max of 18.6 μA/V and mobility of 27.02 cm 2 /Vs than the conventional and N 2 I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and N 2 I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.
Keywords
1. INTRODUCTION
In the memory market, low cost, low power, high density and high performance are important factors of devices to be used in digital equipment as storage. As the potential solution for high density flash applications, many researchers have proposed the silicon-oxide-nitride-oxide-silicon (SONOS) flash memory device. The SONOS device has many benefits, such as low operating voltage, scalability, and high compatibility with conventional technologies [1 , 2] . In this device, to increase the date storage capacity, the multi level cell (MLC) scheme can be adopted, because with MLC, it is possible to store more than one bit in each cell, by programming the cell threshold voltage [3] . However, in the case of the MLC device, V T fluctuations will cause a read failure, and become a prominent issue in designing a memory device. Another method is to reduce the cell size for high density memory implementation. But the limitation by reducing the device size cannot be avoided. For this, 3D devices with SONOS structure are applied to improve the electrical performances and storage capacity, such as the FiN and pillar type memory devices [4 , 5] .
In this paper, we fabricated 3D pillar type SONOS devices for high density flash applications. It is well known that SONOS has fundamental limitations, such as slow erase speed and poor data retention characteristics at the tunneling oxide thickness of less than 2 nm. In order to solve these problems, modulated tunneling oxide schemes are integrated with the SONOS structure, such as N 2 ion implantation (N 2 I/I) [6] , and the bandgap-engineering (BE) method [7] . In addition, flicker noise analysis is carried out, to compare each device characteristics, in particular, the interface properties.
2. EXPERIMENTS
To form the vertical silicon pillar, we used an 8-inch p-type (100) bulk wafer. Three-step chain implantation is applied for the source, channel and drain, respectively. The dopants are phosphorus (5×10 14 cm -2 , 1 MeV, tilt 7°), boron (8×10 13 cm -2 , 120 keV, tilt 7°) and arsenic (3×10 15 cm -2 , 80 keV, tilt 7°). After implantation, these dopants are activated under 1,050℃ in nitrogen ambient for 12 second. Afterwards, the wafers are etched for the formation of a Si pillar, using Cl 2 and HBr gas chemistry. Then, deposition and planarization of high density plasma silicon dioxide (SiO 2 ) are carried out. In the conventional and N 2 I/I devices, tunneling oxide of 5 nm is grown thermally, and a silicon nitride (Si 3 N 4 ) charge trapping layer of 6 nm is deposited by low pressure chemical vapor deposition (LPCVD). N 2 I/I is carried out with 3×10 15 cm -2 dose and 5 keV energy in the N 2 I/I device, to form a modulated tunneling oxide. In BE SONOS, the tunneling oxide consists of ONO layers, and the thickness of each layer is 2 nm. The charge trapping layer, Si 3 N 4 is deposited with 6 nm, as in the conventaional and N 2 I/I devices. Then, 8 nm thick blocking oxide is deposited in each device, by LPCVD. Finally, n-type poly-Si of 180 nm thickness is deposited, to form the gate. The fabricated device structures of the conventional, N 2 I/I, and BE SONOS are shown in Figs. 1 (a), (b) and (c), respectively.
The insets of Fig. 1 show the cross-sectional diagram of the tunneling oxide/trapping layer/blocking oxide, sequentially. First, inset (a) is a cross-sectional diagram of the conventional SONOS device, and each thickness is 5/6/8 nm, respectively. Second, inset (b) is a cross-sectional diagram of the N 2 I/I SONOS device, and each thickness is the same as for the conventional device. The other point with the conventional device, is that the nitrogen atoms are arranged in a tunneling oxide. A portion of nitrogen is bonded with SiO x . This can lead to barrier height lowering, and cause band offset. Finally, inset (c) is a cross-sectional diagram of the BE-SONOS device, and each thickness is 6(2/2/2)/6/8 nm, respectively. In this case, the tunneling oxide consists of the SiO 2 /Si 3 N 4 /SiO 2 layer. This also leads to the same results as the N 2 I/I device.
The electrical properties of the devices were measured at room temperature, using an Agilent 4156C analyzer.
3. RESULTS AND DISCUSSION
Figure 2 shows the transfer characteristic curves and transconductance (g m ) curves of each pillar type SONOS structure device. The measured sizes of pillar structure diameter and gate length are defined as 0.64 μm and 0.2 μm. The threshold voltage (V T ) values of 0.66 V, 0.92 V and 0.13 V are extracted from the conventional, N 2 I/I and BE-SONOS devices, respectively. The V T determines the power consumption of the device. As V T is small, a low power device can be made. The subthreshold slope (SS) that has 60 mV/decades at ideal states, g m.max , which is defined as the change in drain current with respect to the corresponding change in gate voltage, and the mobility are also important parameters to check for device performance. Table 1 dc parameter values of devices, which are extracted from the transfer characteristic curves.
The program and erase (P/E) characteristic are shown in Figs. 3 (a) and (b) as a function of pulse width. First, Fig. 3 (a) is the P/E
Lager Image
The structure of pillar type SONOS memory devices, and theinsets (a), (b) and (c) show cross-sections of the tunneling oxide ofthe conventional, N2 I/I, and BE SONOS, respectively.
The dc parameter extraction results of the fabricated pillar type conventional, N2I/I and BE-SONOS memory devices.
Lager Image
The dc parameter extraction results of the fabricated pillar type conventional, N2 I/I and BE-SONOS memory devices.
Lager Image
Comparison of VG-ID and VG-gm characteristics of the pillar typeSONOS memory devices.
characteristics at different gate voltage (V G ). In this case, the effect of modulated tunneling oxide can be known. It shows that the modulated tunneling oxide devices such as N 2 I/I and BESONOS have faster erase speed than the conventional device. In contrast to Fig. 3 (a), Fig. 3 (b) is the P/E characteristics at the same V G . In this case, which is the more suitable device can be known. This shows that the program speed of BE-SONOS device is much faster than that of the other devices at 10 V of V G . The erase speed is also much better than in other devices at -6 V of V G . Therefore, the BE method is suitable to use for modulated tunneling oxide. The reason for the superior program/erase speed in BE SONOS is well known by the energy band offset [7] .
In the case of the N 2 I/I device, it seems that the nitrogen bonds are implanted with SiO x . According to a recent study, the P/E speed can be improved, using silicon oxynitride (SiON) to replace the oxygen of the tunneling oxide by nitrogen [8] . In other words, the SiON in the tunneling oxide can make a band offset, which increases the electron/hole tunneling. In this case, the barrier height of the energy band is lower, due to the energy
Lager Image
Program/erase characteristic of each pillar type SONOS memorydevice. (a) In comparison with the BE-SONOS device, the largerprogram/erase gate voltage is forced to the conventional with the N2I/I device and (b) the same program/erase voltage is forced on eachdevice.
band gap of SiO 2 being 8.9 eV, and that of SiON being 5.1~8.9 eV. The barrier heights of conventional, N 2 I/I and BE devices are 3.05 eV, 2.7 eV and 0.35 eV for the electron, and 4.6 eV, 3.65 eV and 1.9 eV for the hole, respectively. The reason for increased electron/ hole tunneling can be confirmed in Fig. 4 . The band offset of the conventional device is 0, of the N 2 I/I device is approximately 0.95 eV, and of the BE device is 2.7 eV. In this case, the charges can move easily from band to band. As shown in Fig. 4 , the larger the energy band offset becomes, the more easily charges can move, due to the reduction of thickness of the tunneling path while the voltage is applied.
The higher program/erase speed of the BE-SONOS device means that lower voltage operation is possible. When the program/ erase voltage is lowered, the endurance characteristics can be improved. Fig. 5 shows the endurance properties of pillar type SONOS memory devices at different program/erase voltages, to adjust the program/erase speed. The ΔV T.endu . equation is shown below.
Lager Image
where, V P.init . and V E.init . are the V T , when the P/E voltage is applied the first time. The V E is the V T when the erase voltage is applied at various times. The ΔV T.endu . means that as the value increases, V E nearly approaches V P.init . In this case, it is explained that the device is degraded. From Fig. 5 , it is known that the BE-SONOS
Lager Image
Energy band diagram of each pillar type SONOS memorydevice. (a) conventional, (b) N2 I/I, and (c) BE SONOS device. Thebandgap of SiO2 and Si3N4 is about 8.9, 5.1 eV, respectively. The SiONbandgap is between 5.1 and 8.9 eV.
Lager Image
Endurance characteristics of each pillar type SONOS memorydevice. The condition of program/erase voltages and times of theconventional, N2 I/I and BE-SONOS are 16 V 100 ms / -19 V 100 ms,15 V 10 ms / -19 V 100 ms and 12 V 1 ms / -9 V 60 ms, sequentially.
Lager Image
Data retention characteristics of each pillar type SONOS memorydevice. Applied voltages at the program state are 17 V 5 ms, 17V 50 ms and 12 V 10 ms in the conventional, N2 I/I, and BE-SONOS,respectively. In the case of the erase state, the applied voltages are 12V 2 ms, -19 V 100 ms and -9 V 20 ms, sequentially.
device is more stable than other devices.
Figure 6 presents the data retention characteristics of each pillar type SONOS device, when the device is programmed and erased with V T = 4 V and 2 V, respectively. This shows that all the devices have good data retention characteristics. The reason
Lager Image
Normalized drain current noise spectra density versus frequencyof pillar type SONOS memory devices.
can be explained by the thick tunneling oxide thickness, and the trapping layer using Si 3 N 4 has strong charge trapping properties [9] . In other words, the stored charge can leak less than 2 nm of tunneling oxide. However, the tunneling oxide thickness among the devices is thicker than 2 nm, as follows: the conventional, N 2 I/I and BE-SONOS device has 5 nm, 5 nm and 6 nm, respectively. In addition, before using Si 3 N 4 as a trapping layer, poly-Si, which has a conductor characteristic, is widely used as a trapping layer. The Si 3 N 4 has an insulator characteristic, so charge stored properties of Si 3 N 4 are better than poly-Si. That is, under a high electric field, the band offset of an ultra-thin O1/N1/O 2 will block out the tunneling barrier of the N1 and O 2 layers, and the tunneling distance for holes can effectively be reduced to O1, which will induce a large hole current. The retention characteristics can also be improved, because the total thickness of O1/N1/O 2 will prohibit the direct tunneling of holes in a low electric field.
In order to evaluate the interface characteristic or tunneling oxide quality, flicker noise analysis is carried out [10] . As shown in Table 1 , the three devices have similar SS values, and this means that interface comparison is difficult by SS value. Fig. 7 shows the normalized drain current noise spectra density (S ID /I 2 D ) of pillar type SONOS memory devices. The measured S ID /I 2 D of pillar type devices is much higher than previously reported values in a SONOS device [11] , but the S ID /I 2 D is clearly in inverse proportion to the frequency. From the noise level, the interface characteristics or tunneling oxide quality of conventional and N 2 I/I devices are similar. That is, the implanted N 2 ions are located above the interface of at least 2 nm, and both the devices have similar interface characteristics or tunneling oxide qualities. The noise level of the BE-SONOS device, however, is larger than the conventional and N 2 I/I devices, by about 1 order. This analysis result can be explained by the BE-SONOS device having more traps or defects in tunneling oxide, due to the nitride layer of ONO as tunneling oxide, which should be considered in applying the BE-SONOS devices.
4. CONCLUSIONS
In this paper, we fabricated, characterized and compared the conventional pillar type, N 2 I/I and BE-SONOS memory devices. Compared with the conventional SONOS device, modulated tunneling oxide devices show improved erase speed, and seem to be proper for the next generation memory application. In particular, the BE-SONOS device shows higher P/E speed performance than other devices, due to the large energy band offset. Charges can easily move from band to band, when the bias is applied. The flicker noise, however, confirms that the BE-SONOS device has more traps or defects in the tunneling oxide, which should be considered carefully, in designing the process conditions.
Acknowledgements
This work was supported by a research fund of Chungnam National University (2012-1713).
References
Bu J. , White M. H. (2001) Solid-State Electronics 45 113 -
Shin Y. S. (2005) VLSI Circuits Digest of Technical Papers 10 156 -
Ricco B. , Torelli G. , Lanzoni M. , Manstretta A. , Maes H. E. , Montanari D. , Modelli A. (1998) Proceedings of the IEEE 86 2399 -
Hsu T. H. , Lue H. T. , King Y. C. , Hsieh J. Y. , Lai E. K. , Hsieh K. Y. , Liu R. , Lu C. Y. (2007) IEEE Electron Device Letters 28 443 -
Sun Y. , Yu H. Y. , Singh N. , Shen N. S. , Lo G. Q. , Kwong D. L. (2010) IEEE Electron Device Letters 31 390 -
Oh J. S. , Yang S. D. , Lee S. Y. , Kim Y. S. , Kang M. H. , Lim S. K. , Lee H. D. , Lee G. W. (2013) Microelectronic Engineering 103 33 -
Lue H. T. , Wang S. Y. , Lai E. K. , Shih Y. H. , Lai S. C. , Yang L. W. , Chen K. C. , Ku J. , Hsieh K. Y. , Liu R. , Lu C. Y. 2005 IEEE International Electron Devices Meeting Washington, USA 547 -
Liao J. H. , Hsieh J. Y , Yang L. W , Yang T. , Chen K. C. , Lu C. Y. (2010) International Reliability Physics Symposium 10 639 -
Wilk G. D. , Wallace R. M. , Anthony J. M. (2001) Journal of Applied Physics 89 5243 -
Bae S. H. , Lee J. H. , Kwon H. I. , Ahn J. R. , Om J. C. , Park C. H. , Lee J. H. (2009) IEEE Transactions on Electron Devices 56 1624 -
Hu H. H. , Jheng Y. R. , Wu Y. C. , Hung M. F. , Huang G. W. (2012) IEEE Electron Device Letters 33 1276 -