This paper proposes a new interleaved doubleinput threelevel Boost (DITLB) converter, which is composed of two boost converters indirectly in series. Thus, a high voltage gain, together with a low component stress and a small input current ripple due to the interleaved control scheme, is achieved. The operating principle of the DITLB converter under the individual supplying power (ISP) and simultaneous supplying power (SSP) mode is analyzed. In addition, closedloop control strategies composed of a voltagecurrent loop and a voltagebalance loop, have been researched to make the converter operate steadily and to alleviate the neutralpoint imbalance issue. Experimental results verify correctness and feasibility of the proposed topology and control strategies.
I. INTRODUCTION
In a renewable power generation system with many different input sources, many individual dcdc converters together with independent control schemes are necessary, which are both complex and increase the cost of the system. Integrating different input sources with distinct electrical characteristics into a common system while still achieving a high efficiency and good performance is an important topic. To attain the goal of integration, a multiinput converter (MIC) is a perfect choice, which may integrate diverse power sources and provide power to a common load in a single conversion stage
[1]
.
Many papers related to a variety of MIC topologies have been published. In
[2]
, a systematic approach to synthesizing MICs by introducing pulsating voltage source cells and pulsating current source cells into six basic PWM converters is proposed. Four rules that must be observed in order to realize a MIC from its singleinput version are listed in
[3]
. In renewable power generation systems, MIC topologies are usually integrated with a dc link. However, most of these MICs do not take the high voltage gain into consideration, since the outputs of photovoltaic cells, fuel cells and battery cells are typically unregulated lowlevel dc voltages that need to be stepped up to regulated, highlevel voltages for practical applications.
At present, the conventional Boost converter is usually used because of its simple circuit. Unfortunately, practical considerations limit its output voltage to about four times its input voltage
[4]
. To increase the voltage gain and achieve other performances, many high stepup converter topologies have been proposed. A high stepup activeclamp converter composed of an input current doubler and a symmetrical switchedcapacitor circuit is proposed in
[5]
. Although a high voltage gain is achieved, many switches are needed. Several high setup converter topologies that use coupled inductors have been proposed for the fuel cell generation systems
[6]
,
[7]
. Although a high voltage gain is obtained, their efficiencies are degraded due to the losses associated with leakage inductances. In addition, coupled inductors may introduce high switch voltage stress and EMI problems.
Recently, some stepup dc–dc converters have been studied. However, but they are limited to singleinputsingleoutput systems
[8]

[10]
. The system structure of a conventional threelevel Boost converter (CTLB) combined with a threelevel diodeclamped inverter has been proposed to achieve a high medium voltage and a high power. In addition, a small input current ripple and a neutralpoint voltage control can be achieved
[11]

[13]
. However, the stepup capacity of the systems is limited due to the CTLB converter, which is only 1/(1D). A novel hybrid threelevel Boost (HTLB) converter had been proposed to achieve a high voltage gain at the expense of increasing the number of components and the addition of a complex modulation strategy
[14]
.
[15]
,
[16]
propose a series of multilevel boost converters based on switchedcapacitor networks, which have high voltage gains and a selfbalance function for capacitor voltages. In addition, the selfbalance function is highly advantageous for balancing the dc link capacitor voltages of diodeclamped multilevel inverters
[17]
,
[18]
. However, since no interleaved scheme is adopted, the input current ripple and the current stress of a single switch are both very large, which are great disadvantages for FC and BC systems.
[19]
proposes a threelevel Boost converter with a flyingcapacitor (FCTLB) and
[20]
transforms this converter into a multiinput converter. Although a high voltage gain and small ripples are achieved, the voltage stresses across the output diode are high. In addition, two doubleinput converters operating in the ISP mode and in the SSP mode are proposed with a high voltage gain and small component stresses
[21]
. However, it is difficult to integrate the two converters, and many capacitors are necessary.
On the whole, multiinput stepup converters are essential for integrating different energy sources with low voltage levels. The development of multiinput stepup converter topologies goes through three stages, as shown in
Fig.1
. In
Fig. 1
(a), a MIC structure is constructed by placing several stepup converters in parallel with all of the output terminals. However, the output voltage gain is limited due to its parallel structure. Then, the MIC structure shown in
Fig. 1
(b) is proposed by placing the output terminals in series. However, the input terminals and output terminals usually do not share the same ground, which may introduce an electromagnetic interference (EMI) problem and increase the quantity of isolated power drivers. Therefore, the MIC structure shown in
Fig. 1
(c) should be the best choice to alleviate the above mentioned problems. This structure has a high voltage gain since the output terminals are directly or indirectly connected in series. In addition, the input terminals and output terminals have a common ground, which helps reduce EMI and cost of driver circuits. Additionally, an interleaved control scheme can be easily adopted to decrease the input current ripple.
The development of multiinput stepup converters.
In this paper, a new DITLB converter is proposed that can operate under the individual supplying power (ISP) mode and the simultaneous supplying power (SSP) mode. A small input current ripple, low current stresses and low voltage stresses across all of the power devices are achieved. Additionally, the selfbalance function for capacitor voltages is included. This paper is organized as follows: Section II introduces the operation principle of the proposed converter. A performance analysis is subsequently presented in Section III. A closedloop control strategy for the proposed DITLB converter under different operating modes has been presented in Section IV, and experimental verification is presented in Section V. Finally, some conclusion have been drawn in Section VI.
II. THE PROPOSED DITLB CONVERTER
The proposed DITLB converter is presented in
Fig. 2
. To analyze the converter, the converter is divided into three cells: cell 1, cell 2, and cell 3. Cell 1 (including
L
_{1}
,
S
_{1}
,
D
_{1}
, and
C
_{1}
) and cell 2 (including
L
_{2}
,
S
_{2}
,
D
_{3}
, and
C
_{2}
) are Boost converters. Cell 3 is composed of
C
_{3}
and
D
_{2}
, and connects the two Boost converters in series. Therefore, the operating principle of the DITLB under the continuous conduction mode (CCM) is different from that of two Boost converters directly in series. The proposed converter is controlled by the interleaved operation scheme of
S
_{1}
and
S
_{2}
, where the two carrier signals
C
_{a1}
and
C
_{a2}
have a phase shift of 180 degrees. To simplify the analysis process, some assumptions are made as follows:
The proposed DITLB converter.
1) The inductor currents
i
_{L1}
and
i
_{L2}
and the input current
i
_{in}
are continuous, and their average values are labelled as
I
_{L1}
,
I
_{L2}
, and
I
_{in}
.
2)
u
_{L1}
and
u
_{L2}
represent the voltages across
L
_{1}
and
L
_{2}
, and
U
_{C1}
,
U
_{C2}
, and
U
_{C3}
represent the capacitor voltages of
C
_{1}
,
C
_{2}
, and
C
_{3}
.
3) All of the components are ideal without considering any parasitic parameters.
According to the definition of a MIC, the proposed converter works under both the ISP mode and the SSP mode. In
Fig. 2
, the turnon and turnoff of
Q
_{1}
,
Q
_{2}
, and
Q
_{3}
determine the operating mode. When
Q
_{1}
, and
Q
_{3}
are turned on while
Q
_{2}
is turned off, the DITLB converter operates under the ISP mode with input source 1 supplying power. In addition, when
Q
_{2}
and
Q
_{3}
are turned on while
Q
_{1}
is turned off, the DITLB converter operates under the ISP mode with input source 2 supplying power. However, when
Q
_{1}
and
Q
_{2}
are turned on while
Q
_{3}
is turned off, the DITLB converter operates under the SSP mode with the two input sources supplying power simultaneously.
 A. Operating Principle under ISP Mode
Under the ISP mode, the two switches
S
_{1}
and
S
_{2}
in the DITLB converter are controlled by an interleaved operation scheme with the same duty cycle
D
. Since the converter operates under the same operating principle regardless of which input source is used, the ISP mode with input source 1 is taken as an example for the theoretical analysis. Equivalent circuits of the converter under this mode are shown in
Fig.3
and typical waveforms are given in
Fig.4
. The basic operating principle is presented as follows.
Equivalent circuits of the DITLB converter under ISP mode with input source 1 supplying power:
Typical waveforms.
Stage I: during this period,
L
_{1}
and
L
_{2}
are both charged by
U
_{in1}
. The conduction of
S
_{1}
and
D
_{2}
provides a pathway for
C
_{2}
and
C
_{3}
to be connected in parallel. Thus, the following expressions can be achieved:
Stage II: during this period,
L
_{1}
is still charged by
U
_{in1}
. Additionally,
C
_{2}
is still in parallel with
C
_{3}
, which is charged by
L
_{2}
and
U
_{in1}
. Thus, the voltage across
L
_{2}
is changed by:
Stage III: during this period,
L
_{2}
is charged by
U
_{in1}
and the same formula (2) can be obtained. However, the voltage across
L
_{1}
is described by:
(5) can be simplified by combining (3):
Stage IV: during this period, the voltage across
L
_{1}
is the same as (6). In addition,
C
_{3}
is charged by
L
_{2}
and
U
_{in1}
. Thus, the voltage across
L
_{2}
is the same as (4).
In all four stages, the output voltage of the converter is the sum of
U
_{C1}
and
U
_{C2}
. Since the two Boost converters are indirectly in series, i.e.:
According to the interleaved operation scheme, the converter can operate under two conditions:
D
>0.5 and
D
<0.5. When the duty cycle
D
is bigger than 0.5, it operates at the periodic stages of I, II, I, and III. Accoding to (1)(5) and (7), voltage gain and capacitor voltages can be achieved:
It can be seen from (9) that the three capacitor voltages are equal. It should be noted that
U
_{C2}
and
U
_{C3}
are selfbalanced due to the switchedcapacitor network, while
U
_{C1}
and
U
_{C2}
are balanced since they have the same duty cycle
D
. On the whole, it is called selfvoltagebalance function.
Additionally, the current ripples of
L
_{1}
and
L
_{2}
shown in
Fig. 4
, can be obtained as follows:
At the same time, it is easy to obtain the input current ripple:
When the duty cycle
D
is smaller than 0.5, the proposed converter operates at the periodic stages of IV, II, IV, and III; and the same results shown in (8)(10) can be achieved. Under this operating state, the input current ripple is changed by:
Regardless of the duty cycle D, stages II and III have the same operating time. At stage II, the capacitor
C
_{3}
is charged by
U
_{in1}
and
L
_{2}
with the current
I
_{L2}
. Meanwhile, at stage III,
C
_{3}
discharges energy to the load with the current
I
_{L1}
. According to the AmpereSecond Balance Principle for
C
_{3}
, it is not difficult to conclude that
I
_{L1}
is equal to
I
_{L2}
. This is called selfcurrentbalance function. Then, based on the Power Conservation Principle, there is:
(13) can be simplified by combining (8):
It should be note that similar results can be achieved when the converter operates under the ISP mode with input source 2.
It is well known that the discontinuous conduction mode (DCM) occurs when the inductor current ripple becomes greater than the average inductor current. Since cell 1 and cell 2 have the same inductance, the inductor
L
_{2}
is taken as an example:
The integration of (8), (10) and (14) into (15) yields the following condition for the DCM mode:
Where
K
is equal to 2
Lf
_{s}
/
R
, and
K
_{crit}
(D) is the critical value of
K
at the boundary between the CCM and DCM modes:
The maximum value of
K
_{crit}
(D) can be easily achieved at
D
= 1/3.
If
K
is greater than 2/27, the converter operates under the CCM mode for all values of
D
. If
K
is smaller than 2/27, the converter operates under the DCM mode for some intermediate range values of
D
near
D
=1/3. Thus, the minimum inductance
L
_{min}
should be:
(19) is simplified to achieve
L
_{min}
as follows:
 B. Operating Principle under SSP Mode
When
Q
_{1}
and
Q
_{2}
turn on while
Q
_{3}
turns off, the proposed DITLB converter operating under the SSP mode is shown in
Fig. 5
. Under this mode, cell 1 and cell 2 operate independently, i.e. cell 1 does not affect cell 2. In addition, the two cells are controlled by two independent closedloop control strategies. It should be noted that the converter does not need to operate with an interleaved operation scheme, since the two input sources feed the load simultaneously. Thus, it is not difficult to obtain the output voltage and capacitor voltages as follows:
The two average inductor currents can be described by:
The DITLB converter operates under SSP mode.
III. CLOSEDLOOP CONTROL STRATEGY
As analyzed in section II, the proposed DITLB converter under the ISP mode has a voltagebalance function for the capacitor voltages. However, like threelevel Boost converters, the converter also has a neutralpoint balancing problem due to the interleaved operation scheme. In addition, the IGBTs and power diodes usually have some voltage drops, which should be considered in practical circuit design. If
U
_{d}
is assumed to be the voltage drops, two voltagesecond equations can be rewritten by:
Then, the output voltage and capacitor voltages can be achieved based on (26) and (27):
The voltage difference between
C
_{1}
and
C
_{2}
can be obtained based on (29) and (30)
It can be seen from (31) that there is a voltage difference 2
U
_{d}
between
C
_{1}
and
C
_{2}
due to the voltage drops. Although it is small, the voltage drops may result in a neutralpoint balancing problem.
 A Closedloop Control under ISP Mode
To alleviate the neutralpoint problem of the proposed converter under the ISP mode, a voltagecurrent loop together with a simple voltagebalance loop is presented in
Fig. 6
.
Closedloop control strategy under ISP mode.
As analyzed in section II, cell 1 and cell 2 represent two Boost converters, whose output terminals are connected in series. In addition, the two Boost converters are controlled by an interleaved scheme with the same duty cycle
D
. Thus, the same average inductor current and output capacitor voltage can be achieved. By only controlling one of the Boost converters, the input current and output voltage of the converter can be easily controlled to be stable. In
Fig. 6
, cell 2 is taken as the target to be controlled by voltagecurrent loop 2. By controlling the capacitor voltage
U
_{C2}
and the inductor current
I
_{L2}
, it is easy to get the duty cycle
d
_{2}
of
S
_{2}
.
The voltagebalance loop aims at reducing the voltage difference between
C
_{1}
and
C
_{2}
. In the voltagebalance loop, the difference duty cycle Δ
d
is achieved through a simple PI controller by the difference voltage Δ
U
. Then, the duty cycle
d
_{1}
of the switch
S
_{1}
can be easily obtained by:
From (32), the voltagebalance process is: when
U
_{C2}
is bigger than
U
_{C1}
, Δ
d
becomes positive, which makes
d
_{1}
a little bigger than
d
_{2}
. Then,
U
_{C1}
increases to follow
U
_{C2}
, and is finally equal to
U
_{C2}
after several switching periods. It should be noted that Δ
d
is very small, since the voltage difference is very small. Thus, voltagecurrent loop 2 cannot be greatly affected.
 B Closedloop Control under SSP Mode
Under the SSP mode, the two Boost converters are controlled independently by voltagecurrent loop 1 and voltagecurrent loop 2, as shown in
Fig. 7
. The capacitor voltages are controlled to be equal by setting the same referring voltage for the two Boost converters, i.e.
U
_{C1}
* is equal to
U
_{C2}
*. Thus, there is no need to use a voltagebalance loop under this mode.
Closedloop control strategy under SSP mode.
IV. PERFORMANCE ANALYSIS
 A. Comparative Analysis
For both the ISP and SSP modes, the voltage stresses across the two switches are equal and the voltage stresses across all of the diodes are also equal. They are given as follows:
U
_{VPS}
and
U
_{VPD}
represent the voltage stresses across the switches and diodes, respectively.
Under the ISP mode, the average current stress across all of the diodes and two switches are equal, shown in (34) and (35):
I
_{VPS}
and
I
_{VPD}
represents the current stresses across switches and diodes, respectively.
As given in Section I, the CTLB, HTLB, FCTLB, and SCTLB converters are conventional threelevel Boost, hybrid threelevel Boost, threelevel Boost with a flyingcapacitor, and threelevel Boost with a switchedcapacitor network, respectively. It should be noted that the SCTLB converter is one version of the multilevel Boost converters in
[15

18]
.
Table I
shows comparative results among the CTLB, HTLB, FCTLB, SCTLB, and the proposed TLB converters.
COMPARATIVE ANALYSIS AMONG CTLB, HTLB, FCTLB, SCTLB CONVERTERS AND PROPOSED TLB CONVERTER
COMPARATIVE ANALYSIS AMONG CTLB, HTLB, FCTLB, SCTLB CONVERTERS AND PROPOSED TLB CONVERTER
In the four threelevel Boost converters, the HTLB has the highest voltage gain when the modulation indexes m
_{a}
and m
_{b}
are set well. However, so many components are necessary and the modulation strategy is complex. The SCTLB has a high voltage gain and a selfvoltagebalance function with its input and output sharing a common ground. However, the input current and current stress across only one switch is very large, since it cannot use an interleaved scheme. Although interleaved schemes are adopted, the CTLB has no selfvoltagebalance or currentbalance functions. More importantly, its input and output do not share the same ground and its voltage gain is limited to 1/(1D). Compared with CTLB, HTLB, SCTLB converters, the converter FCTLB presents relatively good performances. However, the output diode and output capacitor have very high voltage stresses, which are equal to the output voltage. Furthermore, since the output capacitor of the FCTLB is not composed of two split capacitors and is independent from its input, it cannot achieve the selfvoltagebalance function or the voltagebalance control. However, all of these issues in the CTLB, HTLB, FCTLB and SCTLB, can be mostly avoided in the proposed TLB. Firstly, small voltage stresses for all of the components are achieved because cell 1 and cell 2 are in series. Secondly, small current stresses for these components are also achieved due to the interleaved operation scheme. Moreover, the selfvoltagebalance function and the selfcurrentbalance function help make cell 1 and cell 2 have the same performances. Lastly, the input source and output terminal share a common ground. Thus, the driver circuit of
S
_{1}
and
S
_{2}
can share the same power supply, reducing the design cost of the drive circuits. On the whole, the proposed TLB is the best converter.
 B. The Key Function of Cell 3
As analyzed in Section II, cell 1 and cell 2 in the proposed converter, are two Boost converters, which share the same input source with the outputs in series. This is similar to an inputserialoutputparallel (IPOS) dc/dc system, which is usually composed of isolated dc/dc converters. However, unlike an IPOS dc/dc system, the proposed converter is composed of nonisolated dc/dc converters owing to cell 3. Because of cell 3 and
S
_{1}
,
C
_{2}
constructs a switchedcapacitor network that has the selfvoltagebalance function. Therefore, the two capacitor voltages of
C
_{2}
and
C
_{3}
are easy to selfbalanced when
S
_{1}
is turned on, as shown in
Fig. 3
(a) and
Fig. 3
(b). In addition, this voltagebalance mechanism has been reported in
[15]

[18]
. Thus, a high voltage gain and a small input current ripple can be easily achieved. The voltagebalance mechanism for a converter under the ISP mode with
U
_{in1}
is: the energy of
C
_{3}
comes from
L
_{1}
and
U
_{in1}
, and the energy of
C
_{2}
comes from
L
_{2}
and
U
_{in1}
. Cell 1 and cell 2 can easily output the same capacitor voltage, since they are controlled by an interleaved scheme with the same duty cycle. Furthermore, the voltages of
C
_{3}
and
C
_{2}
are selfbalanced due to the switchedcapacitor network. Therefore, the voltages of
C
_{1}
,
C
_{2}
, and
C
_{3}
are equal.
The voltagebalance mechanism for the converter under the ISP mode with
U
_{in2}
is the same as the above mentioned mechanism. On the whole, it is the key function of cell 3 that makes the proposed converter have a high voltage gain and the other good performances mentioned above.
 C. Extension
Multiinput converters with more input sources and more output levels can be extended from the proposed DITLB converter.
Fig. 8
shows the topology of an extended threeinput fourlevel Boost converter, where there are three
The threeinput fourlevel Boost converter.
Boost converters:
U
_{in1}
,
S
_{1}
,
L
_{1}
,
D
_{1}
,
C
_{1}
;
U
_{in2}
,
S
_{2}
,
L
_{2}
,
D
_{3}
,
C
_{2}
; and
U
_{in3}
,
S
_{3}
,
L
_{3}
,
D
_{5}
,
C
_{3}
.
A small input current and little current stress across every switch can be achieved. In addition, small voltage stresses 1/3
U
_{o}
across all of the components besides
C
_{4}
, can be achieved. In the extended converter, besides the switchedcapacitor network, is composed of
S
_{2}
and
C
_{5}
.
D
_{4}
and
C
_{3}
, are the components
S
_{1}
and
C
_{4}
.
D
_{2}
,
C
_{2}
, and
C
_{3}
form another switchedcapacitor network. Thus, the voltage stress across
C
_{4}
is 2/3
U
_{o}
, which is the sum of
U
_{C2}
and
U
_{C3}
.
When
Q
_{1}
,
Q
_{2}
, and
Q
_{3}
are turned on and
Q
_{4}
and
Q
_{5}
are turned off, the converter operates under the SSP mode with all three input sources supplying power simultaneously. The output voltage under this mode can be given as follows:
In addition, the converter can also operate under the ISP mode with any two input sources. For instance, when
Q
_{2}
,
Q
_{3}
, and
Q
_{4}
are turned on and
Q
_{1}
and
Q
_{5}
are turned off, the input sources
U
_{in2}
and
U
_{in3}
feed the load simultaneously. Under this mode, the output voltage is:
Under the ISP mode with only one input source supplying power, all three of the switches can be controlled by three interleaved drive signals, which are phase shifted 120 degrees. For example, when
Q
_{3}
is turned on and
Q
_{1}
,
Q
_{2}
,
Q
_{4}
, and
Q
_{5}
are turned off, the converter operates under the ISP mode with the input source
U
_{in3}
. In addition, the output voltage under this mode can be descripted by:
As shown in
Fig. 2
and
Fig. 8
, the proposed DITLB converter and the extended converter are a good choice to connect with NeutralPointClamped (NPC) multilevel inverters to achieve a medium voltage and a high power. With this configuration, the capacitor voltages of the dc link can be controlled with the voltagebalance control strategy in multiinput dc/dc converters, which gives control flexibility to the NPC multilevel inverters to effectively track the grid current references. It is greatly different from the voltagebalance control strategies used in multilevel inverters to solve the neutral point imbalance issue.
V. EXPERIMENTAL VERIFICATION
To verify the correctness and feasibility of the proposed DITLB converter, a small power prototype based on Dspace1006 has been built with the experimental parameters given in
Table II
. In addition, the drive circuits are designed based on a photocoupler HCPL3120. For the sake of simplicity, the two input voltages are set to have the same voltage range 48V80V. To get the output voltage 400V, the referenced capacitor voltages
U
_{C2}
* and
U
_{C3}
* are both set to 200V. Both steady state and dynamic experimental results have been given. In addition, an efficiency analysis for the proposed DITLB converter under both the ISP and SSP modes is presented.
EXPERIMENTAL PARAMETERS
 A. Steady State Experiments
According to the analysis in Section III, the converter under the ISP mode with different input sources operate at the same main circuit. Thus, experimental results of the converter, when
U
_{in1}
with 48V supplies energy to the load independently, are given in
Fig. 9
. In addition, experimental results, when
U
_{in2}
with 80V feeds the load independently, are presented in
Fig. 10
.
Under ISP mode with U_{in1} 48V.
Under ISP mode with U_{in2} 80V.
As can be seen from
Fig. 9
and
Fig. 10
, the output voltage is stable with 400V no matter which input source is used. The duty cycles of
S
_{1}
and
S
_{2}
decrease when the input voltage changes from 48V to 80V. The inductor current ripple and input current ripples are given to compare with their theoretical values, as shown in
Table III
. The theoretical values are calculated based on (10), (11) and the tested duty cycle
D
. In
TABLE III
, Δ
i_{L}
^{*}
means the theoretical value of the two same inductor current ripples, and Δ
i
_{in1}
^{*}
means the theoretical value of the input current ripple. The experimental values are in good agreement with theoretical values. In addition, the input current ripple is small due to the interleaved scheme. More importantly, the ripple frequency of the input current 50kHz is two times the switching frequency 25kHz, which helps design an input filter with a smaller size.
COMPARATIVE ANALYSIS
Under the SSP mode, key experimental waveforms with different input voltages are presented in
Fig. 11
and
Fig. 12
. With two different input voltages, the converter can still operate with a stable output voltage 400V. In addition, the capacitor voltages are all 200V, which is half of the output voltage. According to (24) and (25), the theoretical values for
I
_{L1}
and
I
_{L2}
when
U
_{in1}
is 48V and
U
_{in2}
is 80V, are 3.33A and 2.00A, respectively. In addition, in the experiment test,
I
_{L1}
is 3.68A and
I
_{L2}
is 2.10A, which basically agrees with the theoretical values. Furthermore, when
U
_{in1}
is 80V and
U
_{in2}
is 48V,
I
_{L1}
is 2.12A and
I
_{L2}
is 3.66A, which also agrees with the theoretical values of 2.10A and 3.68A.
Under SSP mode with U_{in1} 48V and U_{in2} 80V.
Under SSP mode with U_{in1} 80V and U_{in2} 48V.
Terminal voltage waveforms of
S
_{1}
,
S
_{2}
,
D
_{1}
,
D
_{2}
, and
D
_{3}
under the ISP mode when
U
_{in1}
is 48V are taken as an example to be presented in
Fig. 13
. It should be noted that
u
_{S1}
and
u
_{S2}
are defined to describe the voltage difference between the collector terminal and the emitter terminal of the IGBTs
S
_{1}
and
S
_{2}
. In addition,
u
_{D1}
,
u
_{D2}
, and
u
_{D3}
are given to define the voltage difference between the cathode and the anode of the power diodes
D
_{1}
,
D
_{2}
, and
D
_{3}
. It is clear from
Fig. 13
that the top voltages of all of the switches and diodes in the converter are 200V, which is half of the output voltage 400V. In addition, it is not difficult to know that the conduction and shutdown of
D
_{1}
is complementary to that of
D
_{2}
, and that the conduction and shutdown of
D
_{1}
has a phase shift of 180 degrees with
D
_{3}
. Furthermore, the conduction and shutdown of
S
_{1}
also has a phase shift of 180 degrees with
S
_{2}
. All these results verify correctness and feasibility of the proposed converter.
Under ISP mode with U_{in1} 48V.
 B. Dynamic Experiments
Dynamic researches on the proposed DITLB converter have also been carried out. Dynamic experimental waveforms of the DITLB under the ISP mode with different jump conditions are presented in
Fig. 14
. Dynamic results of the DITLB under the SSP mode when
U
_{in1}
jumps from 48V to 70V and
U
_{in2}
jumps from 48V to 80V simultaneously, are presented in
Fig. 15
.
Dynamic experimental waveforms under ISP mode.
Dynamic experimental waveforms under SSP mode: U_{in1} jumps from 48V to 70V and U_{in2} jumps from 48V to 80V.
As shown in
Fig. 14
(a), when
U
_{in1}
with 48V jumps to
U
_{in2}
with 80V,
I
_{L2}
drops from 3.68A to 2.10A and
I
_{in}
drops from 7.40A to 4.24A. In addition,
U
_{o}
increases and then drops to be stable with 400V. In
Fig. 14
(b), when
U
_{in1}
with 80V jumps to
U
_{in2}
with 48V,
I
_{L2}
increases from 2.12A to 3.66 and
I
_{in}
increases from 4.21A to 7.39A. In addition,
U
_{o}
drops a little and then increases to be stable with 400V. The dynamic process in
Fig. 14
is quick with about a 0.3 second response time under the two jump conditions. Under the SSP mode as shown in
Fig.15
, the two inductor currents become stable again after about a 0.2 second response time. During this period, the two output capacitor voltages do not change greatly.
Additionally, the dynamic voltagebalance process between
C
_{1}
and
C
_{2}
when the converter operates under the ISP mode when
U
_{in1}
with 48V, is presented in
Fig.16
, in which the voltagebalance loop shown in
Fig.6
is first not added and then added, and finally removed. It can be seen from
Fig.16
that when the voltagebalance loop is not added, there is about a 5V voltage difference between
U
_{C1}
and
U
_{C2}
, where
U
_{C1}
is 195V and
U
_{C2}
is 200V. In addition,
d
_{1}
is equal to
d
_{2}
with the value 0.788. However, when the voltagebalance loop is added,
U
_{C1}
and
U
_{C2}
are both balanced with the same voltage 200V. In addition,
d
_{1}
is 0.797 and
d
_{2}
is 0.789 with a very small dutycycle difference 0.008, which strongly supports (26). Furthermore, steady state and dynamic experimental results verify that the voltagebalance loop does not affect the voltagecurrent loop of the converter.
Dynamic voltagebalance process between C_{1} and C_{2} under ISP mode with U_{in1} 48V.
 C. Efficiency Analysis
In the end, the conversion efficiency curve versus the input voltage for the DITLB converter under both the ISP mode and the SSP mode with different input voltages are presented in
Fig. 17
. For the ISP mode, the conversion efficiency curve is presented with the black line in
Fig. 17
when input source 2 increases by 4V. For the SSP mode, the conversion efficiency curve is plotted with the blue line when the two input sources increase by 4V. Under the ISP mode, the maximum efficiency is 94.4% and the minimum efficiency is 90.1%. In addition, under the SSP mode, the maximum efficiency is 95.0% and the minimum efficiency is 90.2%. It can be concluded that as the input voltage increases, the conversion efficiency increases a little. When input voltage increases with a stable output voltage and a stable output power, the input current decreases. This reduces the conduction losses of the IGBTs and the power diodes.
Efficiency curves under ISP and SSP modes.
Based on all of the experimental results, the operating principle analysis and the performance analysis for the proposed converter are correct and the closedloop control strategy together with the voltagebalance control loop are feasible.
VI. CONCLUSION
This paper introduces a new interleaved DITLB converter, which can operate under both the ISP and SSP modes. The input current ripple is small since the converter can operate with an interleaved control scheme. The output capacitor voltages can be easily balanced by a simple voltagebalance control loop under the ISP mode. Under the SSP mode, the two output capacitor voltages are controlled to be equal since they are independently controlled by two voltagecurrent loops with the same referring capacitor voltage. Experimental results verify the effectiveness and feasibility of the proposed DITLB converter.
Acknowledgements
This work was supported by Fundamental Research Funds for the Central Universities, China, under Grant CDJXS12151109.
BIO
Jianfei Chen was born in China, in 1987. He received his B.S. degree from the Department of Electronic Information, Science, and Technology, Chongqing Normal University, Chongqing, China, in 2011. He is presently working towards his combined M.S. and Ph.D. degrees in the School of Electrical Engineering, Chongqing University, Chongqing, China. From January 2015 to March 2016, he was a guest Ph.D. student in Department of Energy Technology, Aalborg University, Aalborg, Denmark. His current research interests include multilevel dcdc converters and multilevel dcac converters.
Shiying Hou was born in China, in 1962. She received her B.S., M.S., and Ph.D. degrees from the Department of Electrical Engineering, Chongqing University, Chongqing, China, in 1982, 1999, and 2008, respectively. She is presently working as a Professor at the Department of Electrical Engineering, Chongqing University. Her current research interests include control theory and its applications, power electronic technology in power systems, and renewable energy gridgeneration.
Tao Sun was born in China, in 1975. He received his B.S. degree from the Department of Industrial Electrical Automation, Xi'an Petroleum University, Xi’an, China, in 1995; his M.S. degree from the Department of Automatic Control Theory and Applications, Sichuan University, Chengdu, China, in 1998; and his Ph.D. degree from the School of Electrical Engineering, Chongqing University, Chongqing, China, in 2005. In 2009, he was awarded the title of Associate Professor. His current research interests include automatic control and power converters.
Fujin Deng received his B.S. degree in Electrical Engineering from the China University of Mining and Technology, Jiangsu, China, in 2005; his M.S. Degree in Electrical Engineering from the Shanghai Jiao Tong University, Shanghai, China, in 2008; and his Ph.D. degree in Energy Technology from the Department of Energy Technology, Aalborg University, Aalborg, Denmark, in 2012. From 2013 to 2015, he was a Postdoctoral Researcher in the Department of Energy Technology, Aalborg University. He is presently working as an Assistant Professor in the Department of Energy Technology, Aalborg University. His current research interests include wind power generation, multilevel converters, DC grids, highvoltage directcurrent (HVDC) technologies, and offshore wind farmpower system dynamics.
Zhe Chen received his B.S. and M.S. degrees from the Northeast China Institute of Electric Power Engineering, Jilin, China; and his Ph.D. degree from the University of Durham, Durham, England, U.K. He is presently working as a Full Professor in the Department of Energy Technology, Aalborg University, Aalborg, Denmark, where he is the Leader of the Wind Power System Research Program. He is a Danish Principle Investigator of Wind Energy of the SinoDanish Centre for Education and Research. His current research interests include power systems, power electronics, electric machines, wind energy, and modern power systems. He has authored or coauthored more than 320 publications in his field. Dr. Chen is an Associate Editor (Renewable Energy) of the IEEE Transactions on Power Electronics, a Fellow of the Institution of Engineering and Technology, London, England, U.K., and a Chartered Engineer in the U.K.
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