A digital selfsustained phase shift modulation (DSSPSM) strategy that allows for good soft switching and dynamic response performance in the presence of step variations is presented in this paper. The working principle, soft switching characteristics, and voltage gain formulae of a LLC converter with DSSPSM have been provided separately. Furthermore, the method for realizing DSSPSM is proposed. Specifically, some key components of the proposed DSSPSM are carefully investigated, including a parameter variation analysis, the startup process, and the zerocrossing capture of the resonant current. The simulation and experiment results verify the feasibility of the proposed control method. It is observed that the zero voltage switching of the switches and the zero current switching of the rectifier diodes can be easily realized in presence of step load variations.
I. INTRODUCTION
The travelingwave tube (TWT) microwave transmitter has a wide bandwidth and a high gain, and it can be used for various applications, including communications, radar, electronic countermeasures, and space applications. The power converter is one of the key modules of the microwave transmitter, which is used to power the TWT. With the development of modern microwave systems, some parameter criterions of TWT power converters are gradually increasing, including the efficiency, power density, and dynamic response
[1]

[3]
. Resonant converter topologies are usually adopted to meet the high efficiency requirements of the TWT power converter, such as the parallel resonant converter, LCC resonant converter, and fullbridge phaseshift converter
[4]
,
[5]
. Moreover, the LLC resonant converter has been attracting more and more attention due to its inherent merits, including high efficiency, high power density, soft switching, and low EMI
[6]

[10]
. Therefore, the LLC converter is a preferred candidate for microwave transmitters.
The TWT is a special load for a power converter. The TWT load is prone to sudden and repeated changes with the pulse modulation of pulsed microwave transmitters. Considering these step load variations, the power converter should possess good dynamic response and soft switching characteristics. At present, the power converter has not been widely studied in the context of such step load variations, especially with respect to transient soft switching. To overcome these drawbacks, the converter topology should be improved, and a novel applicable control strategy should be developed
[11]

[14]
.
Selfsustained phase shift modulation (SSPSM) has been proposed for resonant converters in
[15]
and
[16]
. This control scheme is inspired by a timing signal from the resonant current. In this manner, the control system is insensitive to parameter uncertainties, and the gate pulses of the switches can be changed adaptively according to the operating conditions. Unlike the conventional frequency modulation (FM) control, SSPSM has much smaller frequency variation range
[15]
, which makes it easy to optimize the magnetic components and to realize miniaturization. Unlike the conventional phase shift modulation (PSM) control, SSPSM can improve soft switching in a wide operation range, which can achieve a higher efficiency
[15]
.
There has been considerable research on SSPSM
[16]

[18]
. The working principle and design method of a fullbridge LCC converter under SSPSM have been presented in
[15]

[17]
. The slidingmode control of a fullbridge LCC converter under SSPSM has been introduced in
[18]
. These references mainly concentrate on the basic working principles of fullbridge LCC converters under SSPSM, in which the characteristics of SSPSM associated with the parameter variations have not been widely analyzed. In addition, in these references, the SSPSM is realized by analog circuits, which are quite complicated, and some of their control functions are difficult to implement. For example, the loop for adaptively compensating the sawtooth wave is difficult to achieve. Consequently, digital selfsustained phase shift modulation (DSSPSM) used for other novel converter topologies in the presence of parameter variations needs to be investigated further.
The major contribution of this paper is the design and development of a novel DSSPSM control strategy. Some new technical factors of DSSPSM, which are used for LLC converters in the presence of the step load variations have been proposed. First, the working principle of a LLC converter with DSSPSM is discussed, which provides new insights into the improvement of the soft switching and dynamic response characteristics of LLC converters. Second, the parameter design method of DSSPSM is presented, which is used to implement the soft switching. Third, a concrete realization method of DSSPSM is elaborated, especially in applications associated with parameter variations. Finally, the transient soft switching of the resonant converter is analyzed and evaluated.
The rest of this paper is organized as follows. The full bridge LLC resonant converter is discussed under DSSPSM in Section II. After that, the hardware and software realization of the DSSPSM is presented in Section III. Then, the key parts of the DSSPSM design are elaborated upon in Section IV. Simulation and experimental results are given in Section V. Finally, some concluding remarks are provided in Section VI.
II. FULL BRIDGE LLC RESONANT CONVERTER UNDER DSSPSM
 A. Circuit Analysis
Fig. 1
shows a schematic of the proposed fullbridge LLC converter with a voltage multiplier rectifier under DSSPSM. The switch pairs
Q
_{1}
and
Q
_{2}
as well as
Q
_{3}
and
Q
_{4}
form the fullbridge inverter. The resonant inductor
L
_{r}
, transformer magnetic inductor
L
_{m}
, and resonant capacitor
C
_{r}
form the LLC resonant tank. The diodes
D
_{5}
and
D
_{6}
, and the capacitors
C
_{5}
and
C
_{6}
form the symmetrical multiplier rectifier. The DSSPSM and proportional plus integral (PI) control are adopted to implement the feedback control.
Schematic of the proposed fullbridge LLC converter.
The main features of the proposed converter can be summarized as follows.
1) Because the phaseshifting angle is the main control variable to regulate converters under DSSPSM, the switching frequency of a converter with DSSPSM has minimalistic variance, which can optimize the magnetic components and passive filters with respect to the volume and losses
[15]
.
2) The timing signal of DSSPSM is derived from the resonant current, which can form a control loop. In this way, the control scheme can eliminate the sensitivity to parameter variations, and the control system can compensate for variations.
3) The control scheme can ensure that the resonant current
i_{L}
_{r}
lags behind the inverter output voltage
v
_{ab}
under any operating condition to realize zero voltage switching (ZVS) of the switches by adjusting the shiftingphase angle, which results in increased efficiency and improved reliability. In addition, zero current switching (ZCS) of the rectifier diodes can be easy to realize under DSSPSM.
4) A symmetrical voltage multiplier rectifier is proposed, which benefits the realization of a highvoltage output and miniaturization of power converters.
 B. Working Principle
Fig. 2
shows the working principle of the proposed DSSPSM.
γ
_{a}
is the phase angle between the reverse resonant current –
i_{L}
_{r}
and drainsource voltage
v
_{ao}
of
Q
_{2}
, and
γ
_{b}
is the phase angle between the resonant current
i_{L}
_{r}
and drainsource voltage
v
_{bo}
of
Q
_{4}
. The sawtooth wave
v
_{st}
is a modulation wave, whose amplitude should be almost constant.
v
_{ca}
and
v
_{cb}
are two modulation lines;
v
_{ca}
is the upper modulation line,
v
_{cb}
is the lower modulation line, and
v
_{ca}
≥
v
_{cb}
. If the gradient
k
of
v
_{st}
is assumed to be constant,
v
_{ca}
and
v
_{cb}
can be described by the following functions,
v
_{ca}
=
kγ
_{a}
and
v
_{cb}
=
kγ
_{b}
. Usually,
v
_{ca}
is kept constant, and
v
_{cb}
is used as the control variable to regulate the converter.
Working principle of DSSPSM.
Fig. 3
shows typical waveforms of a LLC converter under DSSPSM. In terms of the timing diagrams, there are ten switching modes in a complete switching cycle, and the resonance mode between two components (
L
_{r}
and
C
_{r}
) and the resonance mode between three components (
L
_{r}
,
L
_{m}
and
C
_{r}
) are involved.
i_{L}
_{r}
is the resonant current, and
i_{L}
_{m}
is the magnetizing current. When
i_{L}
_{r}
>
i_{L}
_{m}
, the two component resonance occurs. When
i_{L}
_{r}
=
i_{L}
_{m}
, the three component resonance occurs. The starting moment of the two component resonance (the stopping moment of the three component resonance) corresponds to the time when the switches are turned on or off, such as the times
t
_{0}
and
t
_{2}
. The stopping moment of the two component resonance (the starting moment of the three component resonance) is not related to the time that the switches are turned on and off, such as the times
t
_{1}
and
t
_{3}
. The energy of the resonant tank is sent to the load by the form (
i_{L}
_{r}
–
i_{L}
_{m}
).
Typical waveforms of LLC converter under DSSPSM.
 C. SoftSwitching Analysis
1) ZVS Analysis of the Switches:
In order to realize ZVS of the switches, according to
Fig. 2
, the polarity of the resonant current
i_{L}
_{r}
should be kept in the dead time
T
_{d}
between
Q
_{1}
&
Q
_{2}
or
Q
_{3}
&
Q
_{4}
, and the limited condition is given by:
The function can be further expressed as:
where,
f_{s}
is the switching frequency, and
V
_{p}
is the amplitude of the sawtooth wave
v
_{st}
.
Function (2) can be realized by selecting suitable parameters. In this situation, the resonant current
i_{L}
_{r}
lags behind the inverter output voltage
v
_{ab}
, and the zero crossing points of the resonant current are within the inverter output voltage pulse
v
_{ab}
. When one switch is turned on, the resonant current flows through the antiparallel body diode of this switch, and then its drainsource voltage is clamped to zero. In this case, ZVS can be implemented.
2) ZCS Analysis of the Rectifier Diodes:
Under DSSPSM, if
γ
_{a}
–
γ
_{b}
> 0, the period where
v
_{ab}
= 0 is certain to exit in one switch cycle. In
Fig. 2
,
T
_{z}
represents the period where
v
_{ab}
= 0. At the beginning of
v
_{ab}
= 0 (such as the moment
t_{c}
in
Fig. 2
), if
i_{L}
_{r}
=
i_{L}
_{m}
, the converter enters into the three component resonance. If
i_{L}
_{r}
>
i_{L}
_{m}
, the load power is supplied by the LC (
L
_{r}
and
C
_{r}
) resonant tank, the resonant current
i_{L}
_{r}
decreases fast, and soon
i_{L}
_{r}
=
i_{L}
_{m}
.
T
_{r}
represents this decreasing period. If
T
_{z}
>
T
_{r}
, the converter will enter into the threecomponent resonance.
In order to realize ZCS of the rectifier diodes, the three component resonance should always exist in one switch cycle, and the limited condition is given by:
The function can be further expressed as:
Function (4) can be realized by selecting suitable parameters. In this situation, all of the rectifier diodes are switched off with zero current. This reduces the reverse recovery losses of the diodes, which contributes to increased efficiency.
 D. Modeling Analysis
In order to guide the circuit analysis and parameter design, based on the First Harmonic Approximation (FHA) method
[19]
,
[20]
, a LLC converter model under DSSPSM is built.
The fundamental component
v
_{ab1}
of the inverter output voltage
v
_{ab}
can be expressed as:
The effective value
v
_{ab1}
of
v
_{ab1}
is described as:
The symmetrical multiplier rectifier can be simplified as
Fig. 4
(a). The fundamental component
v
_{s1}
of the inverter voltage
v
_{s}
can be expressed as:
The RMS value (
V
_{s1}
) of
v
_{s1}
is described as:
The fundamental component
i
_{s1}
of the inverter current
i
_{s}
can be expressed as:
The equivalent reflected impedance
R
_{eq}
of the multiplier rectifier can be derived as:
Through the above analysis, the equivalent circuit of the LLC converter can be shown as
Fig. 4
(b).
Equivalent circuit of the LLC converter. (a) Symmetrical multiplier rectifier. (b) Equivalent circuit of the LLC converter.
The equivalent reflected impedance
R
_{ac}
on the primary side of the transformer can be expressed as:
The open loop transfer function of the LLC resonant tank can be given as:
Considering (6), (8), and (12), the DC gain of the resonant tank can be obtained as:
The DC gain of the LLC converter can be expressed as:
where:
According to (15), the voltage gain curves of a fullbridge LLC converter with DSSPSM are plotted, as shown in
Fig. 5
. According to this figure, the voltage gain
M
increases with respect to the increase in phase
γ
_{b}
. By controlling the phase
γ
_{b}
,
v
_{cb}
is controlled, and the converter can be regulated. In addition, when the frequency ratio
F
decreases, the phase
γ
_{b}
varies little with the same gain change, and the gain range becomes wide, as shown in
Fig. 5
(a). When the quality factor
Q
increases, the voltage gain
M
becomes small, as shown in
Fig. 5
(b).
Voltage gain curves versus γ_{b}. (a) Q =0.3, γ_{a}=0.9π, n=1, k=4. (b) F=0.9, γ_{a}=0.9π, n=1, k=4).
III. REALIZATION OF DSSPSM
 A. Hardware Realization
Fig. 6
shows a hardware realization schematic of DSSPSM.
Fig. 7
illustrates the main waveforms of DSSPSM based on a DSP. A DSP board by Texas Instruments (TMS320F2812) is primarily used to implement the control scheme. The general timer of the DSP event manager is set to the continuous incremental mode, and is used to generate the sawtooth wave
v
_{st}
. The comparison unit registers CMPR1 and CMPR2 separately represent the modulation lines
v
_{ca}
and
v
_{cb}
. The logic signals
v
_{r1}
and
v
_{r2}
are separately obtained by comparing
v
_{st}
with
v
_{ca}
and
v
_{cb}
. The zerocrossing moment of the resonant current can be captured by the DSP, and then the signal
v
_{r3}
can be easily generated.
Hardware schematic of DSSPSM.
Main waveforms of DSSPSM based on DSP.
In
Fig. 6
, the logic signals
v
_{r1}
,
v
_{r2}
, and
v
_{r3}
can be converted to the drive signals L
Q
_{1}
–L
Q
_{4}
, through the logic operations of NOT gate, NAND gate, and RS flipflop. After that, the deadtime of L
Q
_{1}
L
Q
_{4}
is generated by the RCD circuit. Lastly, two drive chips Si8235 are used to drive the switches.
 B. Software Realization
Fig. 8
shows software realization flowcharts of DSSPSM. The software is mainly composed of the main program and the interrupt programs, and the interrupt programs consist of the capture interrupt, the timerunderflow interrupt, and the analogtodigital conversion (ADC) interrupt.
Software flowcharts of DSSPSM. (a) Main program. (b) Capture interrupt program. (c) ADC interrupt program.
Fig. 8
(a) shows the main program flowchart. The program initialization is carried out first, and then the main program waits to respond to the interrupt flags.
Fig. 8
(b) shows a capture interrupt program flowchart. The capture interrupt is stimulated at the zerocrossing moment of the resonant current. The zerocrossing moment can be captured, and the zerocrossing period can be calculated. If the captured period belongs to the predetermined scope, the timer counter returns to zero. If the captured period does not belong to the predetermined scope, the timer period register is updated.
The program flowchart of the timer underflow interrupt is relatively simple. The timer underflow interrupt is stimulated when the timer counter becomes zero. The zerocrossing square wave
v
_{r3}
is generated in this program, and then the ADC converter is stimulated by the timer underflow interrupt flag.
Fig. 8
(c) shows an ADC interrupt program flowchart. The ADC interrupt is stimulated by the ADC flag. After the sampled value is obtained, the feedback control signal can be calculated by the digital position PI control algorithm, and then the comparison register CMPR2 is updated by the feedback control value.
IV. KEY PARTS OF DSSPSM DESIGN
 A. DSSPSM Design Regarding Parameter Variations
Parameter variations of the converter, such as step load variations, introduce some problems to the DSSPSM design. For instance, the sawtooth wave may have distortions.
Fig. 9
shows simulation results of the sawtooth wave when the load is changed repeatedly between 600 Ω and 1200 Ω every 2.5 ms. It can be seen that the amplitude of the sawtooth wave begins to change at the load change moment. This phenomenon may lead to some mistakes, and some measures should be taken.
Simulation results of sawtooth wave changes with respect to step load variations.
Fig. 10
shows two concrete mistakes associated with the sawtooth wave of DSSPSM.
Concrete mistakes of sawtooth wave of DSSPSM ((a) The first mistake and (b) The second mistake).
As shown in
Fig. 10
(a), during the period
T
_{1}
(
k
+1), for the zerocrossing moment of the resonant current advances, the captured zerocrossing period
T
_{1}
(
k
+1) is less than the normal value
T
_{1}
(
k
), and the amplitude
V
_{p1}
of the sawtooth wave is less than the normal amplitude
T
_{PR}
of the sawtooth wave
v
_{st}
in the period
T
_{1}
(
k
+1). In this situation, if the modulation line
v
_{ca}
is larger than the amplitude
V
_{p1}
, the logic signal
v
_{r1}
cannot be obtained in the correct manner. As a result, the gate pulses of the switches will be wrong.
As shown in
Fig. 10
(b), during the period
T
_{2}
(
k
+1), for the zerocrossing moment of the resonant current delays, the captured zerocrossing period
T
_{2}
(
k
+1) is larger than the normal value
T
_{2}
(
k
), and two sawtooth waves will appear in the period
T
_{2}
(
k
+1). In this situation, the logic signal
v
_{r3}
will be wrong. In addition, if the amplitude
V
_{p2}
of the second sawtooth wave in the period
T
_{2}
(
k
+1) is larger than the modulation line
v
_{cb}
, the logic signal
v
_{r2}
can not be obtained in the correct manner. As a result, the gate pulses of the switches will be wrong.
In order to fix the two mistakes shown in
Fig. 10
, some measures should be taken.
1) For the mistake shown in
Fig. 10
(a), the parameter variations should be taken into consideration when selecting the value of
v
_{ca}
. The value of
v
_{ca}
should be always less than the normal amplitude
T
_{PR}
of the sawtooth wave
v
_{st}
. Moreover, if the captured amplitude
V
_{p1}
is less than
v
_{ca}
, the value of
v
_{ca}
should be immediately updated as:
2) For the mistake shown in
Fig. 10
(b), if the captured zerocrossing period
T
_{2}
(
k
+1) is larger than the normal value
T
_{2}
(
k
), the value of
T
_{PR}
should be immediately updated as:
 B. StartUp Process
There are several situations that warrant consideration in the startup process.
1) The resonant current may not be regular and stable in the startup process, and DSSPSM may become unreliable.
2) A sudden poweron may impact the converter hardware, so soft starting should be realized.
In order to solve these two problems, following measures should be taken.
1) In the startup period, the traditional phase shift control is adopted first. When the converter becomes stable, the DSSPSM control begins to work.
2) The control signal
v
_{cb}
varies slowly from zero to a predetermined value, and the pulse width of the inverter output voltage
v
_{ab}
becomes gradually wider. In this way, soft starting can be realized.
 C. ZeroCrossing Capture
Zerocrossing capture is a vital part of the DSSPSM design. If the zerocrossing moment cannot be correctly captured, DSSPSM may not work.
Fig. 11
shows the zerocrossing detection circuit. A halleffect current sensor TBC06DS3.3 is adopted to sample the resonant current, and the zerocrossing squarewave of the resonant current is obtained through an ultrafast comparator LT1720. However, the rising edge and falling edge of the squarewave may have some chattering. Therefore, the figuration function of this squarewave needs to be achieved through a RC filter and NOT gate 74LS14. In this way, the zerocrossing signal can be obtained in a correct manner, and sent to the capture port of the DSP.
Zerocrossing detection circuit.
V. SIMULATION AND EXPERIMENTAL RESULTS
 A. Simulation Results
In order to evaluate the performance of the proposed DSSPSM control strategy, some simulation results are presented in this section. The simulations are carried out with MATLAB/SIMULINK software.
The simulation and experiment are carried out on a LLC resonant converter with an input voltage of 270 V. The resonant frequency is set to 115 kHz with a
L
_{r}
of 104 μH and a
C
_{r}
of 20 nF. The magnetic inductor
L
_{m}
is set to 416 μH. Thus,
L
_{r}
/
L
_{m}
is 4. The main parameters of the designed converter are shown in
Table I
.
CONVERTER PARAMETERS
Fig. 12
shows typical simulation waveforms of DSSPSM, including the resonant current
i_{L}
_{r}
, the sawtooth wave
v
_{st}
, the drainsource voltage
v
_{ao}
of the switch
Q
_{2}
, the drainsource voltage
v
_{bo}
of the switch
Q
_{4}
, and the inverter output voltage
v
_{ab}
. As can be seen, the simulation results are in accordance with the theoretical analysis.
Typical simulation waveforms of DSSPSM.
Fig. 13
shows a simulation waveform of the output voltage
v
_{o}
with respect to step load variations. The load resistance is changed between 600 Ω and 1200 Ω every 2.5 ms. As can be seen, the output voltage
v
_{o}
has a little ripple against the step load changes, and the converter stays stable during the entire process.
Simulation waveform of output voltage v_{o} with respect to step load variations.
Fig. 14
shows simulation waveforms of the resonant current
i_{L}
_{r}
and inverter output voltage
v
_{ab}
in the presence of step load variations. As can be seen,
i_{L}
_{r}
is kept lagging behind
v
_{ab}
when the load resistance becomes larger or smaller. In this situation, when one switch is turned on, the resonant current flows through the antiparallel body diode and the drainsource voltage is clamped to zero. Then the ZVS can be realized.
Simulation waveforms of resonant current i_{L}_{r} and inverter output voltage v_{ab} with respect to step load variations ((a) From 600 Ω to 1200 Ω and (b) From 1200 Ω to 600 Ω).
 B. Experimental Results
In order to investigate the performance of the proposed DSSPSM control strategy, a laboratory prototype has been built, as shown in
Fig. 15
. The parameters of the converter are listed in
Table I
.
Laboratory prototype.
1) Steady State Performance:
Fig. 16
shows experimental waveforms of the resonant current
i_{L}
_{r}
and zerocrossing square signal
v
_{r3}
at a full load. As can be observed, there is no chattering in the rising edge or falling edge of
v
_{r3}
, and the zerocrossing moment can be correctly captured by the DSP.
Experimental waveforms of resonant current i_{L}_{r} and zerocrossing square wave v_{r3}.
Fig. 17
shows experimental waveforms of the resonant current
i_{L}
_{r}
and inverter output voltage
v
_{ab}
at a full load, half load and light load (10% load). As can be seen, under different load conditions,
i_{L}
_{r}
can lag behind
v
_{ab}
, and all of the switches can implement ZVS which reduces the switching losses of the switches.
Experimental waveforms of resonant current i_{L}_{r} and inverter output voltage v_{ab} ((a) Full load, (b) Half load and (c) Light load (10% load)).
Fig. 18
shows experimental current waveforms of the rectifier diodes
D
_{5}
and
D
_{6}
at a full load, half load, and light load (10% load). All of the rectifier diodes can implement ZCS which reduces the reverse recovery losses of the rectifier diodes.
Experimental current waveforms of the rectifier diodes D_{5} and D_{6} ((a) Full load, (b) Half load and (c) Light load (10% load)).
2) Dynamic State Performance:
Fig. 19
shows transient waveforms of the reverse resonant current 
i_{L}
_{r}
and inverter output voltage
v
_{ab}
under the conventional PSM in the presence of of step load variations. As can be seen, the current
i_{L}
_{r}
cannot keep lagging behind the voltage
v
_{ab}
, and sometimes the soft switching characteristic of the converter is not so good for the step load variations.
Transient waveforms under PSM for the step load variations.
Fig. 20
shows transient waveforms of the resonant current
i_{L}
_{r}
, inverter output voltage
v
_{ab}
and output voltage
v
_{o}
under DSSPSM in the presence of step load variations.
Fig. 20
(a) shows waveforms when the load resistance increases.
Fig. 20
(b) shows waveforms when the load resistance decreases. The load resistance is changed between 600 Ω and 1200 Ω, and the load changing transition time is less than 200 ns.
Transient waveforms under DSSPSM for the step load variations ((a) From 600 Ω to 1200 Ω and (b) From 1200 Ω to 600 Ω).
As can be seen,
i_{L}
_{r}
is kept lagging behind
v
_{ab}
for step load variations, and ZVS can always be implemented. In addition, the converter has good dynamic performance, and the output voltage
v
_{o}
can be tightly regulated at 550 V. The response time is less than 150 μs, and the output voltage overshoot and undershoot are less than 1% of 550 V.
3) Efficiency Analysis:
Fig. 21
shows an efficiency curve according to the load. The figure indicates that the efficiencies under different load conditions are higher than 92%, and their variance is minimalistic. The soft switching of the LLC converter with DSSPSM can be realized under different load conditions leading to an improved efficiency in a wide operation range.
Efficiency curve according to load.
VI. CONCLUSION
In this paper, a novel DSSPSM control strategy is proposed, and a full bridge LLC resonant converter with a multiplier rectifier under DSSPSM is introduced. The working principle, softswitching characteristic, and realization procedure of DSSPSM are separately analyzed. Simulation and experimental results validate that the proposed LLC converter under DSSPSM has a good dynamic performance and soft switching characteristics in presence of the step load variations. Therefore, the proposed DSSPSM control strategy is valuable for improving the efficiency and power density of power converters. In addition, a simulated resistance load is used to represent a TWT in the simulation and experiment, which makes it easy to test the steadystate and dynamicstate performance of DSSPSM. In future work, the practical application of DSSPSM in TWT microwave transmitters will be explored.
BIO
Kai Zheng was born in Henan Province, China. He received his B.S. and M.S. degrees in Electrical Engineering from the New Star Research Institute of Applied Technology, Hefei, China, in 2005 and 2009, respectively. He is presently working toward his Ph.D. degree in Electrical Engineering at the Zhengzhou Information Science and Technology Institute, Zhengzhou, China. His current research interests include the modeling and control of resonant power converters.
Dongfang Zhou was born in Zhejiang Province, China. He received his B.S. degree in Electrical Engineering from the Zhengzhou Information Science and Technology Institute, Zhengzhou, China, in 1983; his M.S. degree in Electrical Engineering from Xidian University, Xi’an, China, in 1989; and his Ph.D. degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2005. He is presently working as a Professor in the Zhengzhou Information Science and Technology Institute. His current research interests include power electronics and the control of microwave systems.
Jianbing Li was born in Hubei Province, China. He received his B.S., M.S. and Ph.D. degrees in Electrical Engineering from the Zhengzhou Information Science and Technology Institute, Zhengzhou, China, in 1999, 2002 and 2006, respectively. He is presently working as an Associate Professor in the Zhengzhou Information Science and Technology Institute. His current research interests include power electronics and control.
Li Li was born in Henan Province, China. She received her B.S. degree in Electrical Engineering from the North China University of Water Resources and Electric Power, Zhengzhou, China, in 2012. She is presently working towards her M.S. degree in Electrical Engineering at the Zhengzhou Information Science and Technology Institute, Zhengzhou, China. Her current research interests include the topologies and control of power converters.
Yujing Zhao was born in Henan Province, China. He received his B.S. degree in Electrical Engineering from Tianjin University, Tianjin, China, in 2012. He is presently working towards his M.S. degree in Electrical Engineering at the Zhengzhou Information Science and Technology Institute, Zhengzhou, China. His current research interests include the topologies and control of power converters.
Bijeev N. V.
,
Malhotra A.
,
Kumar V.
“Design and realization challenges of power supplies for space TWT,”
in Proc. IEEE Vacuum Electronics Conference
2011
431 
432
Barbi I.
,
Gules R.
2003
“Isolated DCDC converters with highoutput voltage for TWTA Telecommunication Satellite Applications,”
IEEE Trans. Power Electron.
18
(4)
975 
984
DOI : 10.1109/TPEL.2003.813762
Springmann D.
,
Chan D.
,
Schoemehl T.
“A 50W Kaband NanoMPM,”
in Proc. IEEE Vacuum Electronics Conference
2014
123 
124
Singh A. K.
,
Das P.
,
Pahlevaninezhad M.
“A novel high output voltage DCDC LLC resonant converter with symmetric voltage quadrupler rectifier for RF communications,”
in Proc. IEEE Telecommunications Energy Conference
2014
1 
6
Zhang G.
,
Zhou D.
,
Yang L.
2013
“Development of novel type of twostage high voltage converter,”
Chinese Journal of Vacuum Science and Technology
33
(5)
419 
425
Yang B.
,
Ph.D. Dissertation
2003
“Topology investigation for front end DC/DC power conversion for distributed power system,”
Virgina Polytechnic Institute and State University
USA
Ph.D. Dissertation
Beiranvand R.
,
Rashidian B.
,
Zolghadri M.R.
,
Alavi S. M. H.
2012
“A design procedure for optimizing the LLC resonant converter as a wide output range voltage source,”
IEEE Trans. Power Electron.
27
(8)
3749 
3763
DOI : 10.1109/TPEL.2012.2187801
Feng W.
,
Lee F. C.
,
Mattavelli P.
2013
“Simplified optimal trajectory control (SOTC) for LLC resonant converters,”
IEEE Trans. Power Electron.
28
(5)
2415 
2426
DOI : 10.1109/TPEL.2012.2212213
Li X. D.
2014
“LLCtype dualbridge resonant converter: Analysis, design, simulation, and experimental results,”
IEEE Trans. Power Electron.
29
(8)
4313 
4321
DOI : 10.1109/TPEL.2013.2291207
Zhao Y.
,
Xiang X.
,
Li W.
,
He X.
2013
“Advanced symmetrical voltage quadrupler rectifiers for high stepup and high outputvoltage Converters,”
IEEE Trans. Power Electron.
28
(4)
1622 
1631
DOI : 10.1109/TPEL.2012.2211108
Pan H.
,
He C.
,
Ajmal F.
2014
“Pulsewidth modulation control strategy for high efficiency LLC resonant converter with light load applications,”
IET Power Electron.
7
(11)
2887 
2894
DOI : 10.1049/ietpel.2013.0846
Shafiei N.
,
Ordonez M.
,
Cracium M.
,
Edington M.
“High power LLC battery charger: Wide regulation using phaseshift for recovery mode,”
in Proc. IEEE Energy Conversion Congress and Exposition
2014
2037 
2042
Sun X. F.
,
Shen Y. F.
,
Zhu Y.
,
Guo X.
2015
“Interleaved boostintegrated LLC resonant converter with fixedfrequency PWM control for renewable energy generation applications,”
IEEE Trans. Power Electron.
30
(8)
4312 
4326
DOI : 10.1109/TPEL.2014.2358453
Buccella C.
,
Cecati C.
,
Latafat H.
,
Pape P.
2015
“Observerbased control of LLC DC/DC resonant converter using extended describing functions,”
IEEE Trans. Power Electron.
30
(10)
5881 
5891
DOI : 10.1109/TPEL.2014.2371137
Mohamed Z. Y.
,
Praveen K. J.
“A review and performance evaluation of control Techniques in resonant converters,”
in Proc. IEEE Industrial Electronics Society
2004
215 
221
Mohamed Z. Y.
,
Humberto P.
,
Praveen K. J.
2006
“Selfsustained phase shift modulated resonant converters: Modeling, design, and performance,”
IEEE Trans. Power Electron.
21
(2)
401 
414
DOI : 10.1109/TPEL.2005.869751
Mohamed Z. Y.
,
Ph. D. Dissertation
2005
“Control and modeling of high frequency resonant DC/DC converters for powering the next generation microprocessors,”
Queen’s University
Canada
Ph. D. Dissertation
Jorge L. S.
,
Miguel C.
,
Jaume M.
2009
“Modeling and performance analysis of the DC/DC series–parallel resonant converter operating with discrete selfsustained phaseshift modulation technique,”
IEEE Trans. Ind. Electron.
55
(3)
697 
705
Fang X.
,
Hu H.
,
Shen J.
,
Batarseh I.
2012
“Operation mode analysis and peak gain approximation of the LLC resonant converter,”
IEEE Trans. Power Electron.
27
(4)
1985 
1995
DOI : 10.1109/TPEL.2011.2168545
Park Y. J.
,
Kim H. J.
,
Chun J. Y.
,
Lee J. Y.
,
Pu Y. G.
,
Lee K. Y.
2007
“A wide frequency range LLC resonant controller IC with a phasedomain resonance deviation prevention circuit for LED backlight units,”
Journal of Power Electronics
15
(4)
861 
875
DOI : 10.6113/JPE.2015.15.4.861