This paper presents a comprehensive analysis of the spurious turnon phenomena in phaseshifted fullbridge (PSFB) converters. The conventional analysis of the spurious turnon phenomenon does not establish in the PSFB converter as realizing zero voltage switching (ZVS). Firstly, a circuit model is proposed taking into account the parasitic capacitors and inductors of the transistors, as well as the parasitic elements of the power circuit loop. Second, an exhaustive investigation into the impact of all these parasitic elements on the spurious turnon is conducted. It has been found that the spurious turnon phenomenon is mainly attributed to the parasitic inductors of the power circuit loop, while the parasitic inductors of the transistors have a weak impact on this phenomenon. In addition, the operation principle of the PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turnon problems. Design guidelines are given based on the theoretical analysis. Finally, detailed simulation and experimental results obtained with a 1.5 kW PSFB converter are given to validate proposed analysis.
I. INTRODUCTION
The phaseshifted fullbridge (PSFB) converter is applied in medium to high power conversions due to its attractive features including a simple circuit, constant operation frequency and ZVSon of the primary switches
[1]

[5]
. This type of converter has been extensively studied in the literature, including modeling, design optimization, control method, flux bias compensation, improved fullbridge topologies, etc.
[6]

[10]
.
Despite all its merits, the PSFB converter has the risk of spurious turnon of the transistors. The interaction between the upper and lower transistors in a bridge leg during a switching transient (crosstalk) can appear. This leads to additional switching losses and overstress of the power devices. With the increased demand for high power density, larger currents and higher switching frequencies are the new trends for power supplies. Under these circumstances, the effects of the circuit parasitic parameters on the converter’s performance are becoming more and more significant
[11]
. As a result, the PSFB converter is becoming more vulnerable to spurious turnon problems.
Actually, the spurious turnon phenomena in power switching converters and has been studied in many works
[12]

[17]
. In these studies, the spurious turnon phenomena are mainly induced by the hard switching of transistors. High dv/dt during fast switching on the transient of one device affects the operating behavior of its complementary device
[12]

[15]
. Meanwhile, the high di/dt induces a negative voltage across the parasitic source inductor of the MOSFET, pulling down its source voltage
[16]
,
[17]
. The parasitic source inductor, the recovery current presented by the body diode, and the parasitic capacitors are thought to be the key elements of the spurious turnon phenomena in hard switching power converters. However, in PSFB converters, ZVS on is achieved and the conventional analysis does not apply here. In addition, the mechanism of the spurious turnon phenomena in PSFB converters has been rarely analyzed comprehensively. Thus, it is very meaningful to conduct studies on phaseshifted fullbridge converters.
In this paper, the switching transition when the spurious turnon phenomenon occurs in a PSFB converter will be specified by an analytical model, which takes into account the parasitic inductors of the power circuit loop, as well as the parasitic capacitors and inductors of the transistors. According to the analysis, the parasitic inductors of the power circuit loop are the key elements of the spurious turnon in PSFB converters, while the parasitic source inductors and the recovery current presented by the body diode have weak impacts on this phenomenon since ZVSon is realized here. Design guidelines for reducing the spurious triggering pulse are then given. At last, a series of simulation and experimental results will be provided to verify the theoretical analysis.
II. SPURIOUS TURNON PHENOMENON
 A. Operation Principle of PSFB Converters
Fig. 1
(a) and (b) show a circuit diagram
[1]
,
[18]
and key waveforms
[18]
,
[19]
of the standard PSFB converter. According to
Fig. 1
(a), a PSFB converter is formed by four transistors Q
_{1}
Q
_{4}
, a power transformer T
_{r}
, a resonant inductor L
_{R}
(including the leakage inductor), output rectifier diodes D
_{R1}
and D
_{R2}
, an output filter inductor L
_{f}
and a capacitor C
_{f}
. Meanwhile, as shown in
Fig. 1
(b), Q
_{3}
and Q
_{4}
are switched on/off before Q
_{1}
and Q
_{2}
. Thus, the Q
_{3}
Q
_{4}
leg is designated as the “leading leg”, while the Q
_{1}
Q
_{2}
leg is designated as the “lagging leg”. The primary current
I
_{p}
reaches its peak value when the transistor of the leading leg is turned off.
PSFB converter topology and key waveforms.
It is well known that ZVS turnon can be achieved by utilizing the energy stored in the resonant inductor L
_{R}
to charge and discharge the parasitic capacitors of MOSFETs
[19]
. The voltage across the draintosource terminals of a MOSFET should be discharged to zero before it is switched on. Meanwhile, the current through the MOSFET decreases to zero. This transition interval (TI), between
t_{b}

t_{2}
, is accomplished during the turn off procedure of the MOSFET as shown in
Fig. 2
[20]
,
[21]
. The voltage across the draintosource terminals of the MOSFET and current through the MOSFET change drastically. For example, the voltage across the draintosource terminals of Q
_{4}
is charged to
V_{in}
and the voltage across the draintosource terminals of Q
_{3}
is discharged to zero during the turnoff procedure of Q
_{4}
. Meanwhile, the drain current of Q
_{4}
decreases to zero during this interval.
Turnoff procedure of MOSFET in PSFB converter.
 B. Spurious TurnOn in Practice
According to the analysis in
[15]
, in the softswitching power converters, during the turnoff transient of the lower switch, the negative spurious voltage induced at the gate–source terminals of the upper switch may overstress the power device if its magnitude exceeds the maximum allowable negative gate voltage that is acceptable to the semiconductor device. For example, when Q
_{4}
is turned off, there is a negative spurious voltage across the gate–source terminals of Q
_{3}
. However, in addition to a negative spurious voltage at the gate–source terminals of the complementary transistor, a positive spurious voltage is observed at the gatesource terminals of the transistors. This is shown in
Fig. 3
, which is directly obtained from a 1.5 kW phaseshifted fullbridge converter. Since the Q
_{1}
Q
_{2}
leg is the lagging leg, Q
_{1}
is still on when Q
_{4}
is turned off and the spurious turnon of Q
_{2}
leads to an interaction between the transistors of the lagging leg (crosstalk).
Spurious turnon of the transistors in lagging leg.
Actually, a positive induced voltage can be observed during every transistor’s turnoff procedure. As shown in
Fig. 3
, when the transistor in a lagging leg, such as Q
_{2}
, is turned off, an oscillation can be observed at the gatetosource terminals of Q
_{4}
. However, the amplitude of the voltage oscillation is much smaller than the positive voltage when the transistor in the leading leg is turned off. A detail analysis and explanations are given in Section III.
III.MECHANISM ANALYSIS AND DESIGN GUIDELINES
 A. Circuit Modeling and Mechanism Analysis
An equivalent circuit model of a PSFB converter is shown in
Fig. 4
. The parasitic elements considered for the transistors are the gatesource capacitance C
_{gs}
, gatedrain capacitance C
_{gd}
, drainsource capacitance C
_{ds}
, internal gate inductor L
_{gin}
, drain inductor L
_{din}
, source inductor L
_{sin}
, and the body diode D. The drain inductor L
_{dcw}
and source inductor L
_{scw}
are the parasitic inductors introduced by the copper wires and the pads of the printed circuit board. In addition, the parasitic inductors of the power circuit loop, L
_{pc1}
, L
_{pc2}
, L
_{pc3}
and L
_{pc4}
, are considered in the proposed equivalent circuit model. It should be noted that the proposed equivalent circuit model is valid only when a PSFB converter has a large power (usually larger than 500W) and is realized within the printed circuit board (PCB). The large power of the converter means bulky capacitors with a large size at the input terminal
[22]
. As a result, the copper lines from the drain node to the input capacitor are long enough to produce parasitic inductors. This can be verified by the layout shown in
Fig. 8
. These parasitic inductors, which are introduced by the copper wires of the power circuit loop, have been neglected in previous analyses since they are not involved in the gate drive loop, as shown in
Fig. 4
, and are thought to be irrelevant in terms of the spurious turnon phenomena. However, the occurrence of crosstalk is mainly induced by the parasitic inductors of the power circuit loop due to the special operation principle of the PSFB converter. Detailed analyses are shown as follows.
Equivalent circuit of a PSFB converter.
Since the oscillation is observed during the turnoff procedure, the converter is analyzed in four different modes, as shown in
Fig. 2
: (1)
Energy transfer and overdrive region
(before
t
_{a}
). (2)
Miller Plateau
(
t
_{a}
~
t
_{b}
). (3)
Transition interval
(
t
_{b}
~
t
_{o}
). (4)
Circulating mode
(after
t
_{o}
). Equivalent circuits of the four operating modes are illustrated in
Fig. 5
. For simplicity, the output stage is not shown in the equivalent circuits.
Equivalent circuits of different operating modes.
Due to the symmetric nature of the two bridge legs, the analysis process for each transistor is similar. Therefore the turnoff procedure of Q
_{4}
is taken as an example. Details of each operation mode are described as follows.
 Mode 1 [Energy transfer, beforeta]
This is an energy transfer mode. The diagonal switches Q
_{1}
and Q
_{4}
were conducting. The primary current flows through the diagonal transistor Q
_{1}
in the lagging leg and the transistor Q
_{4}
in the leading leg. This is shown in
Fig. 5
(a). At
t_{a}
, the primary current reaches its maximum value and can be expressed as
[1]
:
This mode ends when the drain current of Q
_{4}
starts to decrease, which starts at
t_{a}
according to
Fig. 2
.
 Mode 2 [Miller Plateau，tatb]
This stage begins when the gatetosource voltage
V_{gs}
decreases to the Miller Plateau level
V_{miller}
. During this stage, the gatetodrain capacitor C
_{gd}
is charged by the driving current, and the draintosource capacitor C
_{ds}
is charged by the primary current. Although the current through the resonant inductor L
_{R}
is nearly constant, the current through Q
_{4}
(including D
_{4}
and C
_{ds4}
) starts to decrease. This is the beginning of the ZVS procedure.
It should be pointed out that the current through Q
_{4}
changes slightly in this plateau. This is because the driving current is mainly used to discharge the gatetodrain parasitic capacitor. This is not shown in
Fig. 5
.
 Mode 3 [Transition Interval,tb~to]
According to
Fig. 2
, the gatetosource voltage of Q
_{4}
starts to decrease at
t_{b}
. Therefore, the current through the channel of Q
_{4}
decreases drastically. The primary current flows through both of the draintosource parasitic capacitors of Q
_{3}
and Q
_{4}
. Obviously, the current through Q
_{4}
is same as the current through the parasitic inductors L
_{pc1}
, L
_{pc2}
and L
_{pc3}
as shown in
Fig. 5
(b).
where
I_{Lp1}
,
I_{Lp2}
and
I_{Lp3}
are the currents through the parasitic inductors L
_{pc1}
, L
_{pc2}
and L
_{pc3}
.
Therefore, the currents through the parasitic inductors L
_{pc1}
, L
_{pc2}
and L
_{pc3}
decrease drastically. With the decreasing of the current, there is an inductive voltage across the parasitic inductors, which is shown in
Fig. 5
(b). Among them,
V_{Lp1}
can be expressed as:
Similarly, there are inductive voltages across L
_{pc2}
and L
_{pc3}
. The expressions of the two inductive voltages can be deduced as:
The parasitic inductors around the transistor and the gate driver loop can be summarized as:
According to
Fig. 5
(b), during the transition interval, the current through the parasitic inductors around Q
_{2}
remains constant. Therefore, the parasitic inductors of the transistor have a weak influence on the spurious turnon phenomenon of Q
_{2}
. It should be noticed that the current through the parasitic inductors around Q
_{4}
also changes during this interval. An analysis of this has been presented in
[17]
and is not be shown here. More importantly, the inductive voltage across the parasitic inductors of the power circuit loop may lead to the spurious turnon phenomena since the parasitic inductances of the power circuit loop is much larger than the parasitic inductances around the MOSFETs. To be specific, the negative induced voltage across L
_{pc1}
may lead to the spurious turnon phenomenon of Q
_{2}
and the crosstalk of the lagging leg occurs when Q
_{1}
is still on. The negative induced voltage across L
_{pc1}
and L
_{pc2}
may lead to a positive voltage across the gatetosource terminals of Q
_{4}
and increase the switching loss. The negative induced voltage across L
_{pc3}
leads to a positive voltage across the gatetosource terminals of Q
_{1}
. The positive induced voltage of Q
_{1}
has no significant influence unless the voltage amplitude exceeds the maximum tolerant voltage.
In order to obtain the maximum amplitude of the positive induced voltage, the decreasing slope of
I_{Lp1}
is deduced as follows. According to
Fig. 2
, the current decreasing slope changes in
Mode 2
. Therefore, the transition interval can be divided into two stages.
Stage 1 (t_{b}t_{c}):
At the beginning of the transition interval, the primary current keeps flowing using the switch channel and its draintosource parasitic capacitor,
C_{ds4}
. This charges the draintosource parasitic capacitance of Q
_{4}
from essentially zero volts to the upper voltage rail,
V_{in}
. Simultaneously, the draintosource parasitic capacitor of the switch Q
_{3}
is discharged as its source voltage rises from the lower to the upper rail voltage. This resonant transition positions the switch Q
_{3}
with no drain to the source voltage prior to turnon and facilitates lossless, zero voltage switching. This is shown in
Fig. 5
(c).
Therefore, during
Stage 1
, the primary current is equal to the sum of three parts:
I_{c4}
(the current through the channel of Q
_{4}
),
I_{Cds4}
(the current through the draintosource parasitic capacitor of Q
_{4}
) and
I_{Cds3}
(the current through the draintosource parasitic capacitor of Q
_{3}
).
Among them, the voltage transition rates of C
_{ds3}
and C
_{ds4}
are equal, and C
_{ds3}
is equal to C
_{ds4}
since the same type of MOSFETs are adopted. Therefore,
I_{Cds4}
is equal to
I_{Cds3}
according to following equations.
The current through Q
_{4}
can be expressed as:
The relationship between
V_{gs4}
and
I_{c4}
can be deduced as follows.
where
g_{m}
is the transconductance of the MOSFET, and
V_{th}
is the threshold voltage of the MOSFET.
The gate driving current is used to discharge C
_{gs4}
while
V_{gs4}
decreases. It should be noticed that the driving current is used to charge C
_{gd4}
while
V_{gd4}
simultaneously changes.
V_{gs4}
can be expressed as:
where
V_{miller}
is the voltage amplitude of the miller plateau,
I_{dri}
is the driving current, and C
_{gd}
is the parasitic capacitance across the gatetodrain.
Substitute (9) into (8):
Then substitute (9), (10) and (14) into (8), and it can be deduced that:
V_{ds}
can be deduced from (14):
The constants C
_{1}
and C
_{2}
can be evaluated from the initial conditions.
V_{ds4}
is equal to
V_{in}
at
t_{c}
and it is equal to zero at
t_{b}
.
Meanwhile, since the current through L
_{pc1}
is equal to the current through Q
_{4}
, the changing rate of
I_{Lp1}
during
stage 1
can be deduced as:
Substitute (16) into (17). Then the changing rate of
I_{Lp1}
can be deduced. However, the result is too complicated and is not shown here.
This stage ends when the voltage of
V_{ds4}
reaches
V
_{in}
, and the driving current is all applied to discharge C
_{gs}
.
Stage 2 (t_{c}t_{2}):
When the voltage of
V_{ds4}
reaches
V
_{in}
, the primary current continues to flow using the switch and body diode of Q
_{3}
, which is shown in
Fig .5
(c).
Since the driving current is all applied to discharge C
_{gs}
, (13) can be rewritten as:
Substitute (14) into (8):
Then substitute (9), (10) and (19) into (8), and it can be deduced that:
Then the change rate of
I_{Lp1}
during
Stage 2
can be deduced as:
Substitute (17) and (21) into (3), and the inductive voltage across the parasitic inductor L
_{pc1}
can be deduced as:
Since Q
_{1}
is still on, the voltage of the drain node of Q
_{2}
is constant. Thus, the spuriouson voltage of Q
_{2}
can be deduced as
[17]
:
 Mode 3 [Circulating mode，t>t2]
Q
_{4}
is completely turned off and all of the primary current is flowing through D
_{3}
. This is shown in
Fig. 5
(d).
 B. Impact of the Parasitic Elements
According to the above analysis results, the spuriouson voltage is mainly correlated with the value of the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak influence on the spuriouson voltage. In addition, the current change rate is positively correlated with the current amplitude when the transistor is turned off according to (21). Meanwhile, the primary current reaches its peak value when the transistor in the leading leg is turned off, and the transistor in the leading leg is turned off with a much smaller current when the primary current decreases a lot during the circulating mode. The peak value of the primary current has been deduced in (1). The primary current decreases a lot during the circulating mode due to the dc blocking capacitor, which is widely used in PSFB converters to eliminate the flux density bias
[19]
. The current decrease during this mode can be expressed as
[23]
:
where
V
_{cb}
is the voltage across the dc blocking capacitor. Since the primary current when the transistors of the leading leg are turned off is much smaller, the amplitude of the voltage oscillation is much smaller than the positive voltage when the transistor in the leading leg is turned off. As a result, the spurious turnon phenomenon is not induced by the turnoff of the transistors in the lagging leg. The turnoff of the transistors in the leading leg leads to crosstalk of the lagging leg and degrades the system efficiency and reliability. Meanwhile the turnoff of the transistors in the lagging leg have a weak effect on the performance of the system.
Actually, the spuriouson voltage of different transistors during different transition intervals are determined by the different parasitic inductors of the power circuit loop. Details of this are shown as follows.
1) Q_{4}’s TurnOff Procedure:
The analysis in Section IIIA shows that the spurious turnon voltage of Q
_{2}
, when Q
_{4}
is turned off, is correlated with the parasitic inductor L
_{pc1}
. During this transition interval, the voltage of the gatetosource terminals of Q
_{1}
and Q
_{4}
are the superposition of the positive induced voltage and the drive signals. Among them, the positive induce voltage of Q
_{1}
is mainly determined by the parasitic inductor L
_{pc3}
. Meanwhile the positive induce voltage of Q
_{4}
is mainly determined by the parasitic inductors L
_{pc1}
, L
_{pc2}
and L
_{s4}
. This is shown in
Fig. 3
.
When Q
_{1}
is still on, the positive induced voltage of Q
_{2}
leads to crosstalk of the lagging leg. The positive induced voltage of Q
_{1}
has no significant influence unless the voltage amplitude exceeds the maximum gatetosource tolerant voltage. Meanwhile, the positive induced voltage of Q
_{4}
slows down the turnoff procedure of Q
_{4}
and leads to more switching losses.
2) Q_{3}’s TurnOff Procedure:
Similarly, the transition interval of Q
_{3}
induces a positive voltage at the gatetosource terminals of Q
_{1}
, Q
_{2}
and Q
_{3}
. Among them, the positive induced voltage of Q
_{1}
is mainly determined by the parasitic inductor L
_{pc3}
, the positive induce voltage of Q
_{2}
is mainly determined by the parasitic inductor L
_{pc1}
, and the positive induce voltage of Q
_{3}
is mainly determined by the parasitic inductors L
_{pc3}
, L
_{pc4}
and L
_{s3}
.
When Q
_{2}
is still on, the positive induced voltage of Q
_{1}
leads to crosstalk of the lagging leg. The positive induced voltage of Q
_{2}
has no significant influence unless the voltage amplitude exceeds the maximum gatetosource tolerant voltage. Meanwhile, the positive induced voltage of Q
_{3}
slows down the turnoff procedure of Q
_{3}
and leads to more switching losses.
3) Q_{2}’s TurnOff Procedure:
The transition interval of Q
_{2}
induces a positive voltage at the gatetosource terminals of Q
_{1}
, Q
_{2}
and Q
_{4}
. Among them, the positive induce voltage of Q
_{1}
is mainly determined by the parasitic inductor L
_{pc3}
, the positive induce voltage of Q
_{4}
is mainly determined by the parasitic inductor L
_{pc1}
, and the positive induced voltage of Q
_{2}
is mainly determined by the parasitic inductors L
_{pc1}
and L
_{s2}
.
When D
_{3}
is forward bias, the positive induced voltage of Q
_{4}
does not lead to crosstalk of the leading leg. Meanwhile, the positive induced voltage of Q
_{2}
slows down the turnoff procedure of Q
_{2}
and leads to more switching losses.
4) Q_{1}’s TurnOff Procedure:
The transition interval of Q
_{1}
induces a positive voltage at the gatetosource terminals of Q
_{1}
, Q
_{2}
and Q
_{3}
. Among them, the positive induce voltage of Q
_{2}
is mainly determined by the parasitic inductor L
_{pc1}
, the positive induce voltage of Q
_{3}
is mainly determined by the parasitic inductor L
_{pc3}
, and the positive induce voltage of Q
_{2}
is mainly determined by the parasitic inductors L
_{pc3}
and L
_{s1}
.
When D
_{4}
is forward bias, the positive induced voltage of Q
_{3}
does not lead to crosstalk of the leading leg. Meanwhile, the positive induced voltage of Q
_{1}
slows down the turnoff procedure of Q
_{1}
and leads to more switching losses.
It should be noticed that all of the above conclusions are based on the assumption that Q
_{3}
Q
_{4}
is the leading leg. A similar analysis can be extended into the operation mode where Q
_{1}
Q
_{2}
is the leading leg.
In conclusion, since ZVS can be achieved in PSFB converters, the positive voltages across the gatetosource terminals of the transistors are mainly induced by the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak impact on the crosstalk phenomena. In addition, the specific operation principle of a PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turnon problem.
 C. Design Guidelines
At first, the transformer turns ratio should be selected. It is well known that the primary current is significantly affected by the transformer turns ratio
n
[1]
. Since the oscillation amplitude is positively correlated with the peak current of the primary side, the transformer ratio should be designed while carefully considering the primary RMS current and the duty cycle loss
[24]
. Moreover, the transformer turns ratio has an effect on the signal analysis. Specifically, the signal analysis is impacted by the transformer turns ratio in two ways, both directly and indirectly. The transformer turns ratio
n
appears on the expression of the dutytooutput transfer function of
G_{vd}
. The natural frequency
ω
_{n}
and the damping ratio
ξ
can be expressed as
[25]
:
The transformer turns ratio
n
explicitly appears in equations (25) and (26), which shows the direct impact on the damping ratio and the natural frequency. As a result, the transformer turns ratio directly influences the PSFB signal analysis. The direct impact is also verified by the analysis presented in
[26]
. Meanwhile, according to (25) and (26), the power loss equivalent resistor
R
_{eq}
also has an impact on the damping ratio and natural frequency, where the power loss equivalent resistor
R
_{eq}
can be expressed as:
P_{loss}
is the power loss in a PSFB converter. Meanwhile, the selection of the transformer turns ratio has a significant influence on the overall efficiency of the PSFB converter
[27]
,
[28]
. Specifically, a smaller turns ratio means a wider output voltage range. However, the conducting loss and the circulating period of the primary side increase with a smaller transformer turns ratio, which leads to more power loss and lower efficiency. Therefore, the selection of the transformer turns ratio has an effect on the efficiency of PSFB converters, and in turn indirectly impacts the signal analysis.
After that, in order to suppress the detrimental effects brought on by the positive induced voltage, several design guidelines can be given as follows according to the above analysis.
(1) Optimizing the PCB layout and minimizing the parasitic inductor in the power circuit loop. According to Sections IIIA and IIIB, the parasitic inductors L
_{pc1}
and L
_{pc3}
have a significant influence on the positive induced voltages. Therefore, it is important to optimize the PCB layout and reduce the copper line length of L
_{pc1}
and L
_{pc3}
. Meanwhile, the parasitic inductors L
_{pc2}
and L
_{pc4}
do not impact the crosstalk phenomena. Only the turnoff loss of Q
_{3}
and Q
_{4}
are influenced by the two parasitic inductors.
(2) The choice of the leading and lagging legs influences the spurious turnon phenomena. The leading leg is turned off with a larger current than the lagging leg, and the current flows through different parasitic inductors when the control of leading and lagging legs changes. It is preferable to make the Q
_{1}
Q
_{2}
leg, which is closer to the input terminal shown in
Fig. 8
of Section IV, the leading leg. Then the turnoff loss is reduced.
(3) Slow down the turnoff rate of the MOSFET, and decrease the current change rate of the current through the parasitic inductors. This can be realized by reducing the driving current
I_{dri}
. However, power loss occurs at the transition interval when the voltage and current are overlaid. Therefore, the turnoff rate should be as fast as possible in consideration of the power loss. A tradeoff should been made.
IV. EXPERIMENTAL VERIFICATION
In order to verify the above analysis and calculations, a 1.5 kW prototype with the PSFB topology is built. A STM32F051 microcontroller from ST Microelectronics is used to provide the PWM driving signals for the MOSFETs of the phaseshifted fullbridge converter. A microcontroller is chosen since this provides a convenient method for adjusting the switching frequency easily without the need to change the component values. More importantly, with the digital control method, it is very convenient to change the Q
_{1}
Q
_{2}
leg to be the leading or the lagging leg without modifying the layout. All of these are important factors for the experimental verifications carried out below. The simplified digital control scheme for the phaseshifted fullbridge converter in this paper is shown in
Fig. 6
.
Control scheme of the phaseshifted fullbridge converter.
As shown in
Fig. 6
, a voltage control loop is used to regulate the output voltage
V
_{o}
of the PSFB converter. The output voltage is conditioned and sensed by a feedback network, which is made up of the resistors divider (1:100) and the operational amplifier. Then it is converted by the analogtodigital converter in the STM32F051. After that, the voltage error
e
[k] between the output voltage
V
_{o}
[k] and its reference voltage
V
_{REF}
is fed to the digital PI controller. At last, the phaseshift modulator is used to adjust the phaseshift angle and to generate the gate driver signals. Specifically, the gate driver PWM signals are generated from the timer in the STM32F051. Thus, the phaseshift angle and the frequency of the switching signals can be controlled by modified the configuration of the timer.
The phaseshifted fullbridge prototype (1.5 kW) is shown in
Fig. 7
. The dimensions of the power board are also shown in this figure. The parasitic inductances introduced by the copper lines are mainly determined by the length and width of the copper lines, while the thickness of the copper lines has very little effect on the value of these inductors
[30]
. Thus, the dimensions of the copper interconnections that could cause this phenomenon are presented in
Fig. 8
. The irrelevant components are not shown. In order to make the dimensions more clear, they are listed in
Table I
.
Physical aspect of the PSFB Prototype.
Dimensions of the copper interconnect in the converter.
DETAILED CHARACTERIZATION OF THE DIMENSIONS OF THE COPPER LINE
DETAILED CHARACTERIZATION OF THE DIMENSIONS OF THE COPPER LINE
The main parameters of the prototype are listed in
Table II
. The maximum gatetosource voltage of the transistor is 30V, and the minimum gate threshold voltage is 3V. The input capacitance C
_{iss}
is 5870 pF, the output capacitance C
_{oss}
is 530 pF and the reverse transfer capacitance C
_{rss}
is 54 pF when V
_{GS}
=0 and V
_{DS}
=25 V
[29]
. First, simulation results of the voltage across the source node and the power ground,
V
_{Lp1}
, when Q
_{4}
is switched off, are shown in
Fig. 9
. Simulation results with various values of the parasitic inductor L
_{pc1}
are shown in
Fig. 9
(a) and (b). It has been found that the oscillation amplitude decreases with a smaller L
_{pc1}
.
MAIN PARAMETERS OF THE PSFB PROTOTYPE
MAIN PARAMETERS OF THE PSFB PROTOTYPE
Induced voltage across the parasitic inductor with different inductor values.
In order to verify the analysis in Section III, several tests are built separately. First, the Q
_{3}
Q
_{4}
leg is controlled as the leading leg as shown in
Fig. 8
. Basic operation waveforms and gatetosource waveforms of the PSFB converter are shown in
Fig. 10
.
Operational waveforms with Q_{3}Q_{4} as the leading leg.
 A. Minimized the Parasitic InductorLpc3
According to the above analysis, the spurious turnon voltage of Q
_{1}
is positively correlated with the value of the parasitic inductor L
_{pc3}
. The parasitic inductor is introduced by the copper line on the printed circuit board.
Therefore, in order to shorten the length between the source node and the power ground, a shortthick line is used to shorten the two points. Test results are shown in
Fig. 11
.
Operational waveforms with small L_{pc3}.
According to the formula presented in
[30]
, the parasitic inductor L
_{pc3}
is reduced from about 47 nH to 31.7 nH. As a result, the positive induced voltage of Q
_{1}
is suppressed when Q
_{3}
is turned off. However, the effect is not very significant since the existing copper line is not very long when compared to the short line.
 B. Changing theQ1Q2Leg as the Leading Leg
The Q
_{1}
Q
_{2}
leg is controlled as the leading leg. Experimental waveforms are shown in
Fig. 12
. According to
Fig. 12
, the peak amplitude of the induced positive voltage of Q
_{4}
in the lagging leg is sharply reduced.
Operational waveforms with Q_{1}Q_{2} as the leading leg.
The efficiency is improved correspondingly. In order to verify the effect, the overall efficiency is tested with different switching frequency using the Q
_{1}
Q
_{2}
leg and the Q
_{3}
Q
_{4}
leg as leading legs separately. Test results are shown in
Fig. 13
. The efficiency increased with the Q
_{1}
Q
_{2}
leg as the leading leg. Meanwhile, the difference between the efficiencies becomes more and more evident when the switching frequency increases.
Efficiency comparison with different leading leg.
The comparison results between the PSFB converter proposed in this paper, the conventional PSFB converter (CPSFB) and the latest novel PSFB converters proposed in
[7]
,
[8]
can be summarized in
Table III
. The proposed PSFB converter can achieve a relatively high efficiency without additional auxiliary components. In addition, the control scheme of this converter is easy to implement. Moreover, the voltage and current stresses are low when compared to the other existing highefficiency PSFB converters.
SUMMARY OF CONVERTERS CHARACTERISTICS
SUMMARY OF CONVERTERS CHARACTERISTICS
V. CONCLUSION
The PSFB converter is a widespread preferred topology for isolated dcdc power conversion in medium to high power applications. The spurious turnon phenomena have been observed in PSFB converters which lead to additional switching losses and overstress of the power devices. By taking into account the parasitic inductors of the power circuit loop and the transistors in the PSFB converter, the spurious turnon phenomena are thoroughly analysed considering the special operation principle of this topology. It has been found that this phenomenon is mainly induced by the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak impact on the crosstalk phenomena. In addition, the specific operation principle of the PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turnon problem.
Based on this analysis, several design guidelines are presented. Detailed simulation and experimental results obtained from a 1.5 kW PSFB converter are given to verify the above theoretical analysis. The positive induced voltage can be reduced with the proposed method and the efficiency can be improved.
BIO
Qing Wang received her B.A. degree from Shandong University, Shandong, China, in 2003; and her Ph.D. degree from Southeast University, Nanjing, China, in 2014. In 2014, she joined the Binjiang College, Nanjing University of Information Science and Technology, Nanjing, China. Her current research interests include high frequency power converters and their application to microprocessor voltage regulation modules and chargers.
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