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The Impact of Parasitic Elements on Spurious Turn-On in Phase-Shifted Full-Bridge Converters
The Impact of Parasitic Elements on Spurious Turn-On in Phase-Shifted Full-Bridge Converters
Journal of Power Electronics. 2016. May, 16(3): 883-893
Copyright © 2016, The Korean Institute Of Power Electronics
  • Received : October 01, 2015
  • Accepted : December 25, 2015
  • Published : May 20, 2016
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Qing, Wang
wangqing_033@hotmail.com

Abstract
This paper presents a comprehensive analysis of the spurious turn-on phenomena in phase-shifted full-bridge (PSFB) converters. The conventional analysis of the spurious turn-on phenomenon does not establish in the PSFB converter as realizing zero voltage switching (ZVS). Firstly, a circuit model is proposed taking into account the parasitic capacitors and inductors of the transistors, as well as the parasitic elements of the power circuit loop. Second, an exhaustive investigation into the impact of all these parasitic elements on the spurious turn-on is conducted. It has been found that the spurious turn-on phenomenon is mainly attributed to the parasitic inductors of the power circuit loop, while the parasitic inductors of the transistors have a weak impact on this phenomenon. In addition, the operation principle of the PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turn-on problems. Design guidelines are given based on the theoretical analysis. Finally, detailed simulation and experimental results obtained with a 1.5 kW PSFB converter are given to validate proposed analysis.
Keywords
I. INTRODUCTION
The phase-shifted full-bridge (PSFB) converter is applied in medium to high power conversions due to its attractive features including a simple circuit, constant operation frequency and ZVS-on of the primary switches [1] - [5] . This type of converter has been extensively studied in the literature, including modeling, design optimization, control method, flux bias compensation, improved full-bridge topologies, etc. [6] - [10] .
Despite all its merits, the PSFB converter has the risk of spurious turn-on of the transistors. The interaction between the upper and lower transistors in a bridge leg during a switching transient (crosstalk) can appear. This leads to additional switching losses and overstress of the power devices. With the increased demand for high power density, larger currents and higher switching frequencies are the new trends for power supplies. Under these circumstances, the effects of the circuit parasitic parameters on the converter’s performance are becoming more and more significant [11] . As a result, the PSFB converter is becoming more vulnerable to spurious turn-on problems.
Actually, the spurious turn-on phenomena in power switching converters and has been studied in many works [12] - [17] . In these studies, the spurious turn-on phenomena are mainly induced by the hard switching of transistors. High dv/dt during fast switching on the transient of one device affects the operating behavior of its complementary device [12] - [15] . Meanwhile, the high di/dt induces a negative voltage across the parasitic source inductor of the MOSFET, pulling down its source voltage [16] , [17] . The parasitic source inductor, the recovery current presented by the body diode, and the parasitic capacitors are thought to be the key elements of the spurious turn-on phenomena in hard switching power converters. However, in PSFB converters, ZVS on is achieved and the conventional analysis does not apply here. In addition, the mechanism of the spurious turn-on phenomena in PSFB converters has been rarely analyzed comprehensively. Thus, it is very meaningful to conduct studies on phase-shifted full-bridge converters.
In this paper, the switching transition when the spurious turn-on phenomenon occurs in a PSFB converter will be specified by an analytical model, which takes into account the parasitic inductors of the power circuit loop, as well as the parasitic capacitors and inductors of the transistors. According to the analysis, the parasitic inductors of the power circuit loop are the key elements of the spurious turn-on in PSFB converters, while the parasitic source inductors and the recovery current presented by the body diode have weak impacts on this phenomenon since ZVS-on is realized here. Design guidelines for reducing the spurious triggering pulse are then given. At last, a series of simulation and experimental results will be provided to verify the theoretical analysis.
II. SPURIOUS TURN-ON PHENOMENON
- A. Operation Principle of PSFB Converters
Fig. 1 (a) and (b) show a circuit diagram [1] , [18] and key waveforms [18] , [19] of the standard PSFB converter. According to Fig. 1 (a), a PSFB converter is formed by four transistors Q 1 -Q 4 , a power transformer T r , a resonant inductor L R (including the leakage inductor), output rectifier diodes D R1 and D R2 , an output filter inductor L f and a capacitor C f . Meanwhile, as shown in Fig. 1 (b), Q 3 and Q 4 are switched on/off before Q 1 and Q 2 . Thus, the Q 3 -Q 4 leg is designated as the “leading leg”, while the Q 1 -Q 2 leg is designated as the “lagging leg”. The primary current I p reaches its peak value when the transistor of the leading leg is turned off.
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PSFB converter topology and key waveforms.
It is well known that ZVS turn-on can be achieved by utilizing the energy stored in the resonant inductor L R to charge and discharge the parasitic capacitors of MOSFETs [19] . The voltage across the drain-to-source terminals of a MOSFET should be discharged to zero before it is switched on. Meanwhile, the current through the MOSFET decreases to zero. This transition interval (TI), between tb - t2 , is accomplished during the turn off procedure of the MOSFET as shown in Fig. 2 [20] , [21] . The voltage across the drain-to-source terminals of the MOSFET and current through the MOSFET change drastically. For example, the voltage across the drain-to-source terminals of Q 4 is charged to Vin and the voltage across the drain-to-source terminals of Q 3 is discharged to zero during the turn-off procedure of Q 4 . Meanwhile, the drain current of Q 4 decreases to zero during this interval.
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Turn-off procedure of MOSFET in PSFB converter.
- B. Spurious Turn-On in Practice
According to the analysis in [15] , in the soft-switching power converters, during the turn-off transient of the lower switch, the negative spurious voltage induced at the gate–source terminals of the upper switch may overstress the power device if its magnitude exceeds the maximum allowable negative gate voltage that is acceptable to the semiconductor device. For example, when Q 4 is turned off, there is a negative spurious voltage across the gate–source terminals of Q 3 . However, in addition to a negative spurious voltage at the gate–source terminals of the complementary transistor, a positive spurious voltage is observed at the gate-source terminals of the transistors. This is shown in Fig. 3 , which is directly obtained from a 1.5 kW phase-shifted full-bridge converter. Since the Q 1 -Q 2 leg is the lagging leg, Q 1 is still on when Q 4 is turned off and the spurious turn-on of Q 2 leads to an interaction between the transistors of the lagging leg (crosstalk).
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Spurious turn-on of the transistors in lagging leg.
Actually, a positive induced voltage can be observed during every transistor’s turn-off procedure. As shown in Fig. 3 , when the transistor in a lagging leg, such as Q 2 , is turned off, an oscillation can be observed at the gate-to-source terminals of Q 4 . However, the amplitude of the voltage oscillation is much smaller than the positive voltage when the transistor in the leading leg is turned off. A detail analysis and explanations are given in Section III.
III.MECHANISM ANALYSIS AND DESIGN GUIDELINES
- A. Circuit Modeling and Mechanism Analysis
An equivalent circuit model of a PSFB converter is shown in Fig. 4 . The parasitic elements considered for the transistors are the gate-source capacitance C gs , gate-drain capacitance C gd , drain-source capacitance C ds , internal gate inductor L g-in , drain inductor L d-in , source inductor L s-in , and the body diode D. The drain inductor L d-cw and source inductor L s-cw are the parasitic inductors introduced by the copper wires and the pads of the printed circuit board. In addition, the parasitic inductors of the power circuit loop, L pc1 , L pc2 , L pc3 and L pc4 , are considered in the proposed equivalent circuit model. It should be noted that the proposed equivalent circuit model is valid only when a PSFB converter has a large power (usually larger than 500W) and is realized within the printed circuit board (PCB). The large power of the converter means bulky capacitors with a large size at the input terminal [22] . As a result, the copper lines from the drain node to the input capacitor are long enough to produce parasitic inductors. This can be verified by the layout shown in Fig. 8 . These parasitic inductors, which are introduced by the copper wires of the power circuit loop, have been neglected in previous analyses since they are not involved in the gate drive loop, as shown in Fig. 4 , and are thought to be irrelevant in terms of the spurious turn-on phenomena. However, the occurrence of crosstalk is mainly induced by the parasitic inductors of the power circuit loop due to the special operation principle of the PSFB converter. Detailed analyses are shown as follows.
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Equivalent circuit of a PSFB converter.
Since the oscillation is observed during the turn-off procedure, the converter is analyzed in four different modes, as shown in Fig. 2 : (1) Energy transfer and overdrive region (before t a ). (2) Miller Plateau ( t a ~ t b ). (3) Transition interval ( t b ~ t o ). (4) Circulating mode (after t o ). Equivalent circuits of the four operating modes are illustrated in Fig. 5 . For simplicity, the output stage is not shown in the equivalent circuits.
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Equivalent circuits of different operating modes.
Due to the symmetric nature of the two bridge legs, the analysis process for each transistor is similar. Therefore the turn-off procedure of Q 4 is taken as an example. Details of each operation mode are described as follows.
- Mode 1 [Energy transfer, beforeta]
This is an energy transfer mode. The diagonal switches Q 1 and Q 4 were conducting. The primary current flows through the diagonal transistor Q 1 in the lagging leg and the transistor Q 4 in the leading leg. This is shown in Fig. 5 (a). At ta , the primary current reaches its maximum value and can be expressed as [1] :
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This mode ends when the drain current of Q 4 starts to decrease, which starts at ta according to Fig. 2 .
- Mode 2 [Miller Plateau,ta-tb]
This stage begins when the gate-to-source voltage Vgs decreases to the Miller Plateau level Vmiller . During this stage, the gate-to-drain capacitor C gd is charged by the driving current, and the drain-to-source capacitor C ds is charged by the primary current. Although the current through the resonant inductor L R is nearly constant, the current through Q 4 (including D 4 and C ds4 ) starts to decrease. This is the beginning of the ZVS procedure.
It should be pointed out that the current through Q 4 changes slightly in this plateau. This is because the driving current is mainly used to discharge the gate-to-drain parasitic capacitor. This is not shown in Fig. 5 .
- Mode 3 [Transition Interval,tb~to]
According to Fig. 2 , the gate-to-source voltage of Q 4 starts to decrease at tb . Therefore, the current through the channel of Q 4 decreases drastically. The primary current flows through both of the drain-to-source parasitic capacitors of Q 3 and Q 4 . Obviously, the current through Q 4 is same as the current through the parasitic inductors L pc1 , L pc2 and L pc3 as shown in Fig. 5 (b).
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where ILp1 , ILp2 and ILp3 are the currents through the parasitic inductors L pc1 , L pc2 and L pc3 .
Therefore, the currents through the parasitic inductors L pc1 , L pc2 and L pc3 decrease drastically. With the decreasing of the current, there is an inductive voltage across the parasitic inductors, which is shown in Fig. 5 (b). Among them, VLp1 can be expressed as:
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Similarly, there are inductive voltages across L pc2 and L pc3 . The expressions of the two inductive voltages can be deduced as:
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The parasitic inductors around the transistor and the gate driver loop can be summarized as:
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According to Fig. 5 (b), during the transition interval, the current through the parasitic inductors around Q 2 remains constant. Therefore, the parasitic inductors of the transistor have a weak influence on the spurious turn-on phenomenon of Q 2 . It should be noticed that the current through the parasitic inductors around Q 4 also changes during this interval. An analysis of this has been presented in [17] and is not be shown here. More importantly, the inductive voltage across the parasitic inductors of the power circuit loop may lead to the spurious turn-on phenomena since the parasitic inductances of the power circuit loop is much larger than the parasitic inductances around the MOSFETs. To be specific, the negative induced voltage across L pc1 may lead to the spurious turn-on phenomenon of Q 2 and the crosstalk of the lagging leg occurs when Q 1 is still on. The negative induced voltage across L pc1 and L pc2 may lead to a positive voltage across the gate-to-source terminals of Q 4 and increase the switching loss. The negative induced voltage across L pc3 leads to a positive voltage across the gate-to-source terminals of Q 1 . The positive induced voltage of Q 1 has no significant influence unless the voltage amplitude exceeds the maximum tolerant voltage.
In order to obtain the maximum amplitude of the positive induced voltage, the decreasing slope of ILp1 is deduced as follows. According to Fig. 2 , the current decreasing slope changes in Mode 2 . Therefore, the transition interval can be divided into two stages.
Stage 1 (tb-tc): At the beginning of the transition interval, the primary current keeps flowing using the switch channel and its drain-to-source parasitic capacitor, Cds4 . This charges the drain-to-source parasitic capacitance of Q 4 from essentially zero volts to the upper voltage rail, Vin . Simultaneously, the drain-to-source parasitic capacitor of the switch Q 3 is discharged as its source voltage rises from the lower to the upper rail voltage. This resonant transition positions the switch Q 3 with no drain to the source voltage prior to turn-on and facilitates lossless, zero voltage switching. This is shown in Fig. 5 (c).
Therefore, during Stage 1 , the primary current is equal to the sum of three parts: Ic4 (the current through the channel of Q 4 ), ICds4 (the current through the drain-to-source parasitic capacitor of Q 4 ) and ICds3 (the current through the drain-to-source parasitic capacitor of Q 3 ).
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Among them, the voltage transition rates of C ds3 and C ds4 are equal, and C ds3 is equal to C ds4 since the same type of MOSFETs are adopted. Therefore, ICds4 is equal to ICds3 according to following equations.
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The current through Q 4 can be expressed as:
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The relationship between Vgs4 and Ic4 can be deduced as follows.
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where gm is the trans-conductance of the MOSFET, and Vth is the threshold voltage of the MOSFET.
The gate driving current is used to discharge C gs4 while Vgs4 decreases. It should be noticed that the driving current is used to charge C gd4 while Vgd4 simultaneously changes. Vgs4 can be expressed as:
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where Vmiller is the voltage amplitude of the miller plateau, Idri is the driving current, and C gd is the parasitic capacitance across the gate-to-drain.
Substitute (9) into (8):
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Then substitute (9), (10) and (14) into (8), and it can be deduced that:
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Vds can be deduced from (14):
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The constants C 1 and C 2 can be evaluated from the initial conditions. Vds4 is equal to Vin at tc and it is equal to zero at tb .
Meanwhile, since the current through L pc1 is equal to the current through Q 4 , the changing rate of ILp1 during stage 1 can be deduced as:
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Substitute (16) into (17). Then the changing rate of ILp1 can be deduced. However, the result is too complicated and is not shown here.
This stage ends when the voltage of Vds4 reaches V in , and the driving current is all applied to discharge C gs .
Stage 2 (tc-t2): When the voltage of Vds4 reaches V in , the primary current continues to flow using the switch and body diode of Q 3 , which is shown in Fig .5 (c).
Since the driving current is all applied to discharge C gs , (13) can be rewritten as:
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Substitute (14) into (8):
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Then substitute (9), (10) and (19) into (8), and it can be deduced that:
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Then the change rate of ILp1 during Stage 2 can be deduced as:
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Substitute (17) and (21) into (3), and the inductive voltage across the parasitic inductor L pc1 can be deduced as:
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Since Q 1 is still on, the voltage of the drain node of Q 2 is constant. Thus, the spurious-on voltage of Q 2 can be deduced as [17] :
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- Mode 3 [Circulating mode,t>t2]
Q 4 is completely turned off and all of the primary current is flowing through D 3 . This is shown in Fig. 5 (d).
- B. Impact of the Parasitic Elements
According to the above analysis results, the spurious-on voltage is mainly correlated with the value of the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak influence on the spurious-on voltage. In addition, the current change rate is positively correlated with the current amplitude when the transistor is turned off according to (21). Meanwhile, the primary current reaches its peak value when the transistor in the leading leg is turned off, and the transistor in the leading leg is turned off with a much smaller current when the primary current decreases a lot during the circulating mode. The peak value of the primary current has been deduced in (1). The primary current decreases a lot during the circulating mode due to the dc blocking capacitor, which is widely used in PSFB converters to eliminate the flux density bias [19] . The current decrease during this mode can be expressed as [23] :
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where V cb is the voltage across the dc blocking capacitor. Since the primary current when the transistors of the leading leg are turned off is much smaller, the amplitude of the voltage oscillation is much smaller than the positive voltage when the transistor in the leading leg is turned off. As a result, the spurious turn-on phenomenon is not induced by the turn-off of the transistors in the lagging leg. The turn-off of the transistors in the leading leg leads to crosstalk of the lagging leg and degrades the system efficiency and reliability. Meanwhile the turn-off of the transistors in the lagging leg have a weak effect on the performance of the system.
Actually, the spurious-on voltage of different transistors during different transition intervals are determined by the different parasitic inductors of the power circuit loop. Details of this are shown as follows.
1) Q4’s Turn-Off Procedure: The analysis in Section III-A shows that the spurious turn-on voltage of Q 2 , when Q 4 is turned off, is correlated with the parasitic inductor L pc1 . During this transition interval, the voltage of the gate-to-source terminals of Q 1 and Q 4 are the superposition of the positive induced voltage and the drive signals. Among them, the positive induce voltage of Q 1 is mainly determined by the parasitic inductor L pc3 . Meanwhile the positive induce voltage of Q 4 is mainly determined by the parasitic inductors L pc1 , L pc2 and L s4 . This is shown in Fig. 3 .
When Q 1 is still on, the positive induced voltage of Q 2 leads to crosstalk of the lagging leg. The positive induced voltage of Q 1 has no significant influence unless the voltage amplitude exceeds the maximum gate-to-source tolerant voltage. Meanwhile, the positive induced voltage of Q 4 slows down the turn-off procedure of Q 4 and leads to more switching losses.
2) Q3’s Turn-Off Procedure: Similarly, the transition interval of Q 3 induces a positive voltage at the gate-to-source terminals of Q 1 , Q 2 and Q 3 . Among them, the positive induced voltage of Q 1 is mainly determined by the parasitic inductor L pc3 , the positive induce voltage of Q 2 is mainly determined by the parasitic inductor L pc1 , and the positive induce voltage of Q 3 is mainly determined by the parasitic inductors L pc3 , L pc4 and L s3 .
When Q 2 is still on, the positive induced voltage of Q 1 leads to crosstalk of the lagging leg. The positive induced voltage of Q 2 has no significant influence unless the voltage amplitude exceeds the maximum gate-to-source tolerant voltage. Meanwhile, the positive induced voltage of Q 3 slows down the turn-off procedure of Q 3 and leads to more switching losses.
3) Q2’s Turn-Off Procedure: The transition interval of Q 2 induces a positive voltage at the gate-to-source terminals of Q 1 , Q 2 and Q 4 . Among them, the positive induce voltage of Q 1 is mainly determined by the parasitic inductor L pc3 , the positive induce voltage of Q 4 is mainly determined by the parasitic inductor L pc1 , and the positive induced voltage of Q 2 is mainly determined by the parasitic inductors L pc1 and L s2 .
When D 3 is forward bias, the positive induced voltage of Q 4 does not lead to crosstalk of the leading leg. Meanwhile, the positive induced voltage of Q 2 slows down the turn-off procedure of Q 2 and leads to more switching losses.
4) Q1’s Turn-Off Procedure: The transition interval of Q 1 induces a positive voltage at the gate-to-source terminals of Q 1 , Q 2 and Q 3 . Among them, the positive induce voltage of Q 2 is mainly determined by the parasitic inductor L pc1 , the positive induce voltage of Q 3 is mainly determined by the parasitic inductor L pc3 , and the positive induce voltage of Q 2 is mainly determined by the parasitic inductors L pc3 and L s1 .
When D 4 is forward bias, the positive induced voltage of Q 3 does not lead to crosstalk of the leading leg. Meanwhile, the positive induced voltage of Q 1 slows down the turn-off procedure of Q 1 and leads to more switching losses.
It should be noticed that all of the above conclusions are based on the assumption that Q 3 -Q 4 is the leading leg. A similar analysis can be extended into the operation mode where Q 1 -Q 2 is the leading leg.
In conclusion, since ZVS can be achieved in PSFB converters, the positive voltages across the gate-to-source terminals of the transistors are mainly induced by the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak impact on the crosstalk phenomena. In addition, the specific operation principle of a PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turn-on problem.
- C. Design Guidelines
At first, the transformer turns ratio should be selected. It is well known that the primary current is significantly affected by the transformer turns ratio n [1] . Since the oscillation amplitude is positively correlated with the peak current of the primary side, the transformer ratio should be designed while carefully considering the primary RMS current and the duty cycle loss [24] . Moreover, the transformer turns ratio has an effect on the signal analysis. Specifically, the signal analysis is impacted by the transformer turns ratio in two ways, both directly and indirectly. The transformer turns ratio n appears on the expression of the duty-to-output transfer function of Gvd . The natural frequency ω n and the damping ratio ξ can be expressed as [25] :
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The transformer turns ratio n explicitly appears in equations (25) and (26), which shows the direct impact on the damping ratio and the natural frequency. As a result, the transformer turns ratio directly influences the PSFB signal analysis. The direct impact is also verified by the analysis presented in [26] . Meanwhile, according to (25) and (26), the power loss equivalent resistor R eq also has an impact on the damping ratio and natural frequency, where the power loss equivalent resistor R eq can be expressed as:
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Ploss is the power loss in a PSFB converter. Meanwhile, the selection of the transformer turns ratio has a significant influence on the overall efficiency of the PSFB converter [27] , [28] . Specifically, a smaller turns ratio means a wider output voltage range. However, the conducting loss and the circulating period of the primary side increase with a smaller transformer turns ratio, which leads to more power loss and lower efficiency. Therefore, the selection of the transformer turns ratio has an effect on the efficiency of PSFB converters, and in turn indirectly impacts the signal analysis.
After that, in order to suppress the detrimental effects brought on by the positive induced voltage, several design guidelines can be given as follows according to the above analysis.
(1) Optimizing the PCB layout and minimizing the parasitic inductor in the power circuit loop. According to Sections III-A and III-B, the parasitic inductors L pc1 and L pc3 have a significant influence on the positive induced voltages. Therefore, it is important to optimize the PCB layout and reduce the copper line length of L pc1 and L pc3 . Meanwhile, the parasitic inductors L pc2 and L pc4 do not impact the crosstalk phenomena. Only the turn-off loss of Q 3 and Q 4 are influenced by the two parasitic inductors.
(2) The choice of the leading and lagging legs influences the spurious turn-on phenomena. The leading leg is turned off with a larger current than the lagging leg, and the current flows through different parasitic inductors when the control of leading and lagging legs changes. It is preferable to make the Q 1 -Q 2 leg, which is closer to the input terminal shown in Fig. 8 of Section IV, the leading leg. Then the turn-off loss is reduced.
(3) Slow down the turn-off rate of the MOSFET, and decrease the current change rate of the current through the parasitic inductors. This can be realized by reducing the driving current Idri . However, power loss occurs at the transition interval when the voltage and current are overlaid. Therefore, the turn-off rate should be as fast as possible in consideration of the power loss. A tradeoff should been made.
IV. EXPERIMENTAL VERIFICATION
In order to verify the above analysis and calculations, a 1.5 kW prototype with the PSFB topology is built. A STM32F051 microcontroller from ST Microelectronics is used to provide the PWM driving signals for the MOSFETs of the phase-shifted full-bridge converter. A microcontroller is chosen since this provides a convenient method for adjusting the switching frequency easily without the need to change the component values. More importantly, with the digital control method, it is very convenient to change the Q 1 -Q 2 leg to be the leading or the lagging leg without modifying the layout. All of these are important factors for the experimental verifications carried out below. The simplified digital control scheme for the phase-shifted full-bridge converter in this paper is shown in Fig. 6 .
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Control scheme of the phase-shifted full-bridge converter.
As shown in Fig. 6 , a voltage control loop is used to regulate the output voltage V o of the PSFB converter. The output voltage is conditioned and sensed by a feedback network, which is made up of the resistors divider (1:100) and the operational amplifier. Then it is converted by the analog-to-digital converter in the STM32F051. After that, the voltage error e [k] between the output voltage V o [k] and its reference voltage V REF is fed to the digital PI controller. At last, the phase-shift modulator is used to adjust the phase-shift angle and to generate the gate driver signals. Specifically, the gate driver PWM signals are generated from the timer in the STM32F051. Thus, the phase-shift angle and the frequency of the switching signals can be controlled by modified the configuration of the timer.
The phase-shifted full-bridge prototype (1.5 kW) is shown in Fig. 7 . The dimensions of the power board are also shown in this figure. The parasitic inductances introduced by the copper lines are mainly determined by the length and width of the copper lines, while the thickness of the copper lines has very little effect on the value of these inductors [30] . Thus, the dimensions of the copper interconnections that could cause this phenomenon are presented in Fig. 8 . The irrelevant components are not shown. In order to make the dimensions more clear, they are listed in Table I .
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Physical aspect of the PSFB Prototype.
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Dimensions of the copper interconnect in the converter.
DETAILED CHARACTERIZATION OF THE DIMENSIONS OF THE COPPER LINE
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DETAILED CHARACTERIZATION OF THE DIMENSIONS OF THE COPPER LINE
The main parameters of the prototype are listed in Table II . The maximum gate-to-source voltage of the transistor is 30V, and the minimum gate threshold voltage is 3V. The input capacitance C iss is 5870 pF, the output capacitance C oss is 530 pF and the reverse transfer capacitance C rss is 54 pF when V GS =0 and V DS =25 V [29] . First, simulation results of the voltage across the source node and the power ground, V Lp1 , when Q 4 is switched off, are shown in Fig. 9 . Simulation results with various values of the parasitic inductor L pc1 are shown in Fig. 9 (a) and (b). It has been found that the oscillation amplitude decreases with a smaller L pc1 .
MAIN PARAMETERS OF THE PSFB PROTOTYPE
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MAIN PARAMETERS OF THE PSFB PROTOTYPE
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Induced voltage across the parasitic inductor with different inductor values.
In order to verify the analysis in Section III, several tests are built separately. First, the Q 3 -Q 4 leg is controlled as the leading leg as shown in Fig. 8 . Basic operation waveforms and gate-to-source waveforms of the PSFB converter are shown in Fig. 10 .
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Operational waveforms with Q3-Q4 as the leading leg.
- A. Minimized the Parasitic InductorLpc3
According to the above analysis, the spurious turn-on voltage of Q 1 is positively correlated with the value of the parasitic inductor L pc3 . The parasitic inductor is introduced by the copper line on the printed circuit board.
Therefore, in order to shorten the length between the source node and the power ground, a short-thick line is used to shorten the two points. Test results are shown in Fig. 11 .
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Operational waveforms with small Lpc3.
According to the formula presented in [30] , the parasitic inductor L pc3 is reduced from about 47 nH to 31.7 nH. As a result, the positive induced voltage of Q 1 is suppressed when Q 3 is turned off. However, the effect is not very significant since the existing copper line is not very long when compared to the short line.
- B. Changing theQ1-Q2Leg as the Leading Leg
The Q 1 -Q 2 leg is controlled as the leading leg. Experimental waveforms are shown in Fig. 12 . According to Fig. 12 , the peak amplitude of the induced positive voltage of Q 4 in the lagging leg is sharply reduced.
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Operational waveforms with Q1-Q2 as the leading leg.
The efficiency is improved correspondingly. In order to verify the effect, the overall efficiency is tested with different switching frequency using the Q 1 -Q 2 leg and the Q 3 -Q 4 leg as leading legs separately. Test results are shown in Fig. 13 . The efficiency increased with the Q 1 -Q 2 leg as the leading leg. Meanwhile, the difference between the efficiencies becomes more and more evident when the switching frequency increases.
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Efficiency comparison with different leading leg.
The comparison results between the PSFB converter proposed in this paper, the conventional PSFB converter (CPSFB) and the latest novel PSFB converters proposed in [7] , [8] can be summarized in Table III . The proposed PSFB converter can achieve a relatively high efficiency without additional auxiliary components. In addition, the control scheme of this converter is easy to implement. Moreover, the voltage and current stresses are low when compared to the other existing high-efficiency PSFB converters.
SUMMARY OF CONVERTERS CHARACTERISTICS
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SUMMARY OF CONVERTERS CHARACTERISTICS
V. CONCLUSION
The PSFB converter is a widespread preferred topology for isolated dc-dc power conversion in medium to high power applications. The spurious turn-on phenomena have been observed in PSFB converters which lead to additional switching losses and overstress of the power devices. By taking into account the parasitic inductors of the power circuit loop and the transistors in the PSFB converter, the spurious turn-on phenomena are thoroughly analysed considering the special operation principle of this topology. It has been found that this phenomenon is mainly induced by the parasitic inductors of the power circuit loop. The parasitic inductors of the transistors have a weak impact on the crosstalk phenomena. In addition, the specific operation principle of the PSFB converter makes the leading and lagging legs have distinguished differences with respect to the spurious turn-on problem.
Based on this analysis, several design guidelines are presented. Detailed simulation and experimental results obtained from a 1.5 kW PSFB converter are given to verify the above theoretical analysis. The positive induced voltage can be reduced with the proposed method and the efficiency can be improved.
BIO
Qing Wang received her B.A. degree from Shandong University, Shandong, China, in 2003; and her Ph.D. degree from Southeast University, Nanjing, China, in 2014. In 2014, she joined the Binjiang College, Nanjing University of Information Science and Technology, Nanjing, China. Her current research interests include high frequency power converters and their application to microprocessor voltage regulation modules and chargers.
References
Redl R. , Sokal N. O. , Balogh L. 1991 “A novel soft-switching full-bridge DC/DC converter: Analysis, design considerations, and experimental results at 1.5 kW, 100 kHz,” IEEE Trans. Power Electron. 6 (3) 408 - 418    DOI : 10.1109/63.85909
Lee Y. C. , Kim H. K. , Kim J. H. , Hong S. S. 2014 “A study on implementing a phase-shift full-bridge converter employing an asynchronous active clamp circuit,” Journal of Power Electronics 14 (3) 413 - 420    DOI : 10.6113/JPE.2014.14.3.413
Jang Y. , Jovanovic M. M. , Chang Y. M. 2003 “A new ZVS-PWM full-bridge converter,” IEEE Trans. Power Electron. 18 (5) 1122 - 1129    DOI : 10.1109/TPEL.2003.816189
Kim T. H. , Lee S. J. , Choi W. 2012 “Design and control of the phase shift full bridge converter for the on-board battery charger of electric forklifts,” Journal of Power Electronics 12 (1) 113 - 119    DOI : 10.6113/JPE.2012.12.1.113
Chen W. , Ruan X. , Zhang R. 2008 “A novel zero-voltage-switching PWM full bridge converter,” IEEE Trans. Power Electron. 23 (2) 793 - 801    DOI : 10.1109/TPEL.2007.915764
Hsieh Y. , Huang C. 2011 “Li-ion battery charger based on digitally controlled phase-shifted full-bridge converter,” IET Power Electron. 2 (4) 242 - 247    DOI : 10.1049/iet-pel.2009.0206
Lee S. H. , Park C. Y. , Kwon J. M. , Kwon B. H. 2015 “Hybrid-type full-bridge DC/DC converter with high efficiency,” IEEE Trans. Power Electron. 30 (8) 4156 - 4164    DOI : 10.1109/TPEL.2014.2360404
Chen Z. , Liu S. , Shi L. C. 2014 “A soft switching full bridge converter with reduced parasitic oscillation in a wide load range,” IEEE Trans. Power Electron. 29 (2) 801 - 811    DOI : 10.1109/TPEL.2013.2257868
Bakan A. F. , Altintas N. , Aksoy I. 2013 “An improved PSFB PWM DC-DC converter for high-power and frequency applications,” IEEE Trans. Power Electron. 1 (28) 64 - 74    DOI : 10.1109/TPEL.2012.2196287
Kim D. Y. , Lim C. E. , Moon G. W. 2013 “Variable delay time method in the phase-shifted full-bridge converter for reduced power consumption under light load conditions,” IEEE Trans. Power Electron. 9 (28) 5120 - 5126    DOI : 10.1109/TPEL.2013.2237926
Emami Z. , Motahari M. , Shafiei N. , Motahari S. R. “Leading and lagging legs power loss analysis in ZVS Phase-Shifted Full-Bridge converter,” 2nd IEEE Power Electronics, Drive Systems and Technologies Conference 2011 632 - 637
Zhao Q. , Stojcic G. 2007 “Characterization of Cdv/dt induced power loss in synchronous buck DC-DC converters,” IEEE Trans. Power Electron. 22 (4) 292 - 297    DOI : 10.1109/TPEL.2007.900527
Qin H. , Zhao B. , Xu W. , Wen J. , Yan Y. “Evaluation of performance improvement of silicon carbide MOSFETs based DC-DC converter,” 2012 IEEE 7th International Power Electronics and Motion Control Conference - ECCE Asia 2012 717 - 722
Li H. , Munk-Nielsen S. “Detail study of SiC MOSFET switching characteristics,” Power Electronics for Distributed Generation Systems (PEDG), 2014 IEEE 5th International Symposium on IEEE 2014 1 - 5
Zhang Z. , Wang F. , Tolbert L. M. , Blalock B. J. 2014 “Active gate driver for crosstalk suppression of SiC devices in a phase-leg configuration,” IEEE Trans. Power Electron. 29 (4) 1986 - 1997    DOI : 10.1109/TPEL.2013.2268058
Wang J. J. , Chung H. S. 2015 “A novel RCD level shifter for elimination of spurious turn-on in the bridge-leg configuration,” IEEE Trans. Power Electron. 30 (2)    DOI : 10.1109/TPEL.2014.2310898
Wang J. J. , Chung H. S. 2014 “Impact of parasitic elements on the spurious triggering pulse in synchronous buck converter,” IEEE Trans. Power Electron. 29 (12)
Sabate J. A. , Vlatkovic V. , Ridley R. B. , Lee F. , Cho B. H. “Design considerations for high-voltage high-power full-bridge zero-voltage-switched PWM converter,” in Applied Power Electronics Conference and Exposition (APEC), Conference Proceedings 1990., Fifth Annual 1990 275 - 284
Mweene L. H. , Wrigh C. A. , Schlecht M. F. 1991 “A 1 kW 500 kHz Front-End Converter for a Distributed Power Supply System,” IEEE Trans. Power Electron. 6 (3) 398 - 407    DOI : 10.1109/63.85908
Balogh L. “Design and application guide for high speed MOSFET gate drive circuits,” Power Supply Design Seminar SEM-1400 2001 Topic 2, Texas Instruments Literature
2005 International Rectifier-Use Gate Charge to Design the Gate Drive Circuit for Power MOSFETs and IGBTs http://www.irf.com/technical-info/appnotes/an-944.pdf
Ribeiro H. S. , Borges B. S. 2014 “High-performance voltage-fed AC-DC full-bridge single-stage power factor correctors with a reduced DC bus capacitor,” IEEE Trans. Power Electron. 29 (6) 228 - 235
Koo G. B. , Moon G. W. , Youn M. J. 2005 “New zero-voltage-switching phase-shift full-bridge converter with low conduction losses,” IEEE Trans. Ind. Electron. 52 (1) 228 - 235    DOI : 10.1109/TIE.2004.841063
Ribeiro H. , Borges B. V. 2010 “Analysis and design of a high efficiency full-bridge single stage converter with reduced auxiliary components,” IEEE Trans. Power Electron. 25 (7) 1850 - 1862    DOI : 10.1109/TPEL.2010.2042970
Capua G. Di , Shirsavar S. A. , Hallworth M. A. , Femia N. 2015 “An enhanced model for small-signal analysis of the phase-shifted full-bridge converter,” IEEE Trans. Power Electron. 30 (3) 1567 - 1576    DOI : 10.1109/TPEL.2014.2314241
Vlatkovic V. , Sabate J. A. , Ridley R. B. , Lee F. C. , Cho B. H. 1992 “Small-signal analysis of the phase-shifted PWM converter,” IEEE Trans. Power Electron. 7 (1) 128 - 135    DOI : 10.1109/63.124585
Hallworth M. , Potter B. , Shirsavar A. 2013 “Analytical calculation of resonant inductance for zero voltage switching in phase-shifted full-bridge converters,” IET Power Electron. 6 (3) 523 - 534    DOI : 10.1049/iet-pel.2012.0461
Kim E. S. , Joe K. Y. , Kye M. H. , Kim Y. H. , Yoon B. D. 1999 “An improved soft-switching PWM FB DC/DC converter for reducing conduction losses,” IEEE Trans. Power Electron. 14 (2) 258 - 264    DOI : 10.1109/63.750178
InternationalRectifier http://www.irf.com/product-info/data sheets/data/irfps30n60k.pdf
Maniktala S. 2012 Switching Power Supplies A-Z 2nd Ed. Butterworth-Heinemann