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A Novel PCCM Voltage-Fed Single-Stage Power Factor Correction Full-Bridge Battery Charger
A Novel PCCM Voltage-Fed Single-Stage Power Factor Correction Full-Bridge Battery Charger
Journal of Power Electronics. 2016. May, 16(3): 872-882
Copyright © 2016, The Korean Institute Of Power Electronics
  • Received : August 08, 2015
  • Accepted : December 14, 2015
  • Published : May 20, 2016
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About the Authors
Taizhi, Zhang
National ASIC System Engineering Research Center, Southeast University, Nanjing, China
Zhipeng, Lu
National ASIC System Engineering Research Center, Southeast University, Nanjing, China
Qinsong, Qian
National ASIC System Engineering Research Center, Southeast University, Nanjing, China
Weifeng, Sun
National ASIC System Engineering Research Center, Southeast University, Nanjing, China
swffrog@seu.edu.cn
Shengli, Lu
National ASIC System Engineering Research Center, Southeast University, Nanjing, China

Abstract
A novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage power factor correction (PFC) full-bridge battery charger is proposed in this paper. By connecting a freewheeling transistor in parallel with an input inductor, the PFC cell can operate in the PCCM with a constant duty ratio. Thus, the dc/dc stage can be designed using this constant duty ratio and the restriction on the duty ratio of the PFC cell is eliminated. As a result, the input current distortion is less and the dc bus voltage becomes controllable over the wide output power range of the battery charger. Moreover, the operation principle of the dc/dc stage is designed to be similar to that of a conventional phase-shifted full-bridge converter. Therefore, it is easy to implement. In this paper, the operation of the new converter is explained, and the design considerations of the controller and key parameters are presented. Simulation and experimental results obtained from a 1 kW prototype are given to confirm the operation of the proposed converter.
Keywords
I. INTRODUCTION
In recent years, battery chargers have become a key component for the emergence and acceptance of electrical vehicles. A well-known topology for battery chargers is the two-stage structure. A front stage, which is usually a boost converter, is adopted to perform power factor correction (PFC). A second stage, which is usually a high-efficiency isolated dc/dc converter, is adopted to realize isolation and to control the charging current. Normally, a full-bridge (FB) converter is the most popular topology for the dc/dc converter in battery charger applications (1-5 kW) [1] - [5] .
However, the cost and complexity of the overall two-stage converter are increased because an additional converter must be implemented. Therefore, using a single-stage topology to realize the PFC, isolation and dc/dc conversion sounds more attractive. Several single-stage full-bridge topologies can be found in the literature [6] - [21] . Among them, voltage-fed full-bridge converters [13] - [21] , which can operate with a constant frequency and do not have a voltage overshoot problem across the dc bus, have been widely studied. In [13] - [20] , two inherent duty ratios, the dc/dc stage duty ratio D o and the PFC cell duty ratio D i , are defined. However, D i is restricted by Do , and there are only three discontinuous values of Di when Do is settled. Therefore, distortions of input current are high and the dc bus voltage may become uncontrollable, especially in battery charger applications where the output power varies a lot. In [21] , the restriction of the PFC cell duty ratio is weakened by using two controllers, and the PFC cell duty ratio can vary continuously. Nevertheless, the range of Di should still be limited to implement the control of the output voltage. Thus, input current distortions inevitably appear due to the limited duty ratio band. In addition, two controllers increase the system complexity.
In this paper, a novel pseudo-continuous conduction mode (PCCM) voltage-fed single-stage full-bridge battery charger topology is proposed. The proposed converter can operate with a constant frequency, less input current distortion and a controllable dc bus voltage. These features are realized by using PCCM control in the PFC cell. It is well known that discontinuous conduction mode (DCM) PFC converters suffer from heavy current stresses, which restrict the power range of DCM PFC converters to the low power range (<250W) [22] . Therefore, the continuous conduction mode (CCM) is the most popular modulation method in large power applications such as battery chargers. However, the duty ratio of CCM PFC varies a lot over one ac line cycle which limits the regulation range of the output voltage, as is shown in [21] . In this paper, PCCM control, which can be used to achieve a large output power while having a constant on-time, is adopted here. With a constant on-time, the restriction of the input duty ratio can be eliminated. In addition, the operation of the dc/dc stage is designed to be similar to that of the conventional phase-shifted full-bridge (PSFB) converter which makes it easy to implement.
This paper is organized as follows. The operation of the proposed converter is explained in Section II. The converter characteristics are presented in Section III. Then the design procedure of the proposed battery charger is proposed in Section IV. In Section V, simulation and experimental results obtained from a 1kW single-stage battery charger prototype are given to confirm the operation of the proposed converter. Finally, some conclusions are given in section VI.
II. CONVERTER DESCRIPTION AND OPERATION PRINCIPLE
A circuit diagram of the proposed single-stage full-bridge converter is shown in Fig. 1 . The two bridge legs of the full-bridge converter are composed of four transistors, Q 1 , Q 2 , Q 3 and Q 4 . Q 1 and Q 2 are used to perform the same current-shaping function as the switch in a boost converter. The input inductor L is connected to the Q 1 −Q 2 leg. The power transformer T r , the resonant inductor L r (including the leakage inductor), the output diodes D R1 and D R2 , the output filter inductor L O and the capacitor C O make up a standard full-bridge converter. An energy storage capacitor C F is placed across the primary-side dc bus. The freewheeling power switch Q f is placed in parallel with the input inductor L.
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Proposed PCCM single-stage PFC full-bridge converter for battery charger.
The PFC function can be accomplished by two input boost converters ( Boost-1 , when VI <0; and Boost-2 , when VI >0), as shown in Fig. 2 . The operations of the two boost converters Boost-2 ( VI >0) as an example.
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Two input boost converters provided by the proposed topology.
Key waveforms of the proposed converter are shown in Fig. 3 . da is the duty ratio of Q 2 , which is the PFC cell duty ratio, and the inductor current IL ramps up in the time interval d a T. With the PCCM control, d a is nearly constant over half a line are symmetric. Thus, the operation explanation below takes cycle (typical 100 Hz), and VCF is regulated to be constant. Obviously, VCF is larger than VI . Meanwhile, the operation principle of the dc/dc stage (charging current control stage) is similar to that of the PSFB converter. The duty ratio of Q 4 is equal to that of Q 2 , which is nearly constant. Meanwhile, the gating signals for Q 1 and Q 3 are complimentary to those for Q 2 and Q 4 , respectively. Whenever the top switch of a converter leg is on, the bottom switch in the same leg is off and vice versa. The charge current is controlled by phase-shifting the gating signals of the switches in the Q 1 −Q 2 leg with respect to those of the Q 3 −Q 4 leg. φ is the phase difference between the two legs. Although the transformer primary voltage’s positive and negative halves are asymmetrically placed, the voltage-second balance can be achieved. In addition, the time interval d b T represents the period when the input inductor current IL ramps down and the capacitor C F is charged. This happens when both Q 2 and Q f are off. dc T is the time interval when the switch Q 2 is off, and Q f is on. In this interval, the input inductor current is in the freewheeling mode and is kept constant. It should be noted that:
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Equivalent circuit diagrams of the operation modes that the converter goes through during a switching cycle are shown in Fig. 4 . Since the operation principle of the dc-dc stage is similar to that of the conventional PSFB converter, the output stage, dead-time and duty cycle loss have been neglected here for the sake of simplicity.
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Key waveforms of the proposed converter.
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Equivalent circuits of the proposed converter in different modes.
The details of each operation mode are described as follows:
Mode 1 ( t 0 < t < t 1 ): This mode begins when Q 2 is switched on. During this mode, Q 2 and Q 4 are on. The primary voltage V AB is equal to zero, and the current through the resonant inductor decreases. The transformer primary current during this mode is given by:
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where n is the turns ratio of the transformer and Vo is the battery voltage. No energy has been transferred to the load from C F in this period.
Meanwhile, since Q 2 and D B1 are on, the input voltage remains impressed across the input inductor L and its current ramps up. The current through the input inductor can be expressed as:
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where Vm is the peak input voltage. IREF ( tp ) represents the reference of the input current in the previous switching cycle. This is because the inductor current IL reaches the reference current IREF when Q f is turned on and IL remains constant during dcT .
This mode ends when Q 4 is turned off and Q 3 is turned on. It should be noted that the dead-time is neglected here and the ZVS turn-on of the transistors is achieved in the dead-time.
Mode 2 ( t 1 < t < t 2 ): This mode begins when Q 3 is switched on. Actually, two modes are included during this interval. They are the commutation mode and the energy transfer mode. Since the two modes share the same equivalent circuit, as shown in Fig. 4 (b), and the commutation mode is relatively short compared with the other modes, the two modes are analyzed together in this section. The commutation mode is the time interval [ t 1 < t < t 1a ], as shown in Fig. 3 . This interval is known as the duty cycle loss in the standard PSFB converters. During this interval, the dc bus voltage is completely impressed on the resonant inductor L r and the primary current starts to commutate with a finite slope.
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At t 1a , the commutation of the primary current is finished, and the energy transfer mode begins. The energy is transferred from the dc bus to the output through the transformer. The positive voltage of VCF is impressed across the series combination of the leakage inductor and the equivalent output inductor reflected on the primary side. It should be noted that the magnetizing inductance L m is much larger than the output filter inductance L o and is neglected here [21] . Thus, the current in the transformer primary and the output inductor L o rise during this mode. The transformer primary current can be given by:
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Meanwhile, a positive input voltage continues to be impressed across the input inductor L in Mode 2 , and its current can be expressed as:
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At the end of this mode, Q 2 is turned off.
Mode 3 ( t 2 < t < t 3 ): This mode begins when Q 2 is switched off and Q 1 is switched on. When Q 2 is turned off, the energy-transfer mode ends and the primary current freewheels through Q 1 and Q 3 . The transformer primary current during this mode is given by:
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Meanwhile, this is the capacitor-charging mode ( dbT interval). C F is charged in this interval from the energy stored in L. The voltage across the input inductor L can be given by:
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In addition, VCF is controlled to be larger than Vm . Therefore, the input inductor current starts to ramp down and can be expressed as:
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This mode ends when the input inductor current reaches the reference current, which means that:
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At t = t3 , the freewheeling power switch Q f is turned on and the next mode begins.
Mode 4 ( t 3 < t < t 4 ): This mode begins when Q f is switched on. The primary current freewheels through Q 1 and Q 3 . The transformer primary current during this mode is given by:
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When Q f is switched on, the voltage across the input inductor is approximately equal to zero. Thus, D B1 is reverse biased, and the voltage across D B1 is ( VCF - VI ). Meanwhile, the current through the input inductor does not change.
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At the end of this mode, Q 4 is turned on and Q 3 is turned off.
Mode 5 ( t 4 < t < t 5 ): This mode begins when Q 4 is switched on. The commutation mode is the time interval [ t 4 < t < t 4a ] shown in Fig. 3 . During this interval, the dc bus voltage is completely impressed on the resonant inductor L r and the primary current starts to commutate with a finite slope.
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At t 4a , the commutation of the primary current is finished, and the energy transfer mode begins. The energy is transferred from the dc bus to the output through the transformer. The positive voltage of VCF is impressed across the series combination of the leakage inductor and the equivalent output inductor reflected on the primary side. Thus, the current in the transformer primary and the output inductor L o rises during this mode. The transformer primary current can be given by:
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Meanwhile, a positive input voltage continues to be impressed across the input inductor L in Mode 5 , and its current can be expressed as:
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This mode ends when Q 2 is turned on and another switching sequence begins.
III. FEATURES OF THE PROPOSED CONVERTER
The PCCM converter inherits some characteristics of CCM and DCM operations. They can be illustrated as follows.
Like CCM converters, the PCCM converter has a low inductor current ripple. This is because, according to the operation principle presented in Section II, the inductor current IL is reset to IREF instead of zero in every switching cycle. Meanwhile, the PCCM converter can deliver a larger power by simply boosting the current level of IREF . In addition, the ratio da / db , is almost constant when the output power changes. This is determined by the input and output voltage.
Like DCM converters, the on-time of power the MOSFETs in PCCM converters can be designed to be constant over half of the line cycle. This is realized by introducing a freewheeling period dcT . The design and implementation of the dc-dc stage is very simple when the duty ratio of the PFC cell da is constant. In addition, the output power varies with the duty ratio da . Actually, da can be nearly constant over the entire power range with the control method proposed in Section IV. In addition, the output power is mainly regulated by modulating IREF .
Since the duty ratio of the PFC cell is constant, when compared to other voltage-fed single-stage full-bridge converters, the proposed converter has the following attractive features.
1) There is no restriction of the PFC cell duty ratio which is used to shape the input current in the proposed converter. da is nearly constant in the proposed PCCM converter. Therefore, with proper design of the controller and turns ratio of the transformer, the output voltage (or charging current) can be modulated without inducing input current distortions or an uncontrollable dc bus voltage, which are common problems in previous studies.
2) The turns ratio of the transformer in the proposed converter can be designed so that it is larger than that of the other voltage-fed single-stage full-bridge converters. Since the duty ratio da in the proposed converter is nearly constant, the turns ratio can be designed to be as large as possible. Meanwhile, in other voltage-fed single-stage converters, in order to achieve a high PF, the PFC cell duty ratio band must be designed wide enough, which means the turns ratio should be designed considering the minimum duty ratio in a wide scope. Therefore, the circulating loss can be reduced in the proposed converter.
3) The operation principle of the dc-dc conversion stage is similar to that of a standard phase-shift full-bridge converter. Therefore, it is easy to implement. In addition, the output diodes can be replaced with synchronous rectifier MOSFETs for high output current applications. This is very difficult for converters that operate with non-standard control methods.
4) Single-ended transformer coupled gate driver circuits [23] can be used as the MOSFET gate driver for the proposed converter. Meanwhile, in other voltage-fed single-stage full-bridge converters, the asymmetric driver signals, which vary over every switching cycle, cause saturation of the pulse-transformer. Driver ICs had to be used in [13] - [21] . The driver ICs, especially ones that can provide isolation [24] , are much more expensive than the isolated single-ended transformer-based topology.
IV. DESIGN CONSIDERATIONS
- A. PFC Controller Design
Fig. 5 shows a schematic of the controller of a PFC cell. Irrelevant components are neglected for the sake of simplicity. A voltage control loop is used to regulate the voltage across the dc bus ( V CF ). A current control loop is used to control the reference current to make the inductor current in the same wave shape as and in phase with the input voltage to achieve unity power factor. Also In addition, the power delivered by the converter can be regulated by the current control loop. Unlike the conventional average current controller of a CCM boost PFC converter, the output of the voltage control loop is no longer the input of the current control loop. Therefore, the voltage loop and the current loop can be designed separately.
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PFC controller in the proposed converter.
In the voltage control loop, the voltage error Ve between the dc bus voltage VCF and its reference voltage VREF are fed back to generate the gating signal of Q 2 or Q 1 . The bandwidth of the voltage control loop is designed to be very narrow. As a result, da changes slowly and is thought to be constant over a half line cycle. According to (3) and (6), the peak inductor current can be given as:
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where the line voltage and reference current are sinusoidal, and daT and the input inductor L are constant. Thus, the peak inductor current IL ( t ) naturally follows the sinusoidal line-voltage waveform.
A triangle-trailing-edge modulation, as seen in Fig. 5 , is adopted for Q 2 .
In the current control loop, a reference current IREF is produced by multiplying the input voltage k 1 VI by the desired current amplitude IM .
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where k 1 is a coefficient produced by the controller, and k 1 Vm ≈1. Thus:
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The input voltage VI is implemented by a look-up table with the sensing of the zero cross signal.
The key issue of the current control loop is to obtain IM . As mentioned in Section III, the output power is mainly regulated by modulating IREF . Thus, IM should be proportional to the load current of the PFC section Ibus (which is proportional to the load power since the dc bus voltage is constant). Equation (18) can be rewritten as:
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In order to obtain the desired reference current without sampling the load current Ibus , a dead-zone controller, which was proposed in [25] - [26] , is used in this paper. The voltage ripple across C F is sensed here, since the difference between the instantaneous input power and the constant output power produces a voltage ripple Δ VCF ( t ) at twice the line frequency. The voltage ripple can be expressed as:
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From (20), it can be seen that the load current Ibus is directly proportional to the ripple voltage. In the dead-zone controller, the sampled frequency of the output voltage is fa , and fa is significantly higher than the line frequency. The sampled voltage is then used to calculate the output voltage ripple magnitude Δ VCF [ n ], which is compared with several preset digital dead-zone reference levels to give the corresponding predefined IM .
In order to ensure that the converter operate in the PCCM, which requires dc >0, and based on the power conservation of the converter, the following equation should be satisfied:
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Thus, based on (18) and (19), the predefined IM can be determined as:
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According to the sensed ripple voltage, one of the predefined values of IM will be used. If the dead-zone controller senses a higher voltage ripple, a higher level of IM is chosen. Meanwhile, in order to minimize the power loss caused by Q f , the controller limits the minimum turn-on time of Q f to be less than 5% of the switching period. This is achieved by slightly adjusting k 1 . Therefore, da is almost constant over the entire power range as the ratio da / db does not change when the output power changes. The output power is mainly regulated by modulating IREF .
- B. Design of the Input Inductor L
The inductor-current ripple of the PCCM operation is much smaller than the DCM operation and larger than the CCM operation. Thus, a medium inductor is needed in the PCCM operation. According to [22] , the minimum value of the input inductor for the CCM operation and the maximum value for the DCM operation can be derived as:
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where:
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Meanwhile, the power range of a typical four-step battery charger for a 60V system is shown in Fig. 6 [27] . The value of the input inductor L can be selected based on (23), (24), (25) and Fig. 6 .
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Simplified adaptive four-step lead-acid battery charging profile.
- C. Design of the Turns Ratio n
As previously mentioned, the main feature of the proposed converter is that it has no restriction of the PFC cell duty ratio da . In addition, da is nearly constant over the entire power range. Meanwhile, based on the operation principle presented in Section II, the maximum effective duty ratio for the charging current regulation is determined by da . Thus, for designing the turns ratio of the transformer T r , it is necessary to get the operating range of d a .
According to the instantaneous expressions of the input inductor current, the following relation can be obtained:
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From (19) and (26), the following equation can be deduced:
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According to the analysis in Section IV-A, the duty ratio d a is almost constant over one line cycle. In order to make the theoretical analysis more clear, the duty ratios d a , d b and d c over one line cycle can be plotted in a figure. Firstly, based on the assumption that da remains constant at 0.3, the duty ratios d b and d c can be calculated with (1) and (27). The parameters used for the calculation of db ( t ) in (27) are obtained from the prototype shown in Section V ( Table I ). Then, the values of da ( t ), db ( t ) and dc ( t ) over one half line cycle are plotted in Fig. 7 using Matlab. Actually, the value 0.3 is selected because d a is almost equals to 0.3 (0.28 in practice) in the prototype proposed in Section V. In addition, the calculated curves of d b and d c shown in Fig. 7 are based on the system parameters of the prototype.
MAIN PARAMETERS OF THE PROTOTYPE
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MAIN PARAMETERS OF THE PROTOTYPE
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da(t), db(t) and dc(t) during half line cycle.
In the PCCM operation, it is easy to obtain:
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From (27) and (28), the constraint of da can be deduced as:
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Since the switching period T is much smaller than the line period, the following equation can be calculated:
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Therefore, (29) can be rewritten as:
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Since da is constant over half a line cycle, (31) should be satisfied over half a line cycle. According to (27), the envelope of d b ( t ) shown in Fig. 7 increases with a larger d a . Meanwhile, d b varies during half a line cycle and reaches its maximum value at ωt = π /2 with a constant d a . Thus, the available maximum value of d a can be deduced as:
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For Vin =220Vac, and from (32), it can be concluded that da-max is usually smaller than 0.5 because of the limitation of VCF . Thus, the maximum effective duty ratio for dc/dc regulation is equal to da-max when the phase difference φ is zero.
Meanwhile, the output filter inductor L o is designed to work in the CCM mode. Thus, with a constant primary dc bus voltage, the maximum value of the turns ratio n can be deduced considering the maximum effective duty ratio da-max and the maximum battery voltage Vo-max . The following constraint, based on the standard full-bridge operation, can be placed on n .
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where Vomax can be obtained from Fig. 6 . From (32) and (33), the following relation can be obtained:
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It is well known that a smaller turns ratio means a larger circulating loss in the primary side. Therefore, n should be chosen as large as possible after considering the duty cycle loss and the margin.
- D. Selection of the Dc Bus Voltage VCF
According to (34), a larger dc bus voltage means a larger turns ratio and less circulating loss. However, the value of the dc bus voltage should be less than 450 V to allow the bulk capacitance at the primary-side dc bus to be implemented with standard 450 V electrolytic capacitors. Therefore, a voltage of 420V is chosen considering the voltage ripple.
- E. Implementation of the Control Circuit
Fig. 8 shows a simplified schematic of the power converter and the controller. The single-ended transformer coupled gate driver circuit, which can provide isolation, is also presented in Fig. 8 .
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Simplified schematic of the proposed converter with controllers.
V. SIMULATION AND EXPERIMENTAL VERIFICATIONS
In order to verify the analysis above, a 1 kW voltage-fed single-stage full-bridge battery charger prototype for 60V-90Ah lead-acid batteries is built. The prototype is shown in Fig. 9 . A TMS320F2812 is used to realize the controller and the charging strategy.
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Physical aspect of the developed prototype.
The main parameters of the prototype are selected based on the design considerations shown in Section IV. The detailed parameters are listed in Table I .
At first, the converter is built in Saber simulation software with the parameters in Table I . This is shown in Fig. 10 (a).
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Simulation model and simulation results of the proposed PCCM converter.
Fig. 10 (b) shows the steady-state input voltage and current waveforms of the PCCM voltage-fed single-stage full-bridge converter. The function of power factor correction is well realized.
The efficiency of the proposed converter obtained from the simulations is compared to that from the experiments in Fig. 11 . The efficiency results are simulated for different load conditions which can be obtained from the charging profile shown in Fig. 6 .
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Simulation results of the efficiency.
As shown in Fig. 11 , the maximum error between the simulation and experimental results is less than 2% at the minimum load, and most of the errors are less than 1%. Thus, the simulation results are consistent with the experimental results.
Fig. 12 shows the input voltage VI and inductor current IL of the proposed battery charger at the maximum load. It can be seen that the inductor current ripple of the proposed converter is lower than that of the DCM converter. Thus, compared to the DCM control, the PCCM control increases the current-handling capability at heavy loads and a larger output power can be achieved.
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Experimental waveform of input voltage VI and input inductor current IL.
Fig. 13 shows the input voltage and the input current. The input current is slightly distorted, the PF is 0.986, and the THD is 16.1%. Meanwhile, the PF and the overall efficiency during the charging process are plotted in Fig. 14 . The power factor is kept high over the wide output power range because there is no restriction of the PFC cell duty ratio.
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Experimental waveform of input voltage and current.
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PF and the overall efficiency over entire output power range.
Experimental waveforms of the drive signals of Q 2 , Q f , VG 2 and VG F , over several switching cycles are shown in Fig. 15 (a). Q f is switched off just before Q 2 is switched on. Fig. 15 (b) and (c) show the phase-shifted control of the dc/dc stage. In Fig. 15 (b), the driver signals of Q 1 , Q 2 , Q 3 and Q 4 are shown. The gating signals for Q 1 and Q 3 are complimentary to those for Q 2 and Q 4 , respectively. It can be seen that the duty ratio of Q 2 is about 0.3 and that the Q 1 -Q 2 leg is the leading leg. The driver signals of Q 2 and Q 3 versus the voltage across the primary side and transformer primary current are shown in Fig. 15 (c). The experimental waveforms shown in Fig. 15 verify the operating waveforms in Fig. 3 .
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Experimental waveforms of key drive signals. (a) Drive signals waveform of Q2 and Qf. (b) Drive signals waveform of the two legs. (c) Voltage across primary side VAB and primary current IP waveform versus gate drive signals.
VI. CONCLUSION
A novel PCCM voltage-fed single-stage PFC full-bridge battery charger is proposed in this paper. It combines the attractive features of CCM and DCM converters, which includes the low current ripple through the input inductor and the constant on-time operation. With these features, a large output power can be obtained while, more importantly, the restriction of the PFC cell duty ratio, which leads to input current distortion and an uncontrollable dc bus voltage, is eliminated by the constant on-time operation. The operation principle and features of the proposed charger were explained in detail. Then the design of the new converter was discussed. At last, simulation and experimental results were presented to confirm the feasibility of the battery charger and to verify the converter performance. The PF of the proposed converter is kept higher than 0.97 over the entire power range. In addition, the dc-bus voltage is controlled at 420Vdc, and standard 450 V electrolytic capacitors can be used.
The proposed converter operates without a low-frequency output voltage ripple. Thus, it is also suitable for many other applications. In addition, the overall efficiency of the proposed converter is affected by the freewheeling power switch. If a significant increase in the efficiency is desired, the output diodes can be replaced with synchronous rectifier MOSFETs which is very difficult for other single-stage voltage-fed full-bridge converters.
Acknowledgements
This work was supported by the National Nature Science Foundation of China (51277026), Qing Lan Project and Suzhou Application Basic Research Project (SYG201450).
BIO
Taizhi Zhang received his B.S. degree in Electrical Engineering from Hangzhou Dianzi University, Hangzhou, China, in 2010. He is presently working towards his Ph.D. degree at Southeast University, Nanjing, China. His current research interests include the ac-dc, dc-dc and single-stage PFC converters applied in LED drivers and battery chargers.
Zhipeng Lu received his B.S. degree in Electric Power Systems and Automation from Nanchang University, Nanchang, China, in 2014. His current research interests include the analysis and design of dc–dc converters, battery chargers and single-stage PFC converters.
Qinsong Qian received his Ph.D. degree in Electronics Engineering from Southeast University, Nanjing, China, in 2012. Since 2012, he has been with the School of Electronic Science and Engineering, Southeast University, where he is presently working as a Lecturer. His current research interests include power device design, simulations, and power converters.
Weifeng Sun received his B.S., M.S., and Ph.D. degrees in Electronic Engineering from Southeast University, Nanjing, China, in 2000, 2003, and 2007, respectively. Since 2006, he has been with the School of Electronic Science and Engineering, Southeast University, where he is presently working as the Dean of the School of Electronic Science and Engineering. His current research interests include new power device designs, power ICs, power device models, and power systems.
Shengli Lu received his Ph.D. degree in Information and Physics from Nanjing University, Nanjing, China, in 1994. Since 1994, he has been with the School of Electronic Science and Engineering, Southeast University, Nanjing, China, where he is presently working as a Professor in the National ASIC System Engineering Research Center. His current research interests include VLSIs and application specific integrated circuits.
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