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An Isolated Bidirectional Modular Multilevel DC/DC Converter for Power Electronic Transformer Applications
An Isolated Bidirectional Modular Multilevel DC/DC Converter for Power Electronic Transformer Applications
Journal of Power Electronics. 2016. May, 16(3): 861-871
Copyright © 2016, The Korean Institute Of Power Electronics
  • Received : July 27, 2015
  • Accepted : December 14, 2015
  • Published : May 20, 2016
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About the Authors
Zhaohui, Wang
College of Electrical Engineering, Zhejiang University, Hangzhou, China
Junming, Zhang
College of Electrical Engineering, Zhejiang University, Hangzhou, China
zhangjm@zju.edu.cn
Kuang, Sheng
College of Electrical Engineering, Zhejiang University, Hangzhou, China

Abstract
With high penetration of renewable energies, power electronic transformers (PETs) will be one of the most important infrastructures in the future power delivery and management system. In this study, an isolated bidirectional modular multilevel DC/DC converter is proposed for PET applications. A modular multilevel structure is adopted as switching valves to sustain medium voltages to achieve modular design and high reliability. Only one high-frequency transformer is used in the proposed converter, which significantly simplifies the circuit and galvanic insulation design. A dual-phase-shift modulation strategy is proposed to regulate the output power and achieve a simple voltage balancing control. A down-scaled (2 kW/20 kHz) prototype is constructed to demonstrate the proposed converter and verify the control strategy. The experimental results comply with the theoretical analysis well, with the highest power efficiency reaching 97.6%.
Keywords
I. INTRODUCTION
With considerable progress of DC smart grids and distributed generations, power electronic transformers (PETs) or solid state transformers with low voltage DC bus have gained significant research interest in recent years [1] - [4] .
Until now, several PET structures have been reported in [5] - [15] . Among these configurations, the three-stage structure ( Fig. 1 ) is the most popular one because of its reactive power compensation capability, simple control, and high efficiency [3] . The medium voltage DC (MVDC) bus ( Fig. 1 ) fully decouples the front-end AC/DC stage and the isolated DC/DC stage, while providing the possibility for future MVDC distribution. Voltage conversion and galvanic isolation are realized by the DC/DC stage, which is the main challenge in a PET converter to achieve high efficiency and high power density of the whole converter [16] .
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Typical circuit structure of the three-stage PET converter.
Therefore, this study focuses on the DC/DC stage. As shown in Fig. 1 , for the 10 kV AC grid, the MVDC bus will reach 15 kV or higher, which is much greater than the voltage rating of present power semiconductor devices. Ultrahigh voltage rating silicon carbide (SiC) power devices show great advantages in this application [17] , [18] , although they are still far from commercial availability. The voltage issue can also be addressed by connecting low voltage rating power devices in series [19] ; however, the voltage balance among these power devices is a great challenge, especially during dynamic transient [3] .
Another way to sustain medium voltage is adopting multilevel topologies with low voltage rating power devices. The input–series–output–parallel structure is one of the most popular topologies [15] , [16] , [20] - [23] . The inputs of low voltage power cells are connected in series to sustain the medium DC voltage. Each power cell requires a high-frequency (HF) transformer to achieve galvanic isolation and voltage conversion. All HF transformers are usually immersed in an oil tank in practical applications to meet the requirements of galvanic isolation and heat dissipation [14] . The structure inside the oil tank is complex and fabricating cost is high. Meanwhile, each transformer requires four or more terminals outside the oil tank, which makes the assembly more difficult. Therefore, a single HF transformer is preferred for such applications.
The modular multilevel structure can also sustain high input voltage with low voltage power devices, which has many advantages for high voltage applications, like modular design, high voltage scalability, simple redundancy design, high reliability, and controllable voltage slope (d v /d t ) [24] , [25] . Recently, a front-to-front modular multilevel converter is proposed to interconnect an HVDC grid and a MVDC grid [26] - [29] . Only one transformer is used in the converter to realize voltage matching and power transfer, which considerably simplifies the circuit and galvanic insulation design. A two-level or quasi-two-level modulation method is proposed to improve core utilization factor of the HF transformer [28] , [29] . However, realizing voltage balancing control with the two-level or quasi-two-level modulation method is quite difficult.
Regarding the previously mentioned issues, a new isolated bidirectional modular multilevel DC/DC converter for PET applications is proposed in this study. A dual-phase-shift control strategy is proposed to regulate output power and achieve simple voltage balancing control. This study mainly discusses the characteristics of the proposed converter and the related control strategy. This paper is organized as follows: Section II presents the converter characteristics and operation principle. In Section III, the voltage balancing strategy is discussed. In Section IV, a down-scaled prototype is constructed to verify the proposed converter, and key experimental results are presented. Finally, the conclusion is given in Section V.
II. PRINCIPLE OF OPERATION
The circuit diagram of the proposed modular multilevel DC/DC converter is shown in Fig. 2 [30] . The primary H-bridge consists of two legs as switching valves. Each leg is composed of an upper arm, a lower arm, and a coupled inductor. A number of low voltage submodules (SMs) are cascaded to form an arm. Each SM is a half-bridge circuit with a voltage clamping capacitor. A coupled inductor is used to withstand instant voltage difference between the bus voltage and arm output voltage, and the inductor serves as a buffer impedance. In the secondary side, an active full bridge (H-bridge) circuit is adopted for bidirectional power flow.
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Diagram of the proposed DC/DC converter.
With the modular multilevel structure, only one HF transformer is required to achieve voltage matching, galvanic isolation, and power exchange between the MVDC bus and LVDC bus; thus, the transformer can be easily immersed into an oil tank with a simple structure. As a result, assembly cost will be reduced and a smaller volume can be achieved. Meanwhile, the modular multilevel structure has high voltage modulation flexibility and low d v /d t can be achieved, which can further benefit the galvanic insulation design inside the transformer.
In the proposed topology, a coupled inductor instead of separate inductors is adopted in each leg for the following considerations: (1) The phase shift control for the traditional phase shifted dual active bridge (PS-DAB) converter is adopted for output power regulation to fully utilize the leakage inductance of transformer T1. Thus, with the coupled inductors, only their leakage inductances will be included in the power path, which are usually small and have a weak influence on output power control. As a result, the design of the coupled inductor and transformer can be decoupled. (2) The coupled inductors can guarantee that the primary winding current i Lk is equally distributed into the upper and lower arms, to simplify voltage balancing control. (3) The magnetizing inductance of the coupled inductor serves as the arm inductance. High magnetizing inductance can be designed for circulating current ripple reduction and circuit protection, which does not affect the output power capability. For simplicity, leakage inductances of the coupled inductors are ignored in the following analysis.
Key steady-state voltage waveforms of the proposed converter are shown in Fig. 3 . Output power is regulated by the phase shift angle Φ between the primary H-bridge output voltage v ab and secondary H-bridge output voltage v s , which is the same as that in a PS-DAB converter [31] , [32] . In Fig. 3 , v arm i is the output voltage of each arm and v sm ij is the SM output voltage, which is the voltage across the low-side device in each SM, as shown in Fig. 2 . Subscript i ∈{1,2,3,4} denotes the arm number and subscript j ∈{1,2… N } denotes the SM position in an arm. N is the total SM numbers in each arm. The duty cycle of each SM output voltage is 50% by ignoring dead time. Given the symmetrical structure, only the SM output voltages in ARM2 are presented in Fig. 3 as an example.
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Key steady-state voltage waveforms.
In any switching cycle, one SM output voltage is lagging phase-shifted from the others in the same arm with angle θ, which is proposed for the voltage balancing control. This will be further elaborated in the next section. In the following analysis, θ is defined as the voltage balancing angle and Φ as the power control angle. When all SM voltages are balanced, the medium voltage V MV is evenly distributed across the SM capacitors, and steady-state capacitor voltage V Csm ij is equivalent to V MV / N .
Because of the phase-shifted SM output voltage, primary voltage v ab slightly differs from a square waveform. By ignoring the voltage drop across the power devices, the magnitude of v ab is reduced from V MV to ( N − 2) V MV / N during 0 to θ and π to π + θ, as shown in Fig. 3 . The magnitude of v s is just the output voltage V LV . According to the power control angle Φ and voltage balancing angle θ, the proposed DC/DC converter mainly has three operation modes, namely, Mode I (Φ ≥ θ), Mode II (0 ≤ Φ < θ), and Mode III (Φ < 0), where θ is a fixed angle between 0 and 0.5π. Key steady-state waveforms under different operation modes are shown in Figs. 4 to 6 .
Mode I: Φ ≥ θ
Fig. 4 shows the main waveforms in this operation mode. The voltage difference between voltage v ab and primary-referred secondary voltage v s applies across the leakage inductance Lk , and determines inductor current i Lk .
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Key steady-state waveforms in Mode I.
Based on the instant voltage magnitude of v ab and v s , instant inductor current i Lk as a function of φ is derived as:
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where
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and G is the primary-referred DC voltage gain. n is the transformer primary-to-secondary turns ratio. ω is the angular switching frequency in rad/s. I 0 , I θ , and I Φ are the inductor currents at φ = 0, φ = θ, and φ = Φ, respectively.
Given the symmetrical operation, at the end of the half switching cycle, we can obtain I 0 = − I π under a steady-state operation. Thus, from (1) to (3), inductor currents I 0 , I θ , and I Φ can be derived as:
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Mode II: 0 ≤ Φ < θ
When the power-control angle Φ decreases to less than θ but greater than zero, the converter will operate in Mode II. The main waveforms in this mode are shown in Fig. 5 .
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Key steady-state waveforms in Mode II.
Similar to the analysis in Mode I, instant inductor current i Lk can be derived according to instant voltages v ab and v s .
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With the relationship of I 0 = − I π , inductor currents I 0 , I Φ , and I θ can be derived as:
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Mode III: −π + θ ≤ Φ < 0
When power control angle Φ is further reduced to a negative value, the converter operates in backward mode and energy is transferred from the low voltage side to the medium voltage side. The key waveforms are shown in Fig. 6 .
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Key steady-state waveforms in Mode III.
Similarly, instant inductor current i Lk can be derived according to instant voltages v ab and v s .
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With the relationship of I 0 = − I π , inductor currents I 0 , I θ , and I π + Φ can be derived as:
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With (1)–(12), primary winding current i Lk in a complete switching cycle under different operation modes can be attained.
By assuming a unitary power conversion efficiency, the converter output power is the output power of the primary H-bridge, which can be addressed by averaging the instantaneous power during the half switching period from 0 to π.
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By substituting instant voltage v ab and instant current i Lk under different operation modes into (13), the converter output power in the full power range can be written as (14).
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For simplicity, the output power is normalized to a power base P b , which is given as:
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Based on (14) and (15), the normalized output power of the proposed converter is plotted as the solid curves in Fig. 7 with θ = 0.1π and four SMs in each arm, that is, N = 4. For comparison, the normalized output power of the conventional PS-DAB converter is also plotted in Fig. 7 as dashed curves, which is a special case when the voltage balancing angle θ decreases to zero. The voltage v ab differs from a square waveform; thus, the output power curves slightly deviate from that of a conventional PS-DAB converter. The maximum forward and backward output power occur at Φ = 0.5π + θ/ N and Φ = −0.5π + θ/ N , respectively. Also, the converter outputs zero power at Φ 0 , which is given as:
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Normalized output power versus phase shift angle Φ.
III. SUBMODULE VOLTAGE BALANCING CONTROL
The capacitor voltage of each SM must be balanced to ensure reliable operation of the proposed converter. If all active switches in the primary side are turned on/off simultaneously, the capacitor voltage will deviate from each other because of circuit tolerance. Circuit tolerance can lead to nonsynchronous PWM signals between different SMs, asymmetrical PWM signals for the high-side switch and low-side switch in each SM, different switching transients, different SM capacitance, and so on. All these factors affect the SM voltage. Therefore, in this study, an additional phase shift control strategy is proposed for voltage balancing control.
Each SM mainly has two states, that is, inserted into an arm and bypassed from an arm ( Table I ). When the high-side switch ( Th or Dh ) is turned on, SM will be inserted into the related arm. Arm current will flow through the SM capacitor, charging or discharging the capacitor. Hence, the integral of the arm current over a switching period when the high-side switch is turned on will determine the SM voltage state.
SM STATE ANALYSIS
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SM STATE ANALYSIS
Given the symmetrical structure, ARM2 is still taken as an example to illustrate the proposed voltage balancing control mechanism. Key waveforms of ARM2 are shown in Fig. 8 . In each switching cycle, one SM output voltage is lagging phase-shifted from the others with angle θ.
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Key steady-state waveforms of ARM2.
For a non-phase-shifted (NPS)-SM, the capacitor net charge in one switching cycle is the integral of the arm current from 0 to π, which is given in (17), as shown in Fig. 8 .
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For a lagging-phase-shifted (LPS)-SM, the capacitor net charge in one switching cycle is given in (18), which is the integral of the arm current from θ to π + θ.
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The arm current mainly consists of a circulating current and half of the primary winding current i Lk , which are given in (19) and (20) with direction shown in Fig. 2 .
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where I cir1 and I cir2 are the circulating currents in each leg by neglecting their ripple components, which can be derived from the converter output power.
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By substituting the instant arm current into (17), the NPS-SM net charge Δ Q C1 in one switching cycle under different operation modes can be derived as (22).
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From (18), the LPS-SM net charge Δ Q C2 in one switching cycle under different operation modes can be derived as (23), which is equal to N − 1 times Δ Q C1 with opposite polarity.
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For simplicity, SM capacitor net charges written in (22) and (23) are normalized to a net charge base Δ Q Cb .
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The normalized SM capacitor net charge in one switching cycle versus the power control angle Φ at θ = 0.1π is plotted in Fig. 9 . Four SMs in each arm are still used for analysis. The minimum ΔQ C1 and maximum ΔQ C2 occur at Φ = θ/2, which can be derived from (22). If the net charge is positive, the SM capacitor will be charged after one switching cycle; otherwise, it will be discharged. As illustrated in Fig. 9 , the voltage gain G has a direct effect on the net charge value. At high voltage gain, the curves will cross the zero line, which means the SM capacitor will change from charging state to discharging state when output power changes, or vice versa. High voltage gain will complicate the voltage balancing control, especially at the zero net charge points Φ 1 –Φ 4 , where the net charge is zero and SM voltages will be uncontrollable.
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Normalized SM capacitor net charge versus power-control angle Φ.
In order to simply the voltage balancing control, it is better that the curves in Fig. 9 do not change their polarities during the entire power range, which indicates a critical voltage gain with a given voltage balancing angle θ. By setting the minimum value of Δ Q C1 above zero or the maximum value of Δ Q C2 below zero, the critical voltage gain can be derived as (25) and plotted in Fig. 10 .
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Critical voltage gain at different voltage-balance angles θ.
When the voltage gain is less than the critical value, the net charge Δ Q C1 will always be above zero and Δ Q C2 will always be below zero. Thus, with a given angle θ, the capacitor in NPS-SM will be charged and the capacitor in LPS-SM will be discharged after one switching cycle during the whole power range. With this characteristic, the output voltage of the SM with the maximum voltage can be simply lagging phase-shifted with angle θ to discharge the capacitor without detecting the arm current direction, which is usually required in the traditional modular multilevel converter (MMC) [24] , [25] .
Fig. 11 shows the dynamic voltage balancing process based on the above analysis, which takes four SMs in each arm as examples. The capacitor voltage in each SM realizes once dynamic balance in N switching cycles, which include N − 1 charging cycles and one discharging cycle as theoretically determined by (23).
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Dynamic voltage balancing process.
With the proposed voltage balancing strategy, the frequency of AC voltage applied to the isolation transformer is the same as the switching frequency, and a high isolation frequency can be achieved. In addition, the SM capacitor in the proposed converter is a kind of voltage clamping capacitor instead of an energy storage capacitor in the traditional MMC. As shown in the shadowed area in Fig. 8 , most of the positive current integral will cancel out with the negative component, and the capacitor net charge in one switching cycle will be small, making the voltage ripple also small. Therefore, the required SM capacitance is small with a given voltage ripple.
In summary, the power regulation method for the proposed converter is similar to a conventional PS-DAB converter. The voltage balancing control for the cascaded SMs is realized by a simple phase-shift scheme between the SM output voltages without arm current detection.
IV. EXPERIMENTAL VERIFICATION
A down-scaled prototype is constructed to demonstrate the proposed modular multilevel DC/DC structure. Discrete SiC MOSFETs (C2M0080120D from Cree) are adopted as active switches to achieve high isolation frequency and low switching loss. Meanwhile, the intrinsic diodes of SiC MOSFETs show a small reverse recovery current [33] . Thus, even under hard-switching operations, the active devices will not fail to work.
The key parameters of the prototype are listed in Table II . Based on the above analysis, voltage balancing angle θ is fixed to 0.1π. The voltage gain at the rated condition is set at 0.83 to meet the critical voltage gain requirement given in (25). Also, this voltage gain allows voltage disturbance in both voltage buses. The switching frequency is designed at 20 kHz to avoid the acoustic noise. An EE-type ferrite core is used for the HF transformer, and Litz wires are adopted for transformer windings to reduce copper loss.
KEY PROTOTYPE PARAMETERS
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KEY PROTOTYPE PARAMETERS
First, the converter under different operation modes is tested, and the experimental waveforms are presented in Fig. 12 . Output power is 2 kW in Mode I, 0.25 kW in Mode II, and −2 kW in Mode III. The experimental results match the theoretical analysis well, which means the converter works well with the proposed dual-phase-shift method. The phase shift angle Φ at the rated forward power is greater than that at the rated backward power, which complies with the theoretical output power curves shown in Fig. 7 . Because of voltage balancing control, the primary H-bridge outputs a multilevel voltage with 50% duty cycle, which is different from the traditional PS-DAB converter.
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Key waveforms in different operation modes.
The output voltages of each arm at the rated forward power are given in Fig. 13 , which are the same as the theoretical waveforms shown in Fig. 3 . The magnitude of the upper arm voltages and lower arm voltages is close to each other.
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Arm output voltages at the rated forward power.
Given the symmetrical structure, only SM voltages in ARM2 are measured for verification, as shown in Fig. 14 . The steady-state SM capacitor voltage is 150 V, which is the same as the theoretical value V MV / N . The voltage rippls are small. Figs. 13 and 14 indicate that all SM voltages are well-balanced with the proposed dual-phase-shift control strategy.
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SM voltages in ARM2 at the rated forward power.
Fig. 15 shows the circulating currents in each leg at the rated condition. The two legs share the same DC current either at the rated forward power or at the rated backward power. As shown in Fig. 15 (a), the circulating currents are positive at the rated forward power, which means that energy is transferred from the medium voltage side to the low voltage side. At the rated backward power, the polarity of the circulating currents changes to negative, as shown in Fig. 15 (b).
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Circulating current waveforms.
Because of the coupled inductor in each leg, the primary winding current i Lk is equally distributed into the upper and lower arms, which can be verified by the measured waveforms shown in Fig. 16 . Given the symmetrical structure, only the waveforms of ARM1 and ARM2 are presented here. Obvious DC component can be found in the arm current.
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Arm current waveforms.
Fig. 17 shows the dynamic SM voltage balancing mechanism. For clarity, the SM capacitor voltage ripple (AC component) instead of steady-state voltage is measured. Fig. 17 show the key waveforms at the rated forward power and rated backward power. From the waveforms in the dashed area, SM output voltage is lagging phase-shifted with angle θ compared with the arm output voltage. In both forward and backward modes, the LPS-SM voltage decreases and the capacitor is discharged, which confirms the theoretical analysis shown in Figs. 9 and 11 . When the SM capacitor voltage decreases and is not the maximum one in the same arm, the SM output voltage will not be phase-shifted, and the capacitor is charged. This simple method ensures that all capacitor voltages are balanced. Different from the theoretical waveforms in Fig. 11 , SM output voltage may be successively lagging phase-shifted for more than one switching cycle in practical converters, as shown in Fig. 17 (a), which is mainly caused by voltage sampling delays, noise, and sampling errors.
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The dynamic voltage balancing process.
The dynamic response performance of the proposed converter is also tested, as shown in Fig. 18 . In our setup, the low voltage DC bus is sampled for closed-loop control with a simple PI controller. Fig. 18 (a) presents the input and output waveforms when the output power steps are from –1 kW to 1 kW. When the power source at the low voltage side is turned off, the converter will draw high power from the medium voltage input side to maintain the output voltage. SM voltages in ARM2 during the load step transient are shown in Fig. 18 (b). After a small voltage oscillation, all SM voltages immediately return to their steady-state value. SM voltages are balanced not only in steady-state operations, but also during dynamic transient, which validates the proposed voltage balancing control strategy.
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Dynamic performance at load transient.
Fig. 19 shows the submodule voltages in ARM2 when disabling the control method at time t 1 . Once the voltage balancing method is disabled, the submodule voltages deviate from each other immediately. After a short transient, the converter fails to work.
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SM voltages in ARM2 without voltage balancing control.
The experimental results show that the proposed converter can achieve bidirectional power flow and HF isolation. The proposed voltage balancing strategy guarantees that the capacitor in each SM share a uniform voltage to achieve high input voltage with low voltage power devices. Based on the prototype, the highest measured efficiency reaches 97.6% at approximately 1 kW.
V. CONCLUSIONS
In this study, an isolated bidirectional modular multilevel DC/DC converter with a single HF transformer for PET applications is proposed and analyzed. A modular multilevel structure is adopted to achieve high input voltage and high operation reliability with low voltage power devices. A single transformer dramatically simplifies its galvanic insulation design and circuit structure.
A dual-phase-shift control strategy is proposed to regulate output power and ensure voltage balance among the cascaded submodules to achieve high power efficiency. In addition, the leakage inductance of the HF transformer can be fully utilized.
A down-scaled prototype is constructed to verify the proposed topology and control method. All submodule voltages are well-balanced with the proposed dual-phase-shift method. The experimental results at steady-state and dynamic transient are presented in this study, which are in good agreement with the theoretical analysis.
Acknowledgements
This work was supported by the National Nature Science Foundation of China under grant 51277161.
BIO
Zhaohui Wang was born in Hebei, China. He received his B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China, where he is currently working toward his Ph.D. degree in electrical engineering. His research interests mainly include high-efficiency DC/DC converters, high-efficiency PFC, multichannel LED driver, modular multilevel converter, and wide bandgap semiconductors.
Junming Zhang received his B.S., M.S., and Ph.D. degrees in electrical engineering from Zhejiang University, Hangzhou, China, in 1996, 2000, and 2004, respectively. He is currently a professor at the College of Electrical Engineering, Zhejiang University. From 2010 to 2011, he was a visiting scholar at the Department of Electrical and Computer Engineering, Michigan State University, East Lansing, MI, USA. His research interests include power electronic system integrations, power management, and high-efficiency converters.
Kuang Sheng received his B.S. degree in electrical engineering from Zhejiang University, Hangzhou, China in 1995 and his Ph.D. degree in electrical engineering from Heriot-Watt University, Edinburgh, UK in 1999. He was a postdoctoral research associate at Cambridge University, Cambridge, UK between 1999 and 2002. He was an assistant professor and a tenured professor from 2002 to 2009 at Rutgers University, New Brunswick, NJ, USA. He led a team that reported the first power IC on SiC. He is currently at Zhejiang University as a tenured professor. He has published approximately 90 technical papers in international journals and conferences and currently holds 12 patents. His research interests include all aspects of power semiconductor devices and ICs on SiC and Si. Dr. Sheng serves as an associate editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS and the IEEE TRANSACTIONS ON INDUSTRIAL APPLICATIONS.
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