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An Improved Analytical Model for Predicting the Switching Performance of SiC MOSFETs
An Improved Analytical Model for Predicting the Switching Performance of SiC MOSFETs
Journal of Power Electronics. 2016. Jan, 16(1): 374-387
Copyright © 2016, The Korean Institute Of Power Electronics
  • Received : June 03, 2015
  • Accepted : August 10, 2015
  • Published : January 20, 2016
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About the Authors
Mei, Liang
School of Electrical and Engineering, Beijing Jiaotong University, Beijing, China
12117352@bjtu.edu.cn
Trillion Q., Zheng
School of Electrical and Engineering, Beijing Jiaotong University, Beijing, China
Yan, Li
School of Electrical and Engineering, Beijing Jiaotong University, Beijing, China

Abstract
This paper derives an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of SiC MOSFETs. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of the trans-conductance. The turn-on process and the turn-off process are illustrated in detail, and equivalent circuits are derived and solved for each switching transition. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. Note that switching losses calculated based on experiments are imprecise, because the energy of the junction capacitances is not properly disposed. Finally, the proposed analytical model is utilized to account for the effects of parasitic elements on the switching performance of a SiC MOSFET, and the circuit design rules for high frequency circuits are given.
Keywords
I. INTRODUCTION
The silicon carbide (SiC) MOSFET is a promising candidate for next generation power devices. It is featured by much higher blocking voltages, lower on-state resistance, higher switching speeds and higher thermal conductivity than conventional silicon (Si) devices [1] - [5] . In addition, a SiC MOSFET is capability of operation under higher density power conversion [6] . The switching frequency has been continuously pushed up to the megahertz range to reduce the size of the passive components [7] , [8] . However, as the switching loss increases and the effects of parasitic elements on the switching performance become intensified, there is a further increase in the switching frequency. In order to take full advantage of a SiC MOSFET, it is necessary to estimate the switching loss and to analyze the effects of the parasitic elements on the switching performance of the SiC MOSFET for optimization.
Investigation into this issue can be classified into three categories. One way to study this is by measuring experimental switching waveforms [9] - [14] . Some device manufactures provide the switching energy dissipation in a datasheet by capturing the experimental switching waveforms in a double-pulse-test circuit. However, this method needs oscilloscope probes that have a sufficient bandwidth to insure the high fidelity of the switching waveforms, especially for testing high switching-speed devices [15] , [16] . On the other hand, the experimental switching waveforms are impacted by the parasitic inductances of particular PCB traces and the characteristics of free-wheeling diodes. Therefore, switching loss based on different experimental platforms may be different. Not only that, this method only provides experimental switching waveforms under the influence of parasitic elements. It does not provide explanations of the influence mechanism of the parasitic elements through measurement results.
In [17] - [20] , a method for making simulation models, such as pspice models or saber models, is presented. For SiC MOSFETs, Cree has published LTspice models with the parasitic inductances in the package. The simulation model can be combined with an external circuit including the parasitic inductances of the PCB traces to calculate the switching loss and to obtain the switching waveforms under the influence of the parasitic elements. However, like the experimental method, this simulation method does not give the influence mechanism.
Analytical models are set up based on the mathematical methods in [21] - [30] . The piecewise linear model is the most simple and popular analytical model [21] , [22] . However, the parasitic inductances and junction capacitances are not taken into consideration. In [32] and [33] , it is shown that the nonlinear junction capacitances of power devices are critical for the switching transition. As a result they should be fully considered in the modeling and switching transient analysis, especially for high-frequency applications. In addition, the parasitic inductances are also very significant for the switching transient analysis in high-frequency applications [23] . Therefore, the results of the piecewise linear model cannot match well with the experimental results. In [23] - [30] , analytical models considering the parasitic inductances and junction capacitances are presented. The equivalent circuits for each switching transition can be derived and solved. Then, the switching waveforms and switching loss can be calculated, and the effects of the parasitic elements on the switching performance can be analyzed. Some analytical models are designed to predict the switching performance of low-voltage MOSFETs [24] - [29] . The switching processes of a SiC MOSFET, which is a high voltage device, are different from the low-voltage devices usually operating at voltages lower than 40V. The drain-source voltage v DS of low-voltage devices drops to 0V before the drain current i D reaches I o during the turn-on transition, and i D can reach 0A before v DS reaches V DC during the turn-off transition [25] , [31] . In general, these conditions will not happen to high voltage devices. The analytical models from [23] and [30] are for high voltage devices. In [23] and [30] , the junction capacitances and trans-conductance are treated as constants, and the nonlinearity of these two elements is not considered. Therefore, these analytical models are also imprecise. In [30] , the common source parasitic inductance is not considered, which is shared by the power loop and the gate loop. It plays a different role with the power loop parasitic inductances. In addition, [31] shows that the switching loss of a Cascode GaN HEMT, which are derived from terminal waveforms based on experiments, are imprecise. This is due to the fact that the energy in the junction capacitances is not dealt with well. However, this issue is not addressed or analyzed in any of the studies concerning SiC MOSFETs.
The objective of this paper is to estimate the switching loss and analyze the effects of the parasitic elements on the switching performance of a SiC MOSFET with an improved analytical model. The proposed analytical model considers the parasitic inductances, the nonlinearity of the junction capacitances and the nonlinearity of trans-conductance. The switching processes are illustrated in detail, and the equivalent circuits are derived and solved during the switching transition. This paper is organized as follows. The proposed analytical model is established in Section II. Verification of the proposed analytical model of a SiC MOSFET is in Section III. The effects of the parasitic elements on the switching performance of a SiC MOSFET are illustrated in Section IV. Some conclusions are given in Section V.
II. ANALYSIS OF SWITCHING PROCESSES
To analyze the switching processes of a SiC MOSFET, a double-pulse-test circuit is used as an example. The employed double-pulse-test circuit considering the parasitic elements is shown in Fig. 1 . The input voltage source V DC is constant, and the output current I o is constant. The parasitic elements in the package of the SiC MOSFET Q 1 are the gate-source capacitance C GS , the gate-drain capacitance C GD , the drain-source capacitance C DS , the gate inductance L G1 , the drain inductance L D1 , the source inductance L S1 , and the internal gate drive resistance R G1 . The parasitic elements in the package of the freewheeling diode D are the junction capacitance C F , the cathode inductance L C1 , the anode inductance L A1 , and the on-state resistance R F . A SiC JBS diode is employed as the freewheeling diode, which does not have the reverse recovery charge Q rr . L C2 , L A2 , L G2 , L D2 , L S2 , and L S3 represent the interconnection parasitic inductances of the PCB traces. In all of the parasitic inductances, L S1 and L S2 are the common source inductances shared by the power loop and the gate drive loop. R G2 represents the external gate drive resistance. The gate signal v P flips between V SS and V GS , and V SS is a negative value. The circuit in Fig. 1 is also suitable for analyzing the device performance during the switching transitions for other bridge configuration-based topologies, such as boost, buck-boost, half bridge, and full bridge.
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Double-pulse-test circuit considering parasitic elements.
- A. Turn-on Switching Transition
Before Q 1 is turned on, the output current I o flows through D , and the input voltage source V DC is applied to Q 1 . The turn-on switching transition can be divided into four stages, which are analyzed as follows. The complete switching waveforms are shown in the next section.
1) Stage 1, Turn-on Delay Time: When V GS is applied, the gate current i G charges C GS and C GD . C GS is much larger than C GD . Thus, the majority of the gate current charges C GS . Since the gate-source voltage v GS does not reach the threshold voltage V th , Q 1 is cut-off and almost no drain current flows into Q 1 . The equivalent circuit of this stage is shown in Fig. 2 (a). During this stage, the circuit equations can be expressed as:
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where R G = R G1 + R G2 , L G = L G1 + L G2 , and L CS = L S1 + L S2 . The gate-source voltage v GS can be solved by the iterative method presented concretely in the next stage, and the coefficient matrixes are shown in Appendix.
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Equivalent circuits for the turn-on transition. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4.
This stage ends when v GS reaches V th . Since Q 1 is not activated, there is no switching loss during this stage.
2) Stage 2, Current Rising Time: When v GS reaches V th , the channel of Q 1 conducts, and the channel current i CH , which is controlled by v GS , increases. During this stage, I o transfers from D to Q 1 . The rising drain current i D and the falling forward current i F induce voltage drops across the parasitic inductances. This leads to C GD and C DS discharging through the channel of Q 1 , and the drain-source voltage v DS falling. The equivalent circuit is shown in Fig. 2 (b), where Q 1 is modelled as a dependent current source controlled by v GS . The expression of this source is given by:
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where g f is the trans-conductance of Q 1 . The circuit equations can be expressed as:
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where L P is the sum of the power loop parasitic inductances, L P = L C1 + L C2 + L A1 + L A2 + L D1 + L D2 + L S1 + L S2 + L S3 , and V F is the forward voltage of D .
Since there are four independent state variables in Equs. (4)-(8), it is difficult to derive the time domain solutions without simplification. In order to enhance the accuracy of this analytical model, the iterative method is employed. Equs. (4)-(8) are transformed into:
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where X =[ i G v GS i D v DS v F ] T , and A and B are the coefficient matrixes, which are shown in the Appendix. Afterwards, Equs. (4)–(8) can be solved according to the following formula:
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where n=1, 2, 3…, and Δ t is the calculation time step. All of the variables can be solved as Equ. (10).
This stage ends when the drain current i D reaches I o . During this stage, the channel of Q 1 conducts, and a portion of the energy stored in C GD and C DS is dissipated through the channel. Therefore, the turn-on loss can be calculated as:
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where, t n1 is the time of stage 1, and t n2 is the time of stage 1 and stage 2.
3) Stage 3, Voltage Falling Time: When i D reaches I o , D is able to block the voltage, Q 1 need to assume I o , and the additional current is charging C F of the freewheeling diode. v DS eventually decreases and C GD and C DS continue to discharge through the channel of Q 1 . i D may have a ringing because of oscillations between L P and C F . The equivalent circuit is shown in Fig. 2 (c), and the circuit equations different from stage 2 can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.
This stage ends when v DS decreases to i D · R on , where R on is the on-state resistance of Q 1 . At this point, the drain-source voltage and drain current transition are over. During this stage, the turn-on loss is the same as that of the previous stage, and it can be calculated as:
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where t n3 is the time of stage 1, stage 2, and stage 3.
4) Stage 4, Gate Remaining Charging Time: Once v DS reaches i D · R on , v GS continues to increase until it reaches V GS . The channel current i CH is no longer controlled by v GS , and ultimately goes back to I o . The equivalent circuit is shown in Fig. 2 (d), where Q 1 is modelled as the on-state resistance. The circuit equations different from stage 2 and stage 3 can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.
During this stage, the drain-source voltage and the drain current are almost steady. Therefore, there is no turn-on loss.
- B. Turn-off Switching Transition
Before Q 1 is turned off, the output current I o flows through Q 1 , and the input voltage source V DC is applied to D . The turn-off switching transition can be divided into four stages, which are analyzed as follows. The complete waveforms are shown in the next Section.
1) Stage 1, Turn-off Delay Time: When V SS is applied, C GS and C GD discharge, and v GS decreases. However, when Q 1 is still in the on-state, I o keeps flowing through the channel of Q 1 . The equivalent circuit of this stage is shown in Fig. 3 (a), and the circuit equations can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.
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Equivalent circuits for the turn-off transition (a) stage 1, (b) stage 2, (c) stage 3, and (d) stage 4.
This stage ends when v GS reaches V mil , which is given as Equ. (17). During this stage, Q 1 is still turned on. As a result, there is no turn-off loss.
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2) Stage 2, Voltage Rising Time: During this stage, v DS increases, and i D charges C GD and C DS . i CH decreases because C GD and C DS need the charging current, and C F need to release energy. Therefore, v GS continues to decrease due to its dependent relation with i CH . The equivalent circuit is shown in Fig. 3 (b), where Q 1 is modelled as a dependent current source. The circuit equations can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.
This stage ends when the forward voltage v F of D decreases to – V F . Then, D is in the on-state. During this stage, the turn-off loss of Q 1 can be calculated as:
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where, t f1 is the time of stage 1, and t f2 is the time of stage 1 and stage 2.
3) Stage 3, Current Falling Time: During this stage, v GS and i CH decrease. v DS continues to increase, and C GD and C DS are charged. The rapidly changing currents i D and i F induce voltage drops across the parasitic inductances, which eventually incurs a voltage overshoot on v DS . The equivalent circuit is shown in Fig. 3 (c), and the circuit equations different from stage 2 can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix.
This stage ends when i CH reaches zero, and v GS reaches V th . During this stage, the turn-off loss can be calculated as:
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where, t f3 is the time of stage 1, stage 2, and stage 3.
4) Stage 4, Gate Remaining Discharging Time: When v GS drops below V th , the channel of Q 1 is totally shut down. Then v GS continues to decrease until it reaches V ss . During this stage, the drain-source voltage and the drain current have a ringing because the parasitic inductances oscillate with C GD and C DS . The equivalent circuit is shown in Fig. 3 (d), and the circuit equations different from stage 2 and stage 3 can be expressed as:
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The iterative method is also employed in this stage, and the coefficient matrixes are shown in the Appendix. As the ringing dissipation is very small and can be neglected, this stage has no turn-off loss.
III. VERIFICATION OF THE ANALYTICAL MODEL
In this part, experiments based on a double-pulse-test circuit are carried out to validate the proposed analytical model. In the double-pulse-test circuit, the device under examination is a 1200V SiC MOSFET C2M0080120D from CREE, Inc. The freewheeling diode is a 1200V SiC JBS diode C4D20120A with no reverse recovery charge. Note that the proposed analytical model is suitable for not only 1200V SiC MOSFETs from CREE, Inc., but for high voltage SiC MOSFETs from other companies as well.
- A. Extraction of Key Parameters
In the proposed analytical model, the key parameters are the parasitic inductances, the junction capacitances and the trans-conductance, the accuracy of which influences the accuracy of the analytical model.
As packaging technology develops, L G1 , L S1 , and L D1 in the package of devices can be minimized to as low as the nH level. In addition, the extraction of the interconnection parasitic inductances of the PCB traces is implemented by an Ansoft Q3D Extractor finite-element analysis (FEA) simulation [34] , [35] . Table I shows the parasitic inductances in the proposed analytical model.
PARASITIC INDUCTANCES IN THE PROPOSED ANALYTICAL MODEL
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PARASITIC INDUCTANCES IN THE PROPOSED ANALYTICAL MODEL
The device manufacturer provides the curves of the input capacitance C iss , the output capacitance C oss , and the reverse capacitance C rss in the datasheet. The relations between the capacitances given in the datasheet and the junction capacitances are C iss = C GS + C GD , C oss = C GD + C DS , and C rss = C GD . Therefore, junction capacitances can be extracted from the datasheet. Obviously, C oss and C rss change with an applied voltage. According to [26] , [32] , and [33] , the nonlinearity of the capacitance versus the voltage can be modelled as:
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where k and λ are the two adjustment parameters extracted from the capacitance curves in the datasheet, v is the applied voltage, and C 0 is the 0 V capacitance value.
Nevertheless, Equ. (27) cannot accurately fit the capacitance curves, especially the inflection point. Thus, the piecewise fitting method is employed for modelling. The values of C oss and C rss for the SiC MOSFET C2M0080120D can be expressed as Equs. (28)- (29).
Fig. 4 shows a comparison between the capacitance curves provided by the datasheet and the piecewise fitting. This figure shows that the capacitance curves under the piecewise fitting method match well with the datasheet. In addition, the junction capacitance C F of the freewheeling diode is also nonlinear, and it can be extracted based on the piecewise fitting method.
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Capacitance curves of SiC MOSFET C2M0080120D.
The device manufacture also provides the transconductance characteristic curve in the datasheet. The transconductance g f represents the incremental change of i CH over an incremental change of v GS . g f is also nonlinear and can be extracted according to the transconductance characteristic curve. The transconductance characteristic curve of a SiC MOSFET C2M0080120D can be expressed based on the piecewise fitting method. Fig. 5 shows a comparison between the transconductance characteristic curve provided by the datasheet and the piecewise fitting.
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Transconductance characteristic curve of SiC MOSFET C2M0080120D.
- B. Verification
In this part, the experimental results of the drain current i D , the drain-source voltage v DS , and the switching loss p are recorded to compare with the analytical model. Fig. 6 shows the double-pulse-test hardware setup. Table II shows the critical test equipment for the experimental verification. Because of the high switching speed of the SiC MOSFET, the probes should have sufficient bandwidth to capture the fast rising and falling edges of the switching waveforms with high fidelity. As stated in [36] and [37] , the equivalent frequency of a rising/falling edge can be approximated as:
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where t r is the rising time of the switching waveform, and t f is the falling time of the switching waveform. In this experiment, the rising/falling edge of the captured waveform may less than 25ns. Therefore, the equivalent frequency is more than 10MHz. For the sake of accuracy, the bandwidth of the test equipment should be higher than ten times the equivalent frequency of the measured waveform [36] , [37] . The test equipment shown in Table II meets this bandwidth requirement. Table III shows the initial parameters of the proposed analytical model.
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Double-pulse-test hardware setup.
CRITICAL TEST EQUIPMENT FOR EXPERIMENTAL VERIFICATION
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CRITICAL TEST EQUIPMENT FOR EXPERIMENTAL VERIFICATION
INITIAL PARAMETERS OF THE PROPOSED ANALYTICAL MODEL
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INITIAL PARAMETERS OF THE PROPOSED ANALYTICAL MODEL
Fig. 7 shows comparisons between the switching waveforms provided by the experiment, the proposed analytical model, the analytical model in [23] , and the analytical model in [30] . Table IV shows a switching time comparison during the switching transition. It is apparent that the proposed analytical model matches better with the experimental results (in terms of the voltage slope, the current slope, the voltage spike, and the current spike) than analytical models in [23] and [30] . It is easy to see that the oscillation frequency and oscillation amplitude in the voltage and current provided by the proposed analytical model are different from those of the experimental results. This is because the junction capacitances and trans-conductance of all the devices are difficult to maintain a high consistency with the data in the datasheet. In addition, the parasitic inductances include the self-inductances and the mutual-inductances, which are influenced by several factors, including the conductor position, current direction, and oscillation frequency [34] , [35] . However, the current directions and oscillation frequency are difficult to predict accurately when conducting a FEA simulation.
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Switching waveforms of SiC MOSFET C2M0080120D provided by the experiment, the proposed analytical model, the analytical model in [23] and the analytical model in [30] (a) turn-on waveforms, and (b) turn-off waveforms. (Remark: According to the datasheet of SiC MOSFET C2M0080120D, in the analytical model in [23] and [30], the transconductance gf is set 9.8, and the junction capacitances are set as follows, CGD=100pF and CDS=300pF when vGS>Vth and vDS<vGS-Vth, CGD=10pF and CDS=90pF when vGS<Vth, or vGS>Vth and vDS> vGS-Vth. And LCS is set 0nH in the analytical model in [30])
SWITCHING TIME COMPARISON DURING SWITCHING TRANSITION
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SWITCHING TIME COMPARISON DURING SWITCHING TRANSITION
The turn-on loss and the turn-off loss are shown in Fig. 8 . The switching loss calculated based on experimental switching waveforms by integrating i D and v DS is called p e . The switching loss calculated based on the proposed analytical model by integrating i D and v DS is called p m1 . The switching loss calculated based on the proposed analytical model by integrating i CH and v DS is called p m2 . As shown in Fig. 8 (a), p m2 is more than the other calculated results. This is due to the fact that the energy stored in C GD and C DS is dissipated by the channel during the turn-on transition, which is ignored by p e and p m1 . As shown in Fig. 8 (b), p m2 is less than the other calculated results. This is due to the fact that some of i D charges C GD and C DS during the turn-off transition, and the energy stored in the junction capacitances is embraced by p e and p m1 .
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Switching loss of SiC MOSFET C2M0080120D provided by the experiment and the proposed analytical model (a) turn-on loss, and (b) turn-off loss.
IV. EFFECTS OF PARASITIC ELEMENTS ON THE SWITCHING PERFORMANCE
The switching processes of a SiC MOSFET are modeled in detail, and the proposed analytical model is verified effectively in the previous section. Therefore, the effects of the parasitic elements on the switching performance can be predicted according to the proposed analytical model. The effects of the gate drive resistance R G , the gate inductance L G , the common source inductance L CS , and the power loop inductance L P are analyzed. These parasitic elements can be changed within reasonable ranges of the actual conditions. Nevertheless, the effects of the junction capacitances are not analyzed because they are in the package of device and cannot be changed. In order to interpret the effects of the parasitic elements directly by sensors, the switching waveforms of the proposed analytical model with varied parasitic elements are plotted. It should be noted that one parameter is studied, while the other parameters are keep invariable and at their initial values.
- A. Gate Drive Resistance RG
The switching waveforms of the proposed analytical model with varied values of R G are shown in Fig. 9 . With a large R G , the switching speed is slowed down. The voltage stress is the voltage drops across the parasitic inductances induced by the falling current, and the current stress is caused by the charging current of C F of the freewheeling diode, which is related to the current slew rate and the parasitic inductances. Therefore, the device stress is reduced with an increasing R G . The switching loss is positively correlated to the switching time and the values of the voltage and current. In addition, it is negatively correlated to the switching speed. The increase in R G leads to an increase in the switching loss. The turn-on loss is due to the increase in the switching time, the decrease in the voltage and current slew rates, and the decrease in the voltage drops across the parasitic inductances. The turn-off loss is due to the increase in the switching time and the decrease in the voltage and current slew rates which outweigh the reduction of the voltage and current stresses.
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Switching waveforms of the proposed analytical model with varied RG (a) turn-on waveforms, and (b) turn-off waveforms.
- B. Gate Inductance LG
The switching waveforms of the proposed analytical model with varied values of L G are shown in Fig. 10 . It can be seen that they almost overlap. This proves that L G has little effect on the switching speed, device stress, and switching loss. In fact, according to the circuit design guidelines, L G should be kept small to minimize the oscillations in the gate drive circuit.
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Switching waveforms of the proposed analytical model with varied LG (a) turn-on waveforms, and (b) turn-off waveform.
- C. Common Source Inductance LCS
The switching waveforms of the proposed analytical model with varied values of L CS are shown in Fig. 11 . L CS is the sum of the common source inductances L S1 and L S2 . This shows that a large L CS can reduce the current slew rate. However, the effect on the voltage slew rate is inconspicuous. L CS is shared by the power loop and the gate drive loop. In addition, the changing current will generate the voltage drop across L CS opposing real intention of the gate drive stage. Therefore, the effect of L CS on the current slew rate is similar to R G . According to Fig. 11 , L CS decreases the device stress by reducing the current slew rate. The switching loss increases with L CS . This is due to the same reason as R G .
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Switching waveforms of the proposed analytical model with varied LCS (a) turn-on waveforms, and (b) turn-off waveforms.
- D. Power Loop Inductance LP
L P lumps all of the parasitic inductances ( L C1 , L C2 , L A1 , L A2 , L S1 , L S2 , L S3 , L D1 , and L D2 ) along the power loop. The switching waveforms of the proposed analytical model with varied values of L P are shown in Fig. 12 . The effect of L P on the switching speed is similar to L CS , which has been given. However, the effect of L P on the device stress is opposite to L CS . L P increases the device stress so that the increase in L P outweighs the reduction in the current slew rate. The turn-on loss decreases with an increasing L P , because the decrease in voltage drops across the parasitic inductances outweighs the other factors. The turn-off loss increases with a large L P due to the decrease in the current slew rate and the increase in the voltage stress.
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Switching waveforms of the proposed analytical model with varied LP (a) turn-on waveforms, and (b) turn-off waveforms.
- E. Summary
Based on the preceding discussion, the effects of the parasitic elements on the switching performance can be summarized as follows.
With respect to the switching speed, an increase in R G can slow down the switching speed. L CS or L P can slow down the current slew rate. However, they have little effect on the voltage slew rate. Regarding to the device stress, R G and L CS can reduce the device stress. However, L P has the opposite reaction. For the switching loss, R G and L CS can add to the switching loss. Nevertheless, L P decreases the turn-on loss and increases the turn-off loss.
Note that L G has little effect on the switching speed, device stress and switching loss. However, L G may cause oscillations in the gate drive circuit.
After a comprehensive assessment of the effects of the parasitic elements, when initially proceeding the PCB circuit design, L CS should be minimized to get a low switching loss, L P should be minimized to get a low device stress and a low turn-off loss, and R G should be chosen at a reasonable value to mitigate the conflict between the switching loss and the device stress.
V. CONCLUSION
This paper presents an improved analytical model to estimate switching loss and analyze the effects of parasitic elements on the switching performance of a SiC MOSFET. The proposed analytical model takes the parasitic inductances, the nonlinearity of the junction capacitances, and the nonlinearity of the trans-conductance into account. The proposed analytical model is more accurate and matches better with experimental results than other analytical models. The proposed analytical model with varied parasitic elements is compared to account for the effects of parasitic elements on the switching performance of a SiC MOSFET.
In this paper, the following points should be noted:
1): The switching loss calculated based on an experiment is imprecise. The experimental results neglect the energy released by C GD and C DS during the turn-on transition and embrace the energy stored in C GD and C DS during the turn-off transition.
2): When initially proceeding with the PCB circuit design, L CS should be minimized to get a low switching loss, L P should be minimized to get a low device stress and a low turn-off loss, and R G can be chosen to achieve a better compromise between the device stress and the switching loss.
BIO
Mei Liang was born in Hebei Province, China, in 1988. She received her B.S. degree in Electronic Engineering from Beijing Jiaotong University, Beijing, China, in 2011. She is presently working towards her Ph.D. degree at Beijing Jiaotong University. Her current research interests include power conversion systems and wide band-gap semiconductor applied research.
Trillion Q. Zheng (Qionglin Zheng) (M’06-SM’07) was born in Jiangshan, Zhejiang Province, China, in 1964. He received his B.S. degree in Electrical Engineering from Southwest Jiaotong University, Sichuan, China, in 1986; and his M.S. and Ph.D. degrees in Electrical Engineering from Beijing Jiaotong University, Beijing, China, in 1992 and 2002, respectively. He is presently a University Distinguished Professor at Beijing Jiaotong University. He is the director of the Center for Electric Traction, founded by Ministry of Education, China. His current research interests include the power supplies and AC drives of railway traction systems, high performance and low loss power electronics systems, PV based converters and control, active power filters, and power quality correction. He holds 17 Chinese patents, and has published over 60 journal articles and more than 100 technical papers in conference proceedings. From 2003 to 2011, he served as the Dean of the School of Electrical Engineering at Beijing Jiaotong University. He is presently the Deputy Director of the Council of the Beijing Society for Power Electronics, and a member of the Council of the China Electrotechnical Society. He received an Excellent Teacher Award of Beijing Government (1997), and a Youth Award of Railway Science and Technology of Zhan Tianyou (2005). He is a laureate of the Youth Elite of Science and Technology of the Railway Ministry of China (1998), and is a Zhongda Scholar for power electronics and motor drive area, by Delta Environmental and Educational Foundation (2007).
Yan Li was born in Heilongjiang Province, China, in 1977. She received her B.S. and M.S. degrees in Electrical Engineering from Yanshan University, Qinhuangdao, China, in 1999 and 2003, respectively; and her Ph.D. degree in Electrical Engineering from the Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2009. From 1999 to 2009, she was at Yanshan University. Since 2009, she has been in the School of Electrical Engineering, Beijing Jiaotong University, Beijing, China. Her current research interests include multiple-input dc/dc converters, renewable power systems, and PV grid-tied systems.
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