This paper proposes a series arc fault detection algorithm which incorporates peak voltage and harmonic current detectors for singlephase boost power factor correction (PFC) rectifiers. The series arc fault model is also proposed to analyze the phenomenon of the arc fault and detection algorithm. For arc detection, the virtual
dq
transformation is utilized to detect the peak input voltage. In addition, multiple combinations of low and highpass filters are applied to extract the specific harmonic components which show the characteristics of the series arc fault conditions. The proposed model and the arc detection method are experimentally verified through a boost PFC rectifier prototype operating under the gridtied condition with an artificial arc generator manufactured under the guidelines for the Underwriters Laboratories (UL) 1699 standard.
I. INTRODUCTION
The installation of arc fault detectors, such as arc fault circuit interrupters (AFCIs), has been required by law or strongly recommended, because arc faults are considered to be the cause of most electrical fires
[1]

[4]
. Among the three different kinds of arc fault types, parallel, ground, and series
[5]
,
[6]
, the detection accuracy of series arc faults is lower than the others. The reason is that the shape of the input current under a series arc fault is similar to that of a normal nonlinear or light load condition. Several arc detection strategies, including the signal analysis and the hardware filtering techniques, have been proposed for commercial electric systems, photovoltaic converters, and AFCIs
[3]
,
[7]
. However, series arc detection under low power conditions is still a big challenge. On the other hand, the growth of the renewable energy industry also demands AFCIs for protection
[8]
,
[9]
.
A power quality meter which can detect series arcfaults has been proposed in
[10]
. In that paper, the rootmeansquare (rms) values of the voltage and current, and the total harmonic distortion (THD) were utilized to detect series arcs. However, this method cannot be directly applied to arc fault analysis in power electronic circuits. For series arc detection, the adaption of the wavelet transform approach is considered to be a recent trend
[11]
,
[12]
. However, they increase the calculation load.
On the other hand, the use of a simple and accurate arc model is very important to quickly analyze the arc detection mechanism. However, it is difficult to establish a welldefined arc model because of its nonlinearity. Several arc models have been proposed in
[13]

[18]
. However, except for the two diode models, they are somewhat complicated and not very intuitive. In addition, the accuracy of the traditional two diode models is not very high.
To develop an arc detection apparatus or algorithm, it is important to follow the recommendations in the Underwriters Laboratories (UL) 1699 standard
[19]
where the functional description, the rule, and the testing method in arc fault detection are described. For series arc faults, the UL1699 states that an arc detector should be able to detect a series arc fault under an input current larger than 5A for 120V line conditions. However, this may not be directly applicable to 220V lines, because a lower current is necessary at the same power rating when compared to 120V lines.
In this paper, a series arc fault detection method is proposed for singlephase power factor correction (PFC) converters. The proposed method consists of the peak voltage and harmonic current detectors. For the peak voltage detector, the virtual
dq
concept is applied, and the peak voltage information is obtained directly. The harmonic current detector utilizes multiple combinations of low and highpass filters to detect harmonic components. Both of the algorithms are implemented in software, and can be plugged into existing PFC controllers. Consequently, no additional expense is expected. Experimental results with the proposed method demonstrate the detection capability of series arc faults with less than a 3A current, which is 1.66 times worse when compared to the UL1699 standards.
II. MODELING OF SERIES ARC FAULTS
Fig. 1
shows the PFC converter configuration with poor connectivity dealt with in this paper. Series arc faults are mainly caused by a poor or loose connection between the grid voltage source
v_{g}
and the input terminal voltage
v_{i}
. The defective connection introduces highly nonlinear impedance which changes according to the phase angle. Usually, the impedance near the zero crossing point (ZCP) of
v_{i}
is higher than that in other locations, and this leads a zero current as shown in the figure. The section where the input current is zero is called as a shoulder
[6]
. The voltage drop across nonlinear impedance during series arc faults is defined as the arc voltage
v_{arc}
. Then, the relationship among
v_{g}
,
v_{i}
, and
v_{arc}
is established as below.
PFC converter configuration under a series arc fault condition.
From (1), it is supposed that
v_{i}
decreases when
v_{arc}
is generated. In fact,
v_{arc}
contains severe harmonic components because of nonlinearity. Since the total harmonic distortion (THD) of
v_{g}
is much lower than
v_{arc}
, it is supposed that
v_{i}
will contain undesirable harmonic components. In
Fig. 2
, typical shapes
v_{g}
,
v_{i}
and
v_{arc}
are shown. Here,
T_{g}
is the period of the grid voltage. The section where the arc voltage is nearly flat is defined as the plateau. It can be considered as a “steadystate” for the arcing condition. As shown in this figure,
v_{i}
is distorted near the ZCP because of the arc voltage
v_{arc}
. If the airgap between the two terminals increases, more distortion is generated. This naturally increases the third harmonic component in the input current. It should be noticed that this ZCP voltage distortion provides important information for arc detection. Ideally, the grid voltage
v_{g}
should not be changed. However, it is slightly affected due to the grid side impedance.
Typical shapes of v_{g}, v_{i}, and v_{arc} under series arc fault conditions.
Fig. 3
shows the proposed low frequency series arc generation model. This model mainly consists of three parts, ideal diodes, passive components, and voltage sources. In this figure,
R_{p}
,
R_{n}
,
L_{p}
, and
L_{n}
constructs the impedance models for the positive and negative cycles during a series arcing condition. The diode and the voltage source
V_{bias}
work as clipper circuits, and mainly determine the starting point of a fault current. In the existing models
[13
,
18]
, only the dc source
V_{bias}
has been considered. However, as can be seen in
Fig. 2
,
v_{arc}
includes ac components, and they cannot be modeled with
V_{bias}
. In order to cover the ac component and to improve the accuracy of the arc model, the use of ac voltage
v_{r}
is proposed in this paper. By considering these components, the voltage equations can be established. For positive cycles with a series arc, the upper branch conducts, and the series arc voltage
v_{arc}
is written as follows:
Proposed low frequency series arc generation model.
where
i_{p}
represents the input current during the arc fault condition. The voltage equation of the lower branch which conducts for negative cycles is represented as:
In (2) and (3),
v_{r}
is defined as follows:
where
f_{g}
and
K_{r}
represent the fundamental frequency of the grid voltage and the model correction factor whose range varies from zero to unity. By adjusting
K_{r}
, the depth of the circular arc during fault conditions, which will be detailed, later can be changed. If the gap in the poor connection is assumed to be very narrow, the inductances
L_{p}
and
L_{n}
can be ignored. Then, (2) and (3) can be simplified as follows:
The values of
R_{p}
,
R_{n}
, and
V_{bias}
are proportional to the physical airgap at the location where the series arc fault occurs so that the two electrical conductors are separated. Usually,
R_{p}
and
R_{n}
have the same value. Equations (5) and (6) represent the generated arc voltage for the plateau where
D_{p}
or
D_{n}
is conducting. In this case, the conditions below should be valid for the positive and negative input voltage cycles:
If (7) or (8) is not satisfied,
D_{p}
or
D_{n}
does not turn on, and the input current
i_{p}
or
i_{n}
does not flow. Then,
v_{i}
is zero, and
v_{arc}
can be obtained as follows from (1).
In summary, the series arc voltage can be modeled with (5), (6), and (9) according to the voltage and current conditions.
III. PFC CONTROLLER WITH THE PROPOSED SERIES ARC FAULT DETECTION METHOD
 A. PFC Control Strategy
Fig. 4
shows a PFC controller including the proposed arc detection algorithm which will be discussed in this section. The controller consists of a voltage controller
G_{v}
(
z
), a current controller
G_{c}
(
z
), a duty feedforward
d_{ff}
, a phaselocked loop (PLL), and the proposed algorithm. Here, the voltage and the current controllers are in the form of traditional proportionalintegral (PI) controllers.
PFC converter control scheme with the proposed series arc detection algorithm.
The voltage controller regulates the dclink voltage
V_{dc}
as a voltage reference higher than the peak input ac voltage
V_{pk}
. For the voltage controller, the control bandwidth should be much less than the fundamental electrical frequency of the system to avoid the wellknown double frequency power ripples in singlephase power systems.
For PFC operation, the input current is controlled by the current controller. To improve the current control performance, the duty feedforward
d_{ff}
which follows is added to the output of the current controller.
By adding
d_{ff}
, the admittance component in the current control loop can be compensated. As a result, the excessive integration in
G_{c}
(
z
) is prevented. The control bandwidth of
G_{c}
(
z
) should be as high as possible. Usually, it is limited by one tenth of the sampling frequency with the single sampling technique.
A block diagram of the PLL is shown in
Fig. 5
[20]
. The PLL employs an all pass filter (APF) whose pole frequency is 60Hz to obtain the same shape of the input voltage with 90 degree of phase delay. With the two sinusoidal signals, the
dq
components are obtained in the synchronous reference frame. This is the socalled virtual
dq
transformation which decomposes the input voltage into the original and orthogonal ones. The relationship between the peak voltage
V_{pk}
and the
dq
reference frame voltages
v_{d}
and
v_{q}
is established as follows:
The structure of the PLL.
Equation (11) gives that
V_{pk}
can be continuously obtained whenever
v_{d}
or
v_{q}
is controlled to be zero. Here, the
q
axis value is taken to be zero. By doing so, the phase angles can be extracted simultaneously. The estimator is implemented with the proportional gain,
K_{pll}
. After passing the integrator, the estimated phase angle
θ
is obtained. This angle is again returned to the
αβ
to
dq
transformation. In fact, this PLL offers important information for the proposed series arc detection algorithm, which will be discussed in the following subsection.
 B. Proposed Series Arc Fault Detection Algorithm
Fig. 6
shows the proposed series arc fault detection algorithm. The algorithm determines whether a series arc has occurred or not using three indicators, the peak voltage magnitude, the derivative of the peak voltage variation, and the harmonic current detector including multiple LPFs and HPFs. From (1), it can be seen that the PFC input voltage
v_{i}
is decreased when a series arc fault has occurred so that the arc voltage
v_{arc}
is established. Accordingly,
V_{pk}
is also reduced with an increasing
v_{arc}
. For this reason,
V_{pk}
is an important indicator which divulges whether a series arc fault has occurred. The detection of
V_{pk}
is easily achieved by monitoring the virtual
d
axis voltage
v_{d}
and its lowpassfiltered component in the PLL as shown in
Fig. 5
. Here,
V_{pk}
is compared with the minimum allowed peak voltage
V_{pkL}
. If
V_{pk}
is less than
V_{pkL}
, indicator
S
_{1}
becomes true. In practice, the power grid can undergo the undervoltage (UV) condition. To minimize misreading during the normal UV condition,
V_{pkL}
is determined by averaging 600 cycles of
V_{pk}
, and taking 85 to 95 percent of the averaged
V_{pk}
in the software, when no arc fault is detected.
Proposed series arc fault detection algorithm.
The other criterion to detect a series arc is the derivative of
V_{pk}
. Again, equation (1) is utilized. The series arc induces the voltage drop, and it can be detected using the derivative filter as follows:
where
ω
_{dr}
is the pole frequency. In fact,
G_{dV}
is equal to a 1
^{st}
order HPF. Since the output of
G_{dV}
is returned to zero at the steadystate, the latching of the output signal is necessary in the plateau region. In this paper, the latching is implemented in the software.
The last stage is evaluating the harmonic components in the input current. This consists of two steps, the preprocessing and using multiple combinations of LPFs and HPFs. The preprocessor, shown in
Fig. 7
, checks the level of the input current error
i_{err}
between the current reference
i
^{*}
_{L}
and the input current
i_{L}
near the ZCPs. Once this error is over a certain value Δ
i_{err}
, the preprocessor regards it as an abnormal situation. By using the preprocessor, the series arc detection accuracy under light load conditions, where the input current already has some harmonics, can be improved.
The flowchart of the preprocessing step.
Once the preprocessor detects an abnormal situation, certain frequency components of
i_{L}
are extracted by using the LPFs and HPFs. In
Fig. 8
, several filtering branches are paralleled. In the figure, the subscript
n
represents the number of paralleled branches. Each branch is composed of one LPF and one HPF, and their cutoff frequencies are different. Either 1
^{st}
or 2
^{nd}
order filters can be employed. The cutoff frequencies of the filters,
LPF
_{n}
and
HPF
_{n}
, are selected as follows:
Configuration of the harmonic frequency passbands.
where
ω
_{n}
, Δ
ω
_{n}
,
ω
_{nL}
, and
ω
_{nH}
represent the passband frequency, half of the passband width, and the cutoff frequencies of the LPF and the HPF in the branch, respectively. The candidates for
ω
_{n}
are the harmonic frequencies of the fundamental electrical frequency. The passband width affects the accuracy of the filtering effect. A wider passband shows better performance than a lower one, but the potential aliasing effect should be avoided. One simple rule to selecting the passband width is sharing the cutoff frequency of a LPF with that of a HPF in the next branch. By doing so, the aliasing problem can be solved, and the iteration cycle of the software can be considerably reduced. Once the outputs of each branch are obtained, they are multiplied by each other as follows:
where
δ_{n}
and
I_{pk}
are the filtered output of the nth branch and the peak magnitude of the input current to normalize
δ_{c}
for different load conditions. This multiplication process is used to maximize the detection capability of the series arcs because the multiple harmonic components are conjugated under the series arc condition. Next, the obtained
δ_{c}
is compared with the harmonic threshold
δ_{thr}
, which is determined by
I_{pk}
and the correction factor
k_{thr}
. In practice, it may be necessary for
δ_{thr}
to be tuned by considering the signaltonoise ratio of the sampled current information. Finally, the proposed algorithm judges the incidence of a series arc when the values of all of the indicators
S
_{1}
,
S
_{2}
and
S
_{3}
become simultaneously true.
IV. PRELIMINARY TEST AND SIMULATION
To examine how the airgap in the series arc path affects the arc voltage, a preliminary test was performed.
Fig. 9
illustrates the configuration for the test. An arc generator which follows the guidelines outlined in UL1699 is placed between the source and the load. The length of the airgap
g_{arc}
between the two terminal points can be adjusted by turning the knob. At the beginning,
g_{arc}
is 0mm, and
v_{g}
is directly applied to
R_{L}
whose resistance is 70Ω so that the 3A input current condition can be met at the steadystate. After that, the knob is turned, and
g_{arc}
is increased. Once
g_{arc}
is set by the reference distance, the rms values of
v_{g}
,
v_{i}
, and
v_{arc}
are measured.
Test configuration for arcing voltage.
Table I
summarizes the test results. In the results,
v_{i}
gets lower as the airgap increases because of the increasing
v_{arc}
. This means that a lower voltage is transferred to the load side when a series arc fault occurs. The grid voltage rarely changes because of the lower impedance. For the 3.5mm condition,
v_{arc}
is almost 10 percent of the input voltage. When
g_{arc}
is 3.6mm, the closed current path is no longer established, and the circuit is open.
Fig. 10
shows the relationship between
g_{arc}
,
v_{i}
, and
v_{arc}
. It is obvious that a longer airgap induces a higher
v_{arc}
and a lower
v_{i}
.
THE RELATIONSHIP BETWEEN THE AIRGAP DISTANCE AND THE ARC VOLTAGE
THE RELATIONSHIP BETWEEN THE AIRGAP DISTANCE AND THE ARC VOLTAGE
The relationship among g_{arc}, v_{i}, and v_{arc}.
For the simulation, a simulation model of the circuit in
Fig. 1
has been built in PSIM software. For the arc voltage, the proposed model is implemented.
Table II
shows the parameters of the boost PFC rectifier. In the preliminary test results, the minimum
v_{arc}
is 16.43V when
g_{arc}
is 2.5mm. This voltage corresponds roughly to 8.21 percent of the input voltage. By considering this,
V_{bias}
in the proposed arc model is selected as 18V which is 8.21 percent of the nominal grid voltage in the rms. The measured and the simulated values for
v_{g}
,
v_{i}
, and
v_{arc}
are compared in
Fig. 11
. As can be seen in this figure, the proposed arc voltage model reflects the practical phenomenon of the arc condition. The converter input voltage
v_{i}
has distortions near the ZCPs as expected. The repetitive spike of the real
v_{arc}
is caused by nonlinear parasitics which are not considered in the simulation model. However, this does not affect the arc detection capability of the proposed algorithm where high frequency transients are not considered.
PARAMETERS FOR THE BOOST RECTIFIER
PARAMETERS FOR THE BOOST RECTIFIER
Measured and simulated voltages. (a) Measured v_{g}, v_{i}, and v_{arc}. (b) Simulated v_{g}, v_{i}, and v_{arc}.
Fig. 12
shows the simulated values of
v_{i}
,
v_{arc}
, and
i_{g}
for 660W and 1320W load conditions. Here, the series arc occurs at
t
= 0.05s. For both the 660W and 1320W cases, the magnitude of
v_{i}
is slightly reduced, and
i_{g}
is distorted when the series arc is applied. It should be noticed that more current distortion is observed in the higher current condition. The frequency component analyses for the input current are illustrated in
Fig. 13
.
Figs. 13
(
a
) and (
b
) compare the harmonic contents in
i_{g}
for the 660W load condition, where
i_{g}
is 3A. Compared to the harmonic contents in
Fig. 13
(
a
), the 13
^{th}
, 15
^{th}
and 17
^{th}
harmonics have been markedly increased in
Fig. 13
(
b
), where the series arc has been simulated. Similarly, the harmonic contents are compared in
Figs. 13
(
c
) and (
d
) for the 1320W load condition. In
Fig. 13
(
c
), lower harmonic components turn up when compared to
Fig. 13
(
a
) case. This is due to the fact that a higher current is usually favorable for obtaining a lower THD in boost PFC rectifiers. When the series arc is simulated for the 1320W load condition, the 17
^{th}
and 19
^{th}
harmonics are noticeably increased as shown in
Fig. 13
(
d
). Additionally, an increased amplitude boost near 2kHz and 3kHz also occurs. This information is given to the fundamental criteria to determine the filtering frequency in the proposed algorithm presented in the previous section. First, the magnitude of the mid frequency ranges from the 13
^{th}
to 19
^{th}
harmonics is increased. Second, a larger increase of the harmonics is indicated in the higher load current condition. This means that arc detection is easier under heavy load conditions. Third, the large current error near the ZCPs cannot be avoided. This is due to the fact that the input voltage is distorted so that its magnitude is zero in the regions. Since fewer current errors are detected in other regions, this can be worked as an important indicator for arc detection. This supports the role of the preprocessor in the proposed method.
Simulated voltages and currents with PFC operation and arcing conditions. (a) 660W. (b) 1320W.
Frequency components in different load and arc conditions. (a) 660W without the arc. (b) 660W with the arc. (c) 1320W without the arc. (d) 1320W with the arc.
With the above analysis, the simulation results of the proposed arc detection algorithm are shown in
Fig. 14
. In
Fig. 14
(
a
), the load condition is assumed as 660W. At
t
=0.05s, the series arc is generated, and
v_{i}
decreases as previously analyzed. Simultaneously, the current distortion near the ZCPs starts. After that, the magnitude of the series arc indicator
δ_{C}
increases so that the series arc can be detected.
Fig. 14
(
b
) shows the simulation results for the 1320W load condition. In this case, the input current distortion is more severe than in the previous condition, and
δ_{C}
is much larger than before. Consequently, it is supposed that the series arc detection performance is better.
Simulation result of the proposed method. (a) 660W. (b) 1320W.
V. EXPERIMENTAL RESULTS
In order to verify the effectiveness of the series arc detection algorithm, a 2kW PFC boost rectifier prototype whose parameters are the same as the ones in
Table II
has been built and tested. For the algorithm implementation, a Texas Instruments’ 32 bit digital signal controller (TMS320F28335) has been employed. The control board equips a 4channel digital to analog converter (DAC) to monitor the internal variables in real time. The power stage uses Semikron’s IGBT modules. The arc generator was built under the guidance of the UL1699 standard. The length of airgap can be easily changed by adjusting the knob so that the depth of the series arc can be managed. The entire experimental setup, including the PFC boost rectifier and the arc generator, is shown in
Fig. 15
.
Experimental configuration.
Fig. 16
shows the experimental results of the proposed algorithm under 660W and 1320 load conditions. In the test, the series arc was created by the arc generator at 0.045s. Consequently, the arc voltage turns up as in the figure. Although the current distortion after the series arc is barely distinguishable,
δ_{c}
clearly indicates the series arc fault signals in both cases. It should be noticed that the average value of
δ_{c}
in the 1320W condition is higher than that in the 660W condition. This means that arc detection in the higher load condition is easier than in the lower load condition. However, the potential for misreading can also be increased. That is why the normalizing process in
Fig. 6
is necessary in the proposed method.
Experimental results of the proposed algorithm. (a) 660W. (b) 1320W.
The arc detection performances under the 660W and 1320W load conditions are shown in
Fig. 17
. In both cases, the series arc can be detected in 0.025s. This almost corresponds to one and a half cycles of the fundamental period. According to the UL1699 standard
[19]
, at least four sequential cycles are necessary before arc detection devices can judge if true arc faults have occurred. Since the proposed method can detect a series arc in one and half cycles, it can be easily modified to meet the UL1699 standard.
Series arc fault detection performance. (a) 660W. (b) 1320W.
VI. CONCLUSION
A series arc fault detection algorithm for singlephase boost rectifiers has been proposed in this paper. The method mainly utilizes the peak voltage variation and harmonic contents in the phase current. The virtual
dq
transformation is adapted to detect the peak voltage, and multiple combinations of LPFs and the HPFs are introduced for the series arc detection. Additionally, a series arc fault model has been proposed to simply model the phenomenon of series arc faults. To verify the proposed algorithm, simulations and the experiments using a boost PFC rectifier were performed. Both the simulation and experimental results agree very well with the analyses. The proposed method was also tested under the UL1699 standard for series arc detection, and this shows the detection capability of series arc faults of less than 3A current which is a 1.66 times worse condition when compared to the standard.
Acknowledgements
This work was supported by the Power Generation & Electricity Delivery of the Korea Institute of Energy Technology Evaluation and Planning (KETEP) grant funded by the Korea government Ministry of Knowledge Economy (No. 20131020400960).
BIO
Younghoon Cho was born in Seoul, Korea, in 1980. He received his B.S. degree in Electrical Engineering from Konkuk University, Seoul, Korea, in 2002; his M.S. degree in Electrical Engineering from Seoul National University, Seoul, Korea, in 2004; and his Ph.D. degree from the Virginia Polytechnic Institute and State University, Blacksburg, VA, USA, in 2012. From 2004 to 2009, he was an Assistant Research Engineer at the Hyundai MOBIS R&D Center, Yongin, Korea. Since 2013, he has been with the Department of Electrical Engineering, Konkuk University. His current research interests include digital control techniques for the power electronic converters in vehicles and grid applications, multilevel converters, and highperformance motor drives.
Jongung Lim was born in Seoul, Korea. He received his B.S. and M.S. degrees in Electrical Engineering from Konkuk University, Seoul, Korea, in 2011 and 2013, respectively. He is presently working towards his Ph.D. degree in Power Electronics at Konkuk University. His current research interests include renewable energy systems, and arc fault detection.
Hyunuk Seo was born in Seoul, Korea. He received his B.S. and M.S. degrees from Konkuk University, Seoul, Korea, in 2011 and 2013, respectively. He is currently working towards his Ph.D. degree in Power Electronics at Konkuk University. He is presently a Researcher for VC Tech, Gunpo, Korea. His current research interests include motor drivers for electric vehicles, and single phase inverter control methods.
SunBae Bang received his M.S. and Ph.D. degrees in Electrical Engineering from Kangwon National University, Chuncheon, Korea, in 2003 and 2009, respectively. He is presently with the Korea Electrical Safety Research Institute, Wanju, Korea. His current research interests include arc fault detection devices, and electrical fire judgment.
GyuHa Choe was born in Pusan, Korea. He received his B.S., M.S. and Ph.D. degrees from Seoul National University, Seoul, Korea, in 1978, 1980, and 1986, respectively. Since 1980, he has been with the Department of Electrical Engineering, Konkuk University, Seoul, Korea, where he is presently working as a Professor and the Director of the Energy Electronics Research Center. From 2007 to 2008, Dr. Choe was the President of the Korean Institute of Power Electronics, Seoul, Korea. From 2012 to 2013, he was the Vice President of Konkuk University. His current research interests include harmonic cancellation and active power filtering, pulse widthmodulation control for ac voltage regulators and inverter welding machines, PCS design for Brown’s gas generation, photovoltaic generation, fuelcell generation, various technologies related to DC distribution, and EV charging with smart grids.
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