DC microgrids are considered as prospective systems because of their easy connection of distributed energy resources (DERs) and electric vehicles (EVs), reduction of conversion loss between dc output sources and loads, lack of reactive power issues, etc. These features make them very suitable for future industrial and commercial buildings’ power systems. In addition, the bipolar-type dc system structure is more popular, because it provides two voltage levels for different power converters and loads. To keep voltage balanced in such a dc system, a bidirectional dual buck-boost voltage balancer with direct coupling is introduced based on P-cell and N-cell concepts. This results in greatly enhanced system reliability thanks to no shoot-through problems and lower switching losses with the help of power MOSFETs. In order to increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. The basic operating principle, the current relations, and a small-signal model of the voltage balancer are analyzed under the burst-mode control scheme in detail. Finally, simulation experiments are performed and a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the bidirectional dual buck-boost voltage balancer under the proposed burst-mode control scheme in low-voltage bipolar-type dc microgrids. DC microgrids [1] - [14] , compared with conventional ac microgrids, have attracted a lot of attention in the pursuit of effective solutions to meet modern energy distribution challenges. They can provide a better connection for dc output type sources such as photovoltaic (PV) systems, fuel cells, and energy storage devices (Li-ion batteries and super-capacitors, etc.). Moreover, system efficiency becomes higher for the lower conversion losses of the inverters between sources and loads, when loads are directly supplied with dc power. Other advantages are as follows: (1) no frequency stability or reactive power issues; (2) no skin effect or ac losses; (3) no downtime related to voltage sags or blackouts. Thus, they are very suitable for future industrial and commercial buildings’ power systems, and for making our daily life efficient and secure. Generally, there are two types of dc microgrids [1] , [4] : unipolar-type and bipolar-type. The first type has only one voltage level in a two-wire dc distribution system. This makes it impossible to supply some types of loads at half voltage. The other type has two voltage levels in a three-wire system. This can provide a grounded neutral line, which is favorable for the security of people in domestic and office places. Additionally, bipolar-type systems have higher reliability due to the possibility of using a power supply under one line failure. This can also decrease power loss for reducing current levels and increasing power transmission capability. As shown in Fig. 1 , a low-voltage bipolar-type dc microgrid [1] , [11] consists of a bidirectional rectifier, a voltage balancer, distributed energy sources (DERs) and dc/ac loads, where dc power is transmitted through a three-wire system. The bidirectional rectifier can construct a unipolar-type system, and then a voltage balancer with the voltage balancing function is introduced to build a three-wire bipolar-type system. The voltage balancer can make the power supply flexible and reliable with two voltage levels for different loads in a bipolar-type dc microgrid. Compared with the unipolar-type dc grid, a voltage balancer is needed and additional loss can be produced in a bipolar-type dc grid. This paper will focus on the research of a voltage balancer. The conventional topologies of bridge-type converters can suffer from a shoot-through risk, which is a major drawback to the reliability of this type of voltage balancer [4] . In addition, MOSFETs with lower switching loss and conducting loss cannot be used directly in conventional bridge converters due to the poorer characteristic of the MOSFET body-diode. Thus, a bidirectional dual buck-boost voltage balancer based on the P-cell and N-cell concepts is adopted in this paper [15] - [18] . Compared with the traditional bridge-type converter, it exhibits the following distinct merits [19] - [24] : (1) there is no shoot-through issue due to the fact that there are no active power switches connected in series in each phase leg; (2) the reverse recovery dissipation of the power switch is greatly reduced because there is no freewheeling current flowing through the body diode of the power switches which improves the reliability; (3) using MOSFETs combined with optimized diodes permits a higher switching frequency to reduce weight and volume. However, the bidirectional dual buck-boost voltage balancer has the disadvantage that two separate inductors are needed resulting in increased volume and weight. However, this can be mitigated by using the directly coupled inductor technique. Generally, a voltage balancer is always working under constant-voltage mode control, resulting in additional power loss, such as converters’ switching loss and conduction loss, especially under voltage balanced conditions. To increase system efficiency and reliability, a novel burst-mode control strategy is proposed for the dual buck-boost voltage balancer. In this paper, a bidirectional dual buck-boost voltage balancer based on the P-cell and N-cell concepts is introduced in Section II, where a direct coupling inductor combined with a common inductor is presented to optimize the two separate inductors. The basic operation principle based on the continuous conduction mode (CCM) is also presented and analyzed in this section. In Section III, a novel burst-mode control strategy is proposed, where the operating principle and the current relations of the inductors, the capacitors and the unbalanced loads are analyzed in detail. In Section IV, an average small-signal model of the voltage balancer under the CCM condition is given to design the control system parameters. In Section V, a 10kW simulation experiment is carried out to validate the feasibility of the proposed burst-mode control strategy for the voltage balancer. In Section VI, a laboratory unit with a 5kW unbalanced ability is constructed to verify the viability of the proposed burst-mode control strategy for the dual buck-boost voltage balancer in low-voltage bipolar-type dc microgrids. Finally, some concluding remarks are drawn in Section VII. The concept of a “low-voltage bipolar-type dc microgrid” with a higher power supply quality is shown in Fig. 1 , where medium voltage is converted into dc voltage in a range from 360V to 400V through a step-down transformer and an active-front-end rectifier. The three-wire dc distribution consisting of a positive line, a neutral line and a negative line is constructed by the voltage balancer, which provides two different voltage levels for customers. The load-side dc-dc/dc-ac converters can be connected between the positive line and the negative line, the positive line and the neutral line, the negative line and the neutral line separately. Since the latter two connections may cause power and voltage imbalances between the positive-neutral and the negative-neutral lines, it is essential to adopt dc voltage balance control. The voltage balancer is placed near the bidirectional rectifier to balance the positive and negative voltage, which can also be placed near the load side. Power electronics circuits can be constructed with two basic switching cells defined as P-cell and N-cell [16] [17] , as shown in Fig. 2 . Each cell consists of one switching device (a MOSFET, IGBT or any other switching device) and one diode constituting three terminals: (+) which is connected to the positive of a voltage-source or capacitor, (-) which is connected to the negative of a voltage-source or capacitor, and a common terminal which is shown as (→) or (←). For the P-cell, this common terminal is connected to the negative terminal of a current source or inductor. For the N-cell, the common terminal is connected to the positive of a current source or inductor. Fig. 3 shows the buck-boost converters based on the basic switch cells. It can be seen that the P-cell buck-boost converter can only transfer power from upside to downside, and the N-cell buck-boost converter from downside to upside. Thus, by combing the former two converters, a bidirectional dual buck-boost converter can be obtained forming a voltage balancer, as shown in Fig. 4 . The voltage balancer consists of the P-cell leg ( S ₁ , D ₁ ), the N-cell leg ( S ₂ , D ₂ ), separate inductors ( L ₁ , L ₂ ), and two split dc bus capacitors ( C_u , C_d ). MOSFETs are used as power switches here, and their body diodes never work. Thus, both the power switches and the power diodes can get an optimized design independently. This permits a higher switching frequency to reduce the weight and volume. As shown in Fig. 4 , V_dc1 , V_dc2 and V_dc stand for the positive-neutral, negative-neutral and positive-negative voltages, respectively. In the following analysis, it is assumed that V_dc is kept constant with the regulation by the bidirectional rectifier. To overcome the drawback of the bidirectional dual buck-boost converter, where two separate inductors are needed resulting in more volume and weight, the directly coupled inductor technique combined with a common inductor is adopted, as shown in Fig. 5 . The equivalent inductance L_pn is four times each phase inductance ( L_d1 , L_d2 ) using the direct coupling technique. The inductor L_pn between S ₁ and S ₂ , and the stray inductance L_S of the interconnections will limit the current i_pn if there is any overlap in the switching of the P-cell and N-cell devices. It is assumed that the overlap time is limited to below some value Δ i _limit . Then, L _pn has the following relation: Depending on the system requirements, the directly coupled inductor can be optimized using Eq. (1). Based on the current ripple analysis, the total inductance value ( L_d1 + L_com ) can be obtained as: where, f_s is the switching frequency and V_dc1 = V_dc2 . From Eq. (1), L_d1 ( L_d2 ) can be derived, and L_com can also be calculated under the condition that Δ I_LD ≤ 20% I _L0 ( I _L0 -nominal operating current). To simplify the analysis of the operation principle, some assumptions are made as follows: (1) all of the power MOSFETs and diodes are ideal devices with no consideration of the switching time or conduction voltage drop; (2) all of the inductors and capacitors are ideal with L_d1 = L_d2 and C_u = C_d = C ; (3) the output dc voltages ( V_dc1 , V_dc2 ) are constant during each switching process. The reference direction of i_L is from the p terminal to the common terminal o. It can be seen that i_L1 is as a positive current while i_L2 as a negative current. Fig. 6 shows the four basic operation modes under the CCM condition. 1) Mode 1: When R₁ is bigger than R₂ , the voltage V_dc1 of the capacitor C_u will increase combined with a decrease of the voltage V_dc2 of the capacitor C_d . At this moment, S ₁ is turned on and the positive inductor current i_L1 increases linearly. In this mode, the P-cell leg starts to transfer additional power to R₂ through L ₁ , as shown in Fig. 2 (a). 2) Mode 2: When S ₁ is turned off, i _L1 continues to run through the freewheeling diode D ₁ , as shown in Fig. 2 (b). The process is not be terminated until S ₁ is turned on again. 3) Mode 3 and Mode 4: Conversely, when R₁ is smaller than R₂ , S ₂ is turned on and the negative current i_L2 increases linearly. At this time, the N-cell leg starts to transfer the redundant power to R₁ through L ₂ , as shown in Fig. 2 (c). Fig. 2 (d) shows that i_L2 continues to run through the freewheeling diode D ₁ when S ₂ is turned off. Burst mode control has been widely used in PWM converters to achieve lower standby losses [25] , [26] . It is an operation mode using the cycle-skipping technique to reduce the switching loss in a switching regulator and to increase the operating efficiency at low power levels. During a burst cycle, each burst of switching can be started at the lowest output voltage value (which occurs just at the start of a burst) and stopped at the maximum voltage value (which occurs at the end of a burst), and this process is repeated. This operation mode can result in high efficiency at low power levels, because the MOSFETs converters can operate at a designed power level close to the optimum efficiency point during a switching period. Based on the idea of burst mode, a novel adaptive burst mode control scheme is proposed for the bidirectional dual buck-boost voltage balancer in low-voltage bipolar-type dc microgrids. Fig. 7 shows a simplified system control block diagram of this scheme. In the proposed adaptive burst mode control, there are three basic operation modes: P-cell mode (PCM), natural-balance-mode (NBM), and N-cell mode (NCM). The basic operational waveforms are shown in Fig. 8 . 1) P-cell mode (PCM): When R₁ is bigger than R₂ , V_dc1 increases and V_dc2 decreases while V_dc is kept constant at the same time. After V_dc2 touches the voltage lower limit V_lower , the P-cell leg switch S ₁ works under the current mode control with the preset i_L-ref . Then, V_dc2 begins to increase to the allowed voltage lower limit V _{lower-allowed} during a burst-mode switching period, in which the voltage difference should satisfy the condition of V_{upper-allowed} - V _{lower-allowed} ˂ V_dc1 - V_dc2 ˂ V_upper - V_lower . After that, S ₁ does not work until V _dc2 reaches V_lower again. Operating in the P-cell mode, the positive inductor current i_L transfers the redundant power from the upside to the downside, as shown in Fig. 8 (a). 2) Natural-balance mode (NBM): As shown in Fig. 8 (b), when V_dc1 and V_dc2 are naturally maintained between the allowed voltage lower limit V_{lower-allowed} and upper limit V_{upper-allowed} without control, the voltage balancer does not work and i_L is zero at this time. 3) N-cell mode (NCM): When R₁ is smaller than R₂ , V_dc1 decreases and V_dc2 increases while V_dc is kept constant at the same time. After V_dc2 touches the voltage upper limit V_upper , the N-cell leg switch S₂ works under the current mode control with the preset i_L-ref . Then, V_dc2 begins to decrease to the allowed voltage upper limit V_{upper-allowed} during a burst mode switching period, in which the voltage difference should satisfy the condition of V_{upper-allowed} - V_{lower-allowed} ˂ V_dc2 - V_dc1 ˂ V_upper - V_lower After that, S₂ does not work until V_dc2 reaches V_upper again. Operating in the N-cell mode, the negative i_L transfers redundant power from the downside to the upside as shown in Fig. 8 (c). Because V_dc1 and V_dc2 should not higher than V_upper or less than V_lower , the switches ( S ₁ , S ₂ ) will work only when the dc voltage values ( V_dc1 , V_dc2 ) do not meet predetermined values. Then, a positive or negative intermittent i_L will exist to transfer the corresponding power between the two poles making the voltages balanced. Thus, the switching loss of the balancer will be effectively reduced and its efficiency will be improved. In addition, the switches of the P-cell leg and N-cell leg are controlled separately. This can avoid the power switches shoot-through problem in traditional bridge topological structures. In this case, high frequency MOSFETs switches can be used to reduce the system volume. The realization of the proposed burst mode control scheme is presented in Fig. 9 . V_ref is equal to half of the total dc voltage value V_dc . If R₁ is bigger than R₂ , V _dc1 increases combined with the decrease of V_dc2 . When V _dc2 is less than V_lower , the following is true V_ref - V_dc2 > V_ref - V_lower and V_ref - V_dc2 > V_ref - V _{lower-allowed} . At this time, the outputs of the two comparators in the P-cell mode are 1 and 0, respectively, and the outputs of the flip-flop and the OR gate are 1. The PWM current control regulates i_L tracking the reference current i_L-ref , with the outputs of the comparator and the OR gate sent to the AND gate together. When the output of the AND gate connected with the comparator is 1, a trigger signal will be sent to switch S ₁ which will be turned on with a positive i_L . Operating in the P-cell mode, the P-cell leg will transfer redundant power from the upside to the downside, and then V _dc2 will increase. When V_dc2 goes up to the value of V _{lower-allowed} , there will be V_ref - V_dc2 < V_ref - V_lower and V_ref - V_dc2 ˂ V_ref - V_{lower-allowed} . At this time, the outputs of the two comparators are 0 and 1, respectively. The output of the flip-flop is zero and the trigger signal of S ₁ disappears. Then, S ₁ is turned off and the voltage balancer stops working. As the operating procedures of S ₂ are the same as those of S ₁ , the analysis process of S ₂ is not given out. If R₁ is bigger than R₂ , V_dc1 goes up and V_dc2 decreases at the same time. Since V_dc is kept constant through regulation by the bidirectional rectifier, the ripple voltage Δ V_dc1 of V_dc1 is also equal to the negative ripple voltage -Δ V_dc2 of V_dc2 . If the two capacitors, C_u and C_d , are equal, i_Cu = i_Cd . Since i_L = i_Cd + i _{R 2} - i_Cu - i _{R 1} , the following can be obtained: If ( i_L + V_dc1 / R ₁ ) × R ₂ > V_ref is satisfied, either the voltage balancer will work normally to balance V_dc1 and V_dc2 , or the balancer will fail to work properly to balance V_dc1 and V_dc2 . On the premise of the balancer working normally, the balancer does not work all the time if ( i_L + V_{upper-allowed} / R ₁ ) × R ₂ > V_{lower-allowed} is satisfied, and an intermittent inductor current i_L will exist. However, the balancer will always at work with a sustained i_L if ( i_L + V_{upper-allowed} / R ₁ ) × R ₂ = V_{lower-allowed} is satisfied. When R ₁ is infinity in extreme cases, R ₂ should not be less than V_ref / i_L-ref , or the balancer will not work. In order to select the control system parameters, an average small-signal model of the voltage balancer under CCM is derived. The duty cycles of S ₁ and S ₂ are defined as , respectively, where D ₁ , D ₂ , are the stable duty ratios and the perturbations of d ₁ and d ₂ . Moreover, the voltage v_dc2 and the inductance current i_L1 are defined as are the stable voltage values, the current values and the perturbations of v_dc2 and i_L1 . From Fig. 6 , it is possible to obtain (5) and (6) when the P-cell bridge leg operates under CCM. (1) S ₁ turning on (2) S ₁ turning off According to the methods of building the average model, it can be derived from (5) and (6): Thus, the transfer function of the inductance current i_L1 versus the duty cycle d ₁ is represented by: From Fig. 8 , (9) and (10) can be obtained when the N-cell bridge leg operates under CCM. (1) S ₂ turning on (2) S ₂ turning off According to the methods of building the average model, (9) and (10) are rewritten by: Thus, the transfer function of the inductance current i_L2 versus the duty cycle d ₂ is represented by: Comparing (8) with (12), the open-loop transfer functions of the P-cell and N-cell bridge legs are the same. Using the following equation G ₂ ( s ) = G ₁ ( s )/[1 + G ₁ ( s )], the closed-loop transfer functions G₂ ( s ) can also be achieved. The control system diagram of the voltage balancer can be illustrated by Fig. 10 . To validate the aforementioned analysis, computer simulations of the output voltages and inductance currents are carried out in PISM software. The total power of the voltage balancer is 10kW and the switching frequency is 30 kHz. The other main simulation parameters are listed as follows: V_dc = 400V, V_ref = 200V, L ₁ = L ₂ = 0.2mH, i_L-ref = 50A, C_u = C_d = 10mF, V_upper = 202.2V, V_lower = 197.8V, V_{upper-allowed} = 201.8V, and V _{lower-allowed} = 198.2V. R_dc1 and R_dc2 will be given according to the simulation requirements in the following. The PI parameters of the control system in Fig. 10 are K_p = 3.7 and K_i = 0.001. With the above simulation parameters, a Bode diagram of the control system is shown in Fig.1 1 , where G ₁ and G ₂ represent the open-loop and closed-loop transfer functions, respectively. When the unbalanced loads are R ₁ = 5Ω and R ₂ = 50MΩ, that is to say, R ₂ is infinite relative to R ₁ , the open-loop transfer function G ₁ ( s ) and the closed-loop transfer function G ₂ ( s ) are described in (13) and (14), respectively. In this case, a Bode diagram of the control system is shown in Fig. 11 (a). When the unbalanced loads are R ₁ = 500Ω and R ₂ = 50MΩ, the open-loop transfer function G ₁ ( s ) and the closed-loop transfer function G ₂ ( s ) are described in (15) and (16), respectively. In this case, a Bode diagram of the control system is shown in Fig. 11 (b). By analyzing the amplitude-frequency characteristic and phase-frequency response curves in the Bode diagram, where G _m = inf and P _m = inf indicate that the gain margin and phase margin are infinite, it can be seen that the given control system is stable. The simulation waveforms of the output voltages ( V_dc1 , V_dc2 ) and inductor current i _L are given in Fig. 12 . As in the above analysis, the simulations are carried out in three different operation modes. P-cell mode: When R₁ is bigger than R ₂ ( R₁ = 50MΩ, R₂ = 5Ω), V_dc1 will be higher than V_dc2 . The P-cell leg switch S ₁ works under the current control mode with a preset i_L-ref of 50A and it generates an intermittent positive current i_L to transfer the redundant power from the upside to the downside. With a decrease of V_dc1 and an increase of V_dc2 , both V_dc1 and V_dc2 come back to allowable values during a burst mode switching period. Then, the voltage balancer stops working and the inductor current i_L disappears. Waveforms of the voltages and inductor current are shown in Fig. 12 (a). To get a clear view of the voltages and current, Fig. 12 (a) is partially enlarged, as shown in Fig. 13 . Natural-balance mode: When R ₁ is equal to R₂ ( R₁ = R₂ = 5Ω), V_dc1 and V_dc2 automatically tend to become balanced without control, and ultimately they are kept equal as in Fig. 12 (b). Because V_dc1 and V_dc2 naturally keep between V_{lower-allowed} and V_{upper-allowed} , the balancer does not work and the inductor current maintains a constant of zero in this case. N-cell mode: When R₁ is smaller than R₂ ( R₁ = 5Ω, R₂ = 50MΩ), V_dc1 is lower than V_dc2 . Thus, the curve of V_dc1 has a downward trend when comparing with Fig. 12 (a) and Fig. 12 (b). Similarly, the N-cell leg switch S ₂ works under the current control mode with a preset i_L-ref of 50A and it generates a negative intermittent current i_L to transfer redundant power from the downside to the upside. With an increase of V_dc1 and a decrease of V_dc2 , both V_dc1 and V_dc2 come back to allowable values, and the voltage balancer stops working and the inductor current disappears. The waveforms of the voltages and current are shown in Fig. 12 (c). To demonstrate the viability of the proposed voltage balancer and the novel burst-mode control scheme, a 5-kW experiment system, shown in Fig. 14 , was designed and tested. The whole system includes a 400V ac input, voltage balancer, dual-outputs full bridge inverter and loads which can be divided into dc loads and ac loads. Additionally, the ac loads include an ac resistive load and a half-bridge-rectifier ac load (such as a residential heater) which will lead to an unbalance between V_dc1 and V_dc2 . Thus, the experiment consists of two parts: the first part is a dc load test which is emulated by two pure resistors; and the second part is an ac load test including the balanced resistive load and unbalanced load of the half-bridge resistive heater. The simulation parameters are listed as follows: C_u = C_d = 10mF, L ₁ = L ₂ = 0.2mH, C₁ = C₂ = 40uF, R_ac1 = R_ac2 = 25Ω, and i_L-ref = 30A. A directly coupled inductor is used in the voltage balancer to reduce its volume and weight, and L_d1 = L_d2 = 50uH, L_com = 150uH. The resistance of the half-bridge-rectifier load is 11Ω. R_dc1 and R_dc2 will be given according to the experimental requirements in the following. The first experiment is conducted with unbalanced dc loads so that R_dc1 = ∞ and R_dc2 = 9Ω, 18Ω. The steady-state experimental waveforms of the inductor current i_L and load current i_dc2 , which is the current through R_dc2 , are shown in Fig. 15 . As shown in Fig. 15 , the switch duty cycle is reduced with the increase of R_dc2 , and the duration of i_L becomes shorter. Even in this extreme condition, the novel burst-mode control scheme and voltage balancer work well to provide an appropriate voltage for R_dc2 . The second experiment is conducted with unbalanced ac loads which are simulated by a half-bridge-rectifier load and a resistive load. For security reasons, a small V_dc is applied to observe the system performance when the voltage balancer is first disconnected. Fig. 16 shows the experimental waveforms of the ac voltage v_out2 and the half-bridge-rectifier load current i_out1 . It can be seen that the half-bridge-rectifier load leads to a serious asymmetric output ac voltage v_out2 without the balancer. Fig. 17 shows the steady-state output ac voltages ( v_out1 , v_out2 ), and the half-bridge heater current i_out1 when the voltage balancer is connected. It can be seen that the dual-output voltages have almost the same RMS values, v_out1 = 118.90V and v_out2 = 117.52V, though the current of the half-bridge heater is obviously unsymmetrical. Fig. 18 and 19 show the experimental transition waveforms of the dual-output ac voltages, and the load currents between the balanced and unbalanced loads. No impact voltages or currents appear in the system with a smooth transition, and the output voltages are balanced and almost the same before and after the loads change. Fig. 20 and 21 show the experimental waveforms of the dual-outputs ac voltages ( v_out1 , v_out2 ), the inductor current i_L and the half-bridge heater current i_out1 . The inductor current is zero when the ac loads are balanced. However, it becomes an intermittent negative current to balance the two voltages when the ac loads are unbalanced. Similarly, there are no impact voltages or currents in the system, and the output voltages are kept balanced before and after the loads change with a smooth transition. According to the above experimental results, the output ac voltages ( v_out1 , v_out2 ) have almost the same values with the control of the voltage balancer, whether balanced loads or unbalanced loads are connected. Thus, the bidirectional dual buck-boost voltage balancer with the burst-mode control scheme is shown to be correct. In this paper, a bidirectional dual buck-boost voltage balancer and a burst-mode control scheme are proposed for low-voltage bipolar-type DC microgrids. The structure of the voltage balancer will enhance the system reliability thanks to the fact that it does not have any shoot-through problems. Under the proposed novel burst-mode control scheme, the balancer works and generates an intermittent inductor current with lower power losses to balance the two output DC voltages when the two voltages do not satisfy predetermined values. At last, simulation and experimental results have verified that the bidirectional dual buck-boost voltage balancer based on the burst-mode control scheme has a good ability to balance the output voltages with balanced or unbalanced DC/AC loads. Moreover, the system has a smooth transition with no impact voltages or currents when the loads change. Chuang Liu received his M.S. degree in Electrical Engineering from Northeast Dianli University, Jilin, China, in 2009, and his Ph.D. degree from the Harbin Institute of Technology, Harbin, China, in 2013. From 2010 to 2012, he was with the Future Energy Electronics Center (FEEC), Virginia Tech, Blacksburg, VA, USA, as a Visiting PhD Student, supported by the Chinese Scholarship Council. Since 2013, he has been an Associate Professor in the School of Electrical Engineering of Northeast Dianli University, Jilin, China. His current research interests include intelligent universal transformers (IUT) for renewable energy systems, bus power flow controllers (BPFC) for hybrid AC/DC distribution, PHEV/PEV smart parking lot/building charging systems, battery energy storage systems and wireless power transfer. Dawei Zhu received his B.S. degree from Northeast Dianli University, Jilin, China, in 2013, where he is presently working towards his M.S. degree in the Department of Electrical Engineering. His current research interests include distributed generation integration and smart power grids. Jia Zhang received her B.S. and M.S. degrees, from Northeast Dianli University, Jilin, China, in 2012 and 2015, respectively. She is presently working for the State Grid, Jilin Electric Power Training Center, Jilin, China. Her current research interests include smart power grids and power electronics. Haiyang Liu received his B.S. degree from the Huazhong University of Science and Technology, Wuhan, China, in 2012. He is presently working towards his M.S. degree in the Department of Electrical Engineering, Northeast Dianli University, Jilin, China. His current research interests include intelligent universal transformers (IUT) for renewable energy systems. Guowei Cai received his B.S. and M.S. degrees from Northeast Dianli University, Jilin, China, in 1990 and 1993, respectively, and his Ph.D. degree from the Harbin Institute of Technology, Harbin, China, in 1999. Since 2004, he has been a Professor in the School of Electrical Engineering of Northeast Dianli University. His current research interests include power system transient stability analysis and electrical power markets.