A new parallel hybrid soft switching converter with low circulating current losses during the freewheeling state and a low output current ripple is presented in this paper. Two circuit modules are connected in parallel using the interleaved pulsewidth modulation scheme to provide more power to the output load and to reduce the output current ripple. Each circuit module includes a threelevel converter and a halfbridge converter sharing the same laggingleg switches. A resonant capacitor is adopted on the primary side of the threelevel converter to reduce the circulating current to zero in the freewheeling state. Thus, the high circulating current loss in conventional threelevel converters is alleviated. A halfbridge converter is adopted to extend the ZVS range. Therefore, the laggingleg switches can be turned on under zero voltage switching from light load to full load conditions. The secondary windings of the two converters are connected in series so that the rectified voltage is positive instead of zero during the freewheeling interval. Hence, the output inductance of the threelevel converter can be reduced. The circuit configuration, operation principles and circuit characteristics are presented in detail. Experiments based on a 1920W prototype are provided to verify the effectiveness of the proposed converter.
I. INTRODUCTION
In medium and high power applications, threephase AC/DC converters are usually used to provide stable DC voltages for industrial power units. Threephase bridge or bridgeless power factor correctors (PFC) are normally adopted in the front stage to compensate the input power quality with a nearly unit power factor and low total harmonic distortion of the line current. Threelevel DC/DC converters
[1]

[8]
are used as the second stage to provide a stable low output voltage with a high load current. Phaseshift pulsewidth modulation (PSPWM) is normally used to generate gating signals and to regulate the output voltage. However, the main disadvantages of the conventional PSPWM fullbridge converter and threelevel converters are a narrow ZVS range at the laggingleg switches and high circulating current losses. Additional passives or active components added on the primary or secondary side have been presented in
[9]

[14]
to reduce the circulating current in the freewheeling state and to extend the ZVS range of the laggingleg switches. The basic idea behind these techniques is to generate a positive voltage at the freewheeling state in order to reduce the primary current to zero. However, additional power losses can occur on these extra components. Thus, the total circuit efficiency cannot be improved. A large leakage inductance or low magnetizing inductance can be used on the primary side to extend the ZVS range of the laggingleg switches. However, the large leakage inductor will also increase the duty cycle loss and decrease the effective duty cycle. Thus, the conduction losses on the primary side will be increased and the circuit efficiency is reduced.
A parallel soft switching DC/DC converter is presented in this paper. The proposed converter includes two hybrid circuit modules to reduce the current stress of the active and passive power components. Each circuit module includes a threelevel PWM converter and a halfbridge converter to achieve the functions of a low circulating current, a wide ZVS range and a low output inductance. The halfbridge converter shares the laggingleg switches of the threelevel converter and operates at a 0.5 duty cycle control. The primary side current of the halfbridge converter can enable the laggingleg switches to be turned on at ZVS from a light load. Thus, the narrow ZVS range in the conventional threelevel converter is overcome in the proposed converter. The secondary windings of two converters are connected in series so that a positive rectified voltage instead of zero voltage is generated on the secondary side in the freewheeling state. This positive rectified voltage is reflected to the primary side to reduce the circulating current to zero. Thus, the circulating current losses on the primary side can be reduced and the circuit efficiency is improved. Since the output inductor voltage during the freewheeling state is also reduced, the size of output filter inductor can also be reduced. Two hybrid circuit modules are operated using the interleaved PWM scheme. The input and output current ripples can be reduced. During the active mode, both the threelevel converter and halfbridge converter transfer energy from the input voltage to the output load. In the freewheeling state, only the halfbridge converter transfers energy to the output load. The circuit configuration, operation principles and circuit characteristics are presented in detail. Finally, experimental results with a 1920W laboratory prototype converting 800V to 48V/40A are provided to validate the theoretical analysis and effectiveness of the proposed converter.
II. PROPOSED CONVERTER
Fig. 1
(a) shows a circuit diagram of the proposed hybrid DC/DC converter. The main proposed converter includes a threelevel converter and a halfbridge converter. The laggingleg switches
S
_{2}
and
S
_{3}
are shared by the threelevel converter (
C
_{in1}
,
C
_{in2}
,
D_{a}
,
D_{b}
,
C
_{f1}
,
C
_{f2}
,
S
_{1}

S
_{4}
,
T
_{1}
,
L
_{r1}
,
C_{r}
,
D
_{1}
,
D
_{4}
and
L_{o}
) and the halfbridge converter (
C
_{f1}
,
C
_{f2}
,
S
_{2}
,
S
_{3}
,
T
_{2}
,
L
_{r2}
,
D
_{2}
,
D
_{3}
and
L_{o}
). The energy stored in the output inductor is reflected to the primary side to achieve the ZVS operation of all of the switches instead of only the leadingleg switches in the conventional threelevel converter. The resonant capacitor
C_{r}
in the threelevel converter is used to reduce the primary current to zero in the freewheeling state. Therefore, the circulating current losses on the primary side can be reduced. The secondary windings of the two converters are connected in series so that the rectified voltage
v_{r}
is positive instead of zero in the freewheeling state. Hence, the inductor voltage
v_{Lo}
in the freewheeling state is reduced and the inductor current ripple is decreased when compared to the conventional threelevel converter.
The proposed hybrid converter (a) circuit diagram (b) main PWM waveforms.
III. OPERATION PRINCIPLES
In the proposed hybrid converter, the phaseshift PWM scheme is adopted to control the necessary duty cycle on the primary side and to regulate the output voltage. The PWM signal of
S
_{2}
(
S
_{3}
) is phaseshifted with respective to the PWM signal of
S
_{1}
(
S
_{4}
).
S
_{1}
(
S
_{2}
) and
S
_{4}
(
S
_{3}
) operate complementarily with a short dead time to avoid short circuits at the high voltage side. The main PWM waveforms of the proposed converter are shown in
Fig. 1
(b). It is assumed that the power semiconductors including
S
_{1}

S
_{4}
,
D_{a}D_{d}
and
D
_{1}

D
_{4}
are ideal, the turns ratios of
T
_{1}
and
T
_{2}
are
n
_{1}
and
n
_{2}
, respectively,
C
_{S1}
=
C
_{S2}
=
C
_{S3}
=
C
_{S4}
=
C_{oss}
, and
V
_{Cin1}
=
V
_{Cin2}
=
V
_{Cf1}
+
V
_{Cf2}
=
V_{in}
/2. Based on the on/off states of
S
_{1}

S
_{4}
,
D_{a}D_{d}
and
D
_{1}

D
_{4}
, there are six operating stages in each half of a switching period. The duty cycle
δ
is defined as the turnon interval of (
S
_{1}
and
S
_{2}
) or (
S
_{3}
and
S
_{4}
).
Fig. 2
gives the topological circuits for the six operating stages during the first half of a switching period.
Operation modes 16 of the proposed converter during the first half switching period (a) mode 1 (b) mode 2 (c) mode 3 (d) mode 4 (e) mode 5 (f) mode 6.
Stage 1 [t_{0}  t_{1}]:
Prior to time
t
_{0}
, switches
S
_{1}
and
S
_{2}
and diodes
D
_{1}
and
D
_{3}
are conducting. The primary currents
i
_{Lr1}
and
i
_{Lr2}
are positive. At time
t
_{0}
, the diode current
i
_{D3}
decreases to zero. The voltages
v_{ab}
=
V_{in}
/2 and
v_{ac}
=
V
_{Cf1}
=
V_{in}
/4. The primary currents can be approximately expressed as
i
_{Lr1}
≈
I_{o}
/
n
_{1}
and
i
_{Lr2}
≈
I_{o}
/
n
_{2}
. The capacitor voltage
v_{Cr}
is given as
v_{Cr}
(
t
) ≈
v_{Cr}
(
t
_{0}
) +
I_{o}
(
t

t
_{0}
) /(
C_{r}n
_{1}
) . The voltage variation Δ
v_{Cr}
in this stage can be expressed as:
Therefore, the rectified voltage at the transformer secondary side is given as:
The output inductor voltage
v_{Lo}
=
v_{r}V_{o}
>0 so that the inductor current
i_{Lo}
increases in this stage.
Stage 2 [t_{1}  t_{2}]:
At time
t
_{1}
, switch
S
_{1}
is turned off. The energy stored in the output inductor
L_{o}
is reflected to the primary side to charge
C
_{S1}
and discharge
C
_{S4}
.
Thus,
S
_{4}
can be easily turned on under ZVS and the ZVS condition of
S
_{4}
is given as:
At
t
_{2}
, capacitor
C
_{S4}
is discharged to zero voltage and the rectified voltage
v_{r}
is decreased to
V_{in}
/(4
n
_{2}
). The time interval Δ
t
_{12}
in stage 2 can be obtained from (4) and expressed as:
The dead time
t_{d}
between switches
S
_{1}
and
S
_{4}
must be greater than the time interval Δ
t
_{12}
in order to turn on
S
_{4}
under ZVS.
Stage 3 [t_{2}  t_{3}]:
At time
t
_{2}
,
v
_{CS4}
=0. Since
i
_{S4}
(
t
_{2}
)<0, the antiparallel diode of
S
_{4}
conducts.
S
_{4}
can be turned on at this moment under ZVS. The voltages
v_{ab}
=0 and
v_{ac}
=
V_{in}
/4 and diodes
D
_{1}
and
D
_{2}
are conducting to commutate the secondary side current of
T
_{1}
. The diode current
i
_{D1}
decreases and
i
_{D2}
increases. In this stage,
L
_{r1}
and
C_{r}
are resonant to reduce the primary current
i
_{Lr1}
to zero.
Stage 4 [t_{3}  t_{4}]:
At time
t
_{3}
, the diode current
i
_{D1}
is decreased to zero and only diode
D
_{2}
conducts the load current. The primary current
i
_{Lr1}
of the threelevel converter is decreases to zero so that no power is transferred through the threelevel converter. The circulating current in this freewheeling state is reduced to zero and there is no circulating loss in this stage. The primary current of the halfbridge converter
i
_{Lr2}
=
i_{Lo}
/
n
_{2}
and the energy is transferred from the input capacitor
C
_{f1}
to the output load by the halfbridge converter in this stage. The rectified voltage
v_{r}
≈
V_{in}
/(4
n
_{2}
). The output inductor voltage
v_{Lo}
≈
V_{in}
/(4
n
_{2}
)
V_{o}
<0. Therefore, the inductor current
i_{Lo}
decreases in this stage.
Stage 5 [t_{4}  t_{5}]:
Switch
S
_{2}
is turned off at
t
_{4}
. Since
i
_{Lr2}
(
t
_{4}
)>0 and
D
_{2}
is conducting, the energy stored in
L_{o}
is reflected to the primary sides to charge
C
_{S2}
and discharge
C
_{S3}
.
The ZVS condition of
S
_{3}
is approximately given as:
At time
t
_{5}
,
C
_{S3}
is discharged to zero voltage. The time interval Δ
t
_{45}
is obtained as:
The dead time
t_{d}
between switches
S
_{2}
and
S
_{3}
must be greater than the time interval Δ
t
_{45}
in order to turn on
S
_{3}
under ZVS.
Stage 6 [t_{5}  t_{6}]:
At time
t
_{5}
,
C
_{S3}
is discharged to zero voltage. Since
i
_{S3}
(
t
_{5}
)<0, the antiparallel diode of
S
_{3}
conducts. Thus,
S
_{3}
can be turned on at this moment under ZVS. The voltages
v_{ab}
=
V_{in}
/2 and
v_{ac}
=
V_{in}
/4.
D
_{2}
and
D
_{4}
are both conducting to commutate the output inductor current
i_{Lo}
. Since
D
_{2}
and
D
_{4}
are conducting, it is possible to derive that the secondary winding voltages of
T
_{1}
and
T
_{2}
are
v
_{T2,s}
=0.5
v
_{T1,s}
. The secondary winding voltage
v
_{T1,p}
(
t
_{5}
) is approximately equal to 
V_{in}
/ 2 
I_{o}δT_{s}
/(2
C_{r}n
_{1}
). Thus, the primary winding voltage of
v
_{T2,p}
at time
t
_{5}
can be given as:
The primary current
i
_{Lr2}
in this stage is decreased and is expressed as:
The primary current
i
_{Lr1}
is decreased from zero to 
n
_{1}
I_{o}
, and the primary current
i
_{Lr2}
is also decreased from
n
_{2}
I_{o}
to 
n
_{2}
I_{o}
. At time
t
_{6}
, the diode current
i
_{D2}
is decreased to zero and only diode
D
_{4}
conducts the load current. Then, the circuit operations in the first half switching period are complete.
IV. PARALLEL HYBRID CONVERTER
In order to provide more power to the output load, increase the ripple frequency and reduce the input and output current ripple, a parallel hybrid converter with the interleaved PWM scheme is proposed and its circuit diagram is shown in
Fig. 3
(a). There are two circuit modules in the proposed parallel hybrid converter. Each circuit module supplies onehalf of the rated power to the output load. The interleaved PWM scheme is adopted to generate the necessary gating signals for the power switches. The PWM signals of
S
_{5}
~
S
_{8}
are phaseshifted by onefourth of a switching period with respective to the PWM signals of
S
_{1}
~
S
_{4}
. In each of the circuit modules, the phaseshift PWM scheme is used to control the necessary duty cycle on the primary side and to regulate the output voltage.
Fig. 3
(b) shows the key PWM waveforms of the proposed parallel hybrid converter during one switching period. The PWM waveforms of the two circuit modules are similar and they are phaseshifted with onefourth of a switching period. The circuit operations of each circuit module were discussed in the previous section. The main advantages of the interleaved PWM operation of the proposed parallel converter include less current ripple at the output side, double the switching frequency, and less the current stress of the passive components at the high current side. The circuit components of the two modules are identical and the duty cycle of each circuit module is the same due to the controller. Thus, current sharing of each circuit module can be achieved. Even if the circuit parameters of each module have some variation, the output inductor currents are almost balanced.
Proposed parallel hybrid converter (a) circuit diagram (b) main PWM waveforms.
V. CONVERTER PERFORMANCE ANALYSIS
Since the duration periods of stages 2, 3 and 5 are very narrow when compared to the periods of the other stages, only stages 1, 4 and 6 are considered to derive the DC voltage gain. In stage 6, the rectified voltage
v
_{r1}
=
v
_{T2,p}
(
t
_{5}
) . The duty loss in stage 6 is related to the load current and the resonant inductance
L
_{r2}
. This duty loss
δ
_{6}
exists in the conventional threelevel converter and the proposed converter. The average rectified voltage
V_{r}
in stage 1 is approximately equal to
V_{in}
/(2
n
_{1}
)+
V_{in}
/(4
n
_{2}
) with the time interval
δ_{eff}T_{s}
, where
δ_{eff}
=
δ

δ
_{6}
. In stage 4, the average rectified voltage
V_{r}
is equal to
V_{in}
/(4
n
_{2}
) with the time interval (0.5
δ_{eff}
)
T_{s}
. The flux balance on the output inductor
L_{o}
can derive the output voltage
V_{o}
.
However, the output voltage of the conventional threelevel converter is expressed as:
where
n
is the turns ratio of the conventional threelevel PWM converter. Based on (13) and (14), a comparison of the normalized voltage conversion ratios of the proposed converter and the conventional threelevel converter is given as:
From (15), the proposed converter has a higher voltage gain compared to the conventional threelevel converter. The turns ratio
n
_{1}
of the proposed converter can be larger than that in the conventional threelevel converter with the same effective duty ratio. The larger turns ratio
n
_{1}
will decrease the conduction losses and also reduce the voltage stress of the rectifier diodes. The power ratings and power percentage of the threelevel converter and halfbridge converter in the proposed circuit are given as:
It can be seen that most of the load power is delivered by the halfbridge converter at a low effective duty cycle. In
Fig. 3
, the voltage stress of the rectifier diodes can be approximately obtained if the voltage spike on the diodes is neglected.
In the conventional threelevel converter, the voltage stress of the rectifier diodes is
v_{stress,D,convention al}
>
V_{o}
/
δ_{eff}
. Therefore, the voltage stress of the rectifier diodes in the proposed converter in (20) and (21) is less than the voltage stress in the conventional threelevel converter with the same duty ratio. During the freewheeling interval in stage 4, the output inductor voltage
v_{Lo}
is equal to
V_{in}
/(4
n
_{2}
)
V_{o}
with the duration period (0.5
δ_{eff}
)
T_{s}
. Thus, the output inductor value can be derived as:
Based on (13) and (22), the necessary output inductance
L_{o}
is expressed as:
In the conventional threelevel converter, the output inductance is given as:
The output inductance ratio between the proposed converter and the conventional threelevel converter is given as:
This means that the proposed converter has less output inductance based on the same current ripple and effective duty cycle.
VI. EXPERIMENTAL RESULTS
The proposed parallel hybrid soft switching DC/DC converter is designed and implemented in this section to confirm the theoretical analysis and to verify the effectiveness of the proposed converter. In the proposed converter, the input voltage
V_{in}
is from 750V to 800V. The output voltage
V_{o}
is 48V and the rated load current
I_{o,max}
is 40A. The switching frequency of the active switches is 100kHz. The two circuit modules are operated with the interleaved phaseshift PWM scheme. Each circuit module provides onehalf of the load current to the output load,
i.e.
I
_{Lo1}
=
I
_{Lo2}
=
I_{o,max}
/2=20A. IRFP460 MOSFETs were used for switches
S
_{1}
~
S
_{8}
. VF30200C and MUR860 fast recovery diodes were used for
D
_{1}
~
D
_{8}
and
D_{a}~D_{d}
, respectively. The input split capacitances
C
_{in1}
and
C
_{in2}
are 360 μF. The flying capacitances
C
_{f1}
~
C
_{f4}
are 1 μF. The resonant capacitances
C
_{r1}
and
C
_{r2}
are 18nF. The output capacitance
C_{o}
is 4000 μF. The turns ratios of
T
_{1}
and
T
_{3}
are 54 turns: 4 turns: 4 turns. The turns ratios of
T
_{2}
and
T
_{4}
are 27 turns: 4 turns: 4 turns. The leakage inductances
L
_{r1}
and
L
_{r3}
are 14 μH, and the leakage inductances
L
_{r2}
and
L
_{r4}
are 22 μH. The output inductances
L
_{o1}
and
L
_{o2}
are 5 μH. The ZVS range for all of the switches in the proposed converter is from 25% load to full load.
Fig. 4
shows a photograph of the proposed converter. The gate voltages of
S
_{1}
~
S
_{8}
for different load conditions and an 800V input voltage are shown in
Fig. 5
. The PWM signals of
S
_{5}
~
S
_{8}
are phaseshifted onefourth of a switching period with respect to the PWM signals of
S
_{1}
~
S
_{4}
.
Fig. 6
shows the measured gate voltage and drain voltage of switches
S
_{1}
~
S
_{8}
at a 25% load. It is clear that all of the switches are turned on under ZVS from a 25% load.
Figs. 7
and
8
show the primary side voltages and currents of the proposed converter at a 50% load and a 100% load, respectively. There are three voltage levels on the voltages
v_{ao}
and
v_{co}
and two voltage levels on the voltages
v_{ab}
and
v_{cd}
. The circulating currents
i
_{Lr1}
and
i
_{Lr3}
of the threelevel converters are all reduced to zero in the freewheeling state (
v_{ab}
=
v_{cd}
=0). Therefore, the conduction losses on the primary side in the freewheeling state are reduced. The primary currents
i
_{Lr3}
and
i
_{Lr4}
of circuit module 2 are phase shifted with respectively to the primary currents
i
_{Lr1}
and
i
_{Lr2}
of circuit module 1, respectively.
Fig. 9
shows the measured results of the secondary side voltage and currents of circuit module 1 at full load. It can be seen that diodes
D
_{2}
and
D
_{3}
are conducting during the freewheeling interval.
Fig. 10
shows the measured waveforms of the output inductor currents at a 100% load. The output inductor current
i
_{Lo2}
is phase shifted to the output inductor current
i
_{Lo1}
. It is clear that the resulting output current ripple Δ(
i
_{Lo1}
+
i
_{Lo2}
) is less than the inductor ripple currents Δ
i
_{Lo1}
and Δ
i
_{Lo2}
due to the interleaved PWM scheme. The measured circuit efficiencies of the proposed converter are 93.5%, 95.7% and 93.3% at a 25% load, a 50% load and a 100% load, respectively. However, the measured circuit efficiencies of the conventional threelevel converter under the same power ratings are 91.9%, 93.4% and 92.1% at a 25% load, a 50% load and a 100% load, respectively. Based on the measured results, it is clear that the proposed converter has better circuit efficiency compared to the conventional threelevel converter.
Photograph of the prototype circuit (a) analog control board (b) main power circuit.
Measured PWM waveforms of S_{1}~S_{8}) at (a) P_{o}=960W (50% load) (b) P_{o}=1920W (100% load).
Measured gate and drain voltages of S_{1}~S_{8} at 25% load (a) S_{1} and S_{5} (b) S_{2} and S_{6} (c) S_{3} and S_{7} (d) S_{4} and S_{8}.
Measured primary side voltage and current waveforms at 50% load (P_{o}=960W).
Measured primary side voltage and current waveforms at full load (P_{o}=1920W).
Measured secondary side voltage and current waveforms of circuit module 1 at full load (P_{o}=1920W).
Measured output inductor currents at full load (P_{o}=1920W).
VII. CONCLUSION
A new parallel hybrid soft switching converter is presented for medium voltage and power applications. Two circuit modules operated with the interleaved PWM scheme are used in the proposed converter to lessen the current stresses of the active and passive components and to reduce the input and output current ripples. In each circuit module, one threelevel converter and one halfbridge converter sharing the laggingleg switch are used to achieve a wide ZVS range for all of the switches, a low circulating current on the primary side, and less output inductor current ripple. Therefore, the circuit efficiency in the proposed converter is higher than the circuit efficiency in the conventional threelevel converter. The circuit configuration, operation principles and circuit characteristics are discussed in detail. Experimental results based on a 1920W prototype confirm the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022 MY3.
BIO
BorRen Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics. His current research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications (ICIEA), the 2007 Taiwan Power Electronics Conference, the 2009 IEEE–Power Electronics and Drive Systems Conference (PEDS), the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEEInternational Conference on Industrial Technology (ICIT).
JiaSheng Chen is currently working toward his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC). His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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