This paper proposes an actively clamped two-switch flyback converter. Compared to the conventional two-switch flyback converter, the proposed two-switch flyback converter operates with a wide duty cycle range. By using an active-clamp circuit, the proposed converter achieves zero-voltage switching for all of the power switches. Zero-current switching of an output diode is also achieved. Thus, compared with the conventional converter, the proposed converter realizes a higher efficiency with an extended duty cycle. The performance of the proposed converter is verified by the experimental results with use of a 1.0 kW prototype circuit. High switching frequency pulse-width modulated DC-DC converters have been widely used for switch-mode power supplies [1] - [8] . Among these converters, the flyback converter is most popularly used because of its simple power circuit structure [9] , [10] . However, the conventional flyback converter is limited by high switch voltage stress [11] , [12] . The two-switch flyback converter shown in Fig. 1 uses an additional switch and two clamping diodes to overcome the drawback of the conventional flyback converter [13] . The two switches S₁ and S₂ are turned on and off simultaneously. The two clamping diodes D_C1 and D_C2 clamp the voltage across S₁ and S₂ by the input voltage V_in . The energy stored in the transformer T is recycled to the input side through the clamping diodes D_C1 and D_C2 [14] . However, the conventional two-switch flyback converter operates under a hard-switching condition [15] , [16] . The energy stored in the leakage inductor L_lk causes voltage spikes when S₁ and S₂ are turned off. The voltage spikes increase the switching losses and consequently decrease the power efficiency. Moreover, the duty cycle of the conventional two-switch flyback converter is limited to 0.5 because the demagnetization of the transformer should be guaranteed [17] . The narrow duty cycle range limits the practical use of the two-switch flyback converter. To address these problems, this paper proposes an actively clamped two-switch flyback converter. Fig. 2 shows the circuit diagram of the proposed converter. The proposed converter has auxiliary switches S₃ and S₄ and one clamping capacitor C_c . By using an active-clamp circuit, the proposed converter extends the duty cycle of the converter. With the help of the clamping capacitor voltage V_c , the transformer can be demagnetized for the duty cycle from 0 to 1. Furthermore, zero-voltage switching (ZVS) of all of the power switches is achieved. Zero-current switching (ZCS) of an output diode is also achieved. Given that the proposed converter operates under soft-switching conditions, this converter can better improve the power efficiency compared with the conventional converter. The operation principle and converter features are described with simulation verifications. The performance of the proposed converter is verified by the experimental results with the use of a 1.0 kW prototype circuit. Compared with the conventional converter, the proposed converter improves the efficiency by 1.5 % at the rated output power. Fig. 2 shows the circuit diagram of the proposed converter. The primary-side circuit consists of power switches ( S₁ , S₂ , S₃ , S₄ ), a clamping capacitor ( C_c ), and a transformer ( T ). Power switches have body diodes ( D₁ , D₂ , D₃ , D₄ ) and output capacitors ( C₁ , C₂ , C₃ , C₄ ). The transformer T has a magnetizing inductor ( L_m ) and leakage inductor ( L_lk ) with the turns ratio of 1: N , where N = N_s / N_p . The secondary-side circuit consists of an output diode ( D_o ) and an output capacitor ( C_o ). V_in is the input voltage. V_c is the clamping capacitor voltage. V_o is the output voltage. Fig. 3 shows the operation modes of the proposed converter during one switching period T_s . The converter has five operation modes during T_s . Fig. 4 shows the switching waveforms of the proposed converter during T_s . Fig. 4 (a) shows the switch voltages V_S1 , V_S2 , V_S3 , and V_S4 and switch currents i_S1 , i_S2 , i_S3 , and i_S4 . Fig. 4 (b) shows the output diode voltage V_Do , diode current i_Do , and primary current i_p . When S₁ and S₄ are turned on, S₂ and S₃ are turned off. When S₂ and S₃ are turned on, S₁ and S₄ are turned off. Power switches operate complementarily with a short dead time T_d . The duty cycle D is based on the on-time of S₁ and S₄ . Then, the duty cycle of S₂ and S₃ is 1 – D . Before t = t₀ , S₂ and S₃ have been turned off. The voltages V_S1 and V_S4 have been zero when the primary current i_p flows through D₁ and D₄ . Mode 1 [t₀, t₁]: At t = t₀ , S₁ and S₄ are turned on at zero voltage. L_m and L_lk stores energy from V_in . The magnetizing inductor current i_Lm increases linearly as follows: Mode 2 [t₁, t₂]: At t = t₁ , S₁ and S₄ are turned off. The primary current i_p charges C₁ and C₄ and discharges C₂ and C₃ . V_S1 increases from zero to V_in . V_S4 increases from zero to V_in + V_c . V_S3 decreases from V_in + V_c to zero. V_S2 decreases from V_in to zero. Given that the switch output capacitor C_s (= C₁ = C₂ = C₃ = C₄ ) is very small, the time interval during this mode is considered negligible compared with T_s . i_Lm is considered to be constant. The leakage inductor L_lk starts discharging its energy by the primary current i_p . D₂ and D₃ conduct the primary current i_p . Mode 3 [t₂, t₃]: At t = t₂ , S₂ and S₃ are turned on at zero voltage. i_Lm decreases linearly as follows: When the output diode D_o is turned on, the energy stored in L_m is transferred to the output. A series-resonance between L_lk and C_c occurs. As the energy stored in L_lk is fully discharged by the series-resonance, the output voltage V_o at the secondary side is reflected to the primary side. The primary current i_p flows as follows: Z_r is the impedance of the series-resonant circuit. ω_r is the angular resonant frequency as follows: Mode 4 [t₃, t₄]: At t = t₃ , the series-resonance is finished when the output diode current i_Do is zero. D_o is turned off at zero current. ZCS of D_o is achieved. The leakage inductor L_lk has no energy in this mode. Mode 5 [t₄, t₅]: At t = t₄ , S₂ and S₃ are turned off. The primary current i_p charges C₂ and C₃ and discharges C₁ and C₄ . V_S1 decreases from V_in to zero. V_S4 decreases from V_in + V_c to zero. V_S3 increases from zero to V_in + V_c . V_S2 increases from zero to V_in . The leakage inductor L_lk starts charging its energy by the primary current i_p . D₁ and D₄ conduct the primary current i_p . The next switching cycle repeats when S₁ and S₄ are turned on at zero voltage. By the volt-second balance law on L_m during T_s , the following relation between V_in and V_c is obtained as follows: From (6), the clamping capacitor voltage V_c is obtained as follows: By the volt-second balance law on the secondary winding of T during T_s , the following relation between V_in and V_o is obtained: Fig. 5 shows the graph between the normalized voltage gain and the duty cycle D . The duty cycle ranges from 0 to 1. As shown in (7), the clamping capacitor voltage V_c is changed by the duty cycle D . This clamping capacitor voltage affects the transformer in the form of demagnetizing voltage when S₂ and S₃ are turned off. The proposed converter has a wider duty cycle compared with that of the conventional two-switch flyback converter. At t = t₀ , to achieve ZVS of S₁ and S₄ , the energy stored in L_m is larger than the energy stored in C_s . The following condition should be satisfied to achieve ZVS of S₁ and S₄ : At t = t₂ , to achieve ZVS of S₂ and S₃ , the energy stored in L_m is larger than the energy stored in C_s . The following condition should be satisfied to achieve ZVS of S₂ and S₃ : At t = t₃ , to achieve ZCS of D_o , the diode current i_Do becomes zero before D_o is turned off. The time interval from t₃ to t₄ should be ensured to achieve ZCS of D_o . This time duration can be changed by the angular resonant frequency ω_r . The critical condition is i_p ( T_s ) = i_Lm ( T_s ). Then, the angular resonant frequency must satisfy the following condition: as where the critical angular resonant frequency ω_rc = 2 πf_rc is decided by where R_o,min is the minimum output resistance. Fig. 6 shows the simulation results of the proposed converter when V_in is 350 V, V_o is 200 V, and D is 0.4. Fig. 6 (a) shows the switch voltages V_S1 and V_S2 and switch currents i_S1 and i_S2 for a 1.0 kW output power. Fig. 6 (b) shows the switch voltages V_S3 and V_S4 and switch currents i_S3 and i_S4 for a 1.0 kW output power. Switch currents are negative before the power switches are turned on. Switch currents flow through the body diodes of the power switches before the power switches are turned on. Thus, ZVS of power switches is achieved. Fig. 7 shows the simulation results of the proposed converter when V_in is 350 V, V_o is 450 V, and D is 0.6. Fig. 7 (a) shows the switch voltages V_S1 and V_S2 and switch currents i_S1 and i_S2 for a 1.0 kW output power. Fig. 7 (b) shows the switch voltages V_S3 and V_S4 and switch currents i_S3 and i_S4 for a 1.0 kW output power. As shown in Fig. 7 , ZVS of power switches is achieved. Moreover, the duty cycle of the converter can be extended to 0.6. The proposed converter operates with a wide duty cycle and reduced switching losses. Fig. 8 shows the simulated waveforms of the diode voltage V_Do , diode current i_Do , and primary current i_p when V_in is 350 V, V_o is 200 V, and D is 0.4 for a 1.0 kW output power. For the series-resonance between L_lk and C_c , L_lk = 7.0 μH and C_c = 1.0 μF are selected. The resonant frequency f_r (= ω_r /2 π ) is decided as f_r = 60.1 kHz. Before the output diode is turned off, the diode current becomes zero. ZCS of an output diode is achieved, which reduces the switching power losses of the converter. A 1.0 kW prototype circuit has been developed to verify the operation principles and performance of the proposed converter. Table I shows the electrical specification of the proposed converter. Table ІІ shows the parameters of the power circuit components. Fig. 9 shows the experimental results of the proposed converter for an open-loop test. When D is 0.4, V_o is 200 V for V_in = 350 V. Fig. 9 (a) shows the switch voltages V_S1 and V_S2 and switch currents i_S1 and i_S2 for a 1.0 kW output power. Fig. 9 (b) shows the switch voltages V_S3 and V_S4 and switch currents i_S3 and i_S4 for a 1.0 kW output power. ZVS of power switches is achieved, which reduces the switching losses at the primary side. Fig. 10 shows the experimental results of the proposed converter for an open-loop test. When D is 0.6, V_o is 450 V for V_in = 350 V. Fig. 10 (a) shows the switch voltages V_S1 and V_S2 and switch currents i_S1 and i_S2 for a 1.0 kW output power. Fig. 10 (b) shows the switch voltages V_S3 and V_S4 and switch currents i_S3 and i_S4 for a 1.0 kW output power. The proposed converter can operate when the duty cycle is over 0.5. Fig. 11 shows the experimental waveforms of the diode voltage V_Do , diode current i_Do , and primary current i_p when V_o is 200 V with D = 0.4 for a 1.0 kW output power. The resonant frequency f_r is around f_r = 60 kHz, which is above the switching frequency f_r = 50 kHz. ZCS of output diode is also achieved, which reduces the switching power losses at the secondary side. Fig. 12 shows the experimental waveforms of the proposed converter for a closed-loop test. This figure also shows the output voltage V_o and output current io when the output power is changed abruptly. The output voltage V_o is regulated when the output power changes from 0.5 kW to 1.0 kW. Fig. 13 shows the measured power efficiency curves of the different power levels. The conventional two-switch flyback converter achieves the efficiency of 93.0 % for a 1.0 kW output power. On the contrary, the proposed converter realizes the efficiency of 94.5 % for a 1.0 kW output power. The proposed converter improves the converter efficiency by 1.5 %. The main factor for the efficiency improvement is the reduced switching losses. Given that the proposed converter is developed for high input voltage applications, the switching losses are more dominant than the conduction losses. The input voltage of the proposed converter is 350 V. For such a high input voltage, the switching losses are more significant than the conduction losses. This significance is because the average current of the switching devices is reduced as the input voltage of the converter is increased. The duty cycle range is also extended from 0 to 1 for the practical use of the proposed converter for a wide input voltage range. This paper has proposed an actively clamped two-switch flyback converter. Operation principle and converter features of the proposed converter are described. The duty cycle range is extended by using an active-clamp circuit. ZVS of all power switches is achieved. ZCS of an output diode is also achieved. The proposed converter reduces switching power losses with an extended duty cycle range. Simulation verifications and experimental results are presented to verify the performance of the proposed converter. The proposed converter realizes the efficiency of 94.5 % for a 1.0 kW output power. This converter improves power efficiency by 1.5 % for a 1.0 kW output power compared with the conventional converter. The proposed converter is suitable for a high-efficiency isolated power supplies for a wide input voltage range. Min-Kwon Yang was born in 1987 in Jeonju, South Korea, in 1987. He received his B.S. in Electronic Engineering from Chonbuk National University, Jeonju, South Korea, in 2012. He is currently working toward his Ph.D. in Electronic Engineering at Chonbuk Nation University. His current research interest is designing of switching power converters including the circuit design and control. Woo-Young Choi was born in 1979 in Gwangju, South Korea. He received his B.S. in Electrical Engineering from Chonnam National University, Gwangju, South Korea, in 2004; and his Ph.D. in Electronic and Electrical Engineering from the Pohang University of Science and Technology, Pohang, South Korea, in 2009. Since 2010, he has been with the Division of Electronic Engineering at Chonbuk National University, Jeonju, South Korea, where is currently working as an Associate Professor. His research interest is power electronics system design for high-efficiency switching power converters.