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Actively Clamped Two-Switch Flyback Converter with High Efficiency
Actively Clamped Two-Switch Flyback Converter with High Efficiency
Journal of Power Electronics. 2015. Sep, 15(5): 1200-1206
Copyright © 2015, The Korean Institute Of Power Electronics
  • Received : January 30, 2015
  • Accepted : April 24, 2015
  • Published : September 20, 2015
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About the Authors
Min-Kwon Yang
Division of Electronic Engineering, Chonbuk National University, Jeonju, Korea
Woo-Young Choi
Division of Electronic Engineering, Chonbuk National University, Jeonju, Korea
wychoi@jbnu.ac.kr

Abstract
This paper proposes an actively clamped two-switch flyback converter. Compared to the conventional two-switch flyback converter, the proposed two-switch flyback converter operates with a wide duty cycle range. By using an active-clamp circuit, the proposed converter achieves zero-voltage switching for all of the power switches. Zero-current switching of an output diode is also achieved. Thus, compared with the conventional converter, the proposed converter realizes a higher efficiency with an extended duty cycle. The performance of the proposed converter is verified by the experimental results with use of a 1.0 kW prototype circuit.
Keywords
I. INTRODUCTION
High switching frequency pulse-width modulated DC-DC converters have been widely used for switch-mode power supplies [1] - [8] . Among these converters, the flyback converter is most popularly used because of its simple power circuit structure [9] , [10] . However, the conventional flyback converter is limited by high switch voltage stress [11] , [12] . The two-switch flyback converter shown in Fig. 1 uses an additional switch and two clamping diodes to overcome the drawback of the conventional flyback converter [13] . The two switches S1 and S2 are turned on and off simultaneously. The two clamping diodes DC1 and DC2 clamp the voltage across S1 and S2 by the input voltage Vin . The energy stored in the transformer T is recycled to the input side through the clamping diodes DC1 and DC2 [14] . However, the conventional two-switch flyback converter operates under a hard-switching condition [15] , [16] . The energy stored in the leakage inductor Llk causes voltage spikes when S1 and S2 are turned off. The voltage spikes increase the switching losses and consequently decrease the power efficiency. Moreover, the duty cycle of the conventional two-switch flyback converter is limited to 0.5 because the demagnetization of the transformer should be guaranteed [17] . The narrow duty cycle range limits the practical use of the two-switch flyback converter.
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Circuit diagram of the conventional two-switch flyback converter.
To address these problems, this paper proposes an actively clamped two-switch flyback converter. Fig. 2 shows the circuit diagram of the proposed converter. The proposed converter has auxiliary switches S3 and S4 and one clamping capacitor Cc . By using an active-clamp circuit, the proposed converter extends the duty cycle of the converter. With the help of the clamping capacitor voltage Vc , the transformer can be demagnetized for the duty cycle from 0 to 1. Furthermore, zero-voltage switching (ZVS) of all of the power switches is achieved. Zero-current switching (ZCS) of an output diode is also achieved. Given that the proposed converter operates under soft-switching conditions, this converter can better improve the power efficiency compared with the conventional converter. The operation principle and converter features are described with simulation verifications. The performance of the proposed converter is verified by the experimental results with the use of a 1.0 kW prototype circuit. Compared with the conventional converter, the proposed converter improves the efficiency by 1.5 % at the rated output power.
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Circuit diagram of the active-clamped two-switch flyback converter.
II. PROPOSED CONVERTER
- A. Operation Principle
Fig. 2 shows the circuit diagram of the proposed converter. The primary-side circuit consists of power switches ( S1 , S2 , S3 , S4 ), a clamping capacitor ( Cc ), and a transformer ( T ). Power switches have body diodes ( D1 , D2 , D3 , D4 ) and output capacitors ( C1 , C2 , C3 , C4 ). The transformer T has a magnetizing inductor ( Lm ) and leakage inductor ( Llk ) with the turns ratio of 1: N , where N = Ns / Np . The secondary-side circuit consists of an output diode ( Do ) and an output capacitor ( Co ). Vin is the input voltage. Vc is the clamping capacitor voltage. Vo is the output voltage.
Fig. 3 shows the operation modes of the proposed converter during one switching period Ts . The converter has five operation modes during Ts . Fig. 4 shows the switching waveforms of the proposed converter during Ts . Fig. 4 (a) shows the switch voltages VS1 , VS2 , VS3 , and VS4 and switch currents iS1 , iS2 , iS3 , and iS4 . Fig. 4 (b) shows the output diode voltage VDo , diode current iDo , and primary current ip . When S1 and S4 are turned on, S2 and S3 are turned off. When S2 and S3 are turned on, S1 and S4 are turned off. Power switches operate complementarily with a short dead time Td . The duty cycle D is based on the on-time of S1 and S4 . Then, the duty cycle of S2 and S3 is 1 – D . Before t = t0 , S2 and S3 have been turned off. The voltages VS1 and VS4 have been zero when the primary current ip flows through D1 and D4 .
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Operation modes of the proposed converter during Ts.
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Switching waveforms of the proposed converter during Ts: (a) switch voltages VS1 ,VS2, VS3, and VS4 and switch currents iS1, iS2, iS3, and iS4 and (b) output diode voltage VDo, diode current iDo, and primary current ip.
Mode 1 [t0, t1]: At t = t0 , S1 and S4 are turned on at zero voltage. Lm and Llk stores energy from Vin . The magnetizing inductor current iLm increases linearly as follows:
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Mode 2 [t1, t2]: At t = t1 , S1 and S4 are turned off. The primary current ip charges C1 and C4 and discharges C2 and C3 . VS1 increases from zero to Vin . VS4 increases from zero to Vin + Vc . VS3 decreases from Vin + Vc to zero. VS2 decreases from Vin to zero. Given that the switch output capacitor Cs (= C1 = C2 = C3 = C4 ) is very small, the time interval during this mode is considered negligible compared with Ts . iLm is considered to be constant. The leakage inductor Llk starts discharging its energy by the primary current ip . D2 and D3 conduct the primary current ip .
Mode 3 [t2, t3]: At t = t2 , S2 and S3 are turned on at zero voltage. iLm decreases linearly as follows:
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When the output diode Do is turned on, the energy stored in Lm is transferred to the output. A series-resonance between Llk and Cc occurs. As the energy stored in Llk is fully discharged by the series-resonance, the output voltage Vo at the secondary side is reflected to the primary side. The primary current ip flows as follows:
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Zr is the impedance of the series-resonant circuit. ωr is the angular resonant frequency as follows:
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Mode 4 [t3, t4]: At t = t3 , the series-resonance is finished when the output diode current iDo is zero. Do is turned off at zero current. ZCS of Do is achieved. The leakage inductor Llk has no energy in this mode.
Mode 5 [t4, t5]: At t = t4 , S2 and S3 are turned off. The primary current ip charges C2 and C3 and discharges C1 and C4 . VS1 decreases from Vin to zero. VS4 decreases from Vin + Vc to zero. VS3 increases from zero to Vin + Vc . VS2 increases from zero to Vin . The leakage inductor Llk starts charging its energy by the primary current ip . D1 and D4 conduct the primary current ip . The next switching cycle repeats when S1 and S4 are turned on at zero voltage.
- B. Converter Features
By the volt-second balance law on Lm during Ts , the following relation between Vin and Vc is obtained as follows:
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From (6), the clamping capacitor voltage Vc is obtained as follows:
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By the volt-second balance law on the secondary winding of T during Ts , the following relation between Vin and Vo is obtained:
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Fig. 5 shows the graph between the normalized voltage gain and the duty cycle D . The duty cycle ranges from 0 to 1. As shown in (7), the clamping capacitor voltage Vc is changed by the duty cycle D . This clamping capacitor voltage affects the transformer in the form of demagnetizing voltage when S2 and S3 are turned off. The proposed converter has a wider duty cycle compared with that of the conventional two-switch flyback converter.
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Graph between the normalized voltage gain and the duty cycle D.
At t = t0 , to achieve ZVS of S1 and S4 , the energy stored in Lm is larger than the energy stored in Cs . The following condition should be satisfied to achieve ZVS of S1 and S4 :
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At t = t2 , to achieve ZVS of S2 and S3 , the energy stored in Lm is larger than the energy stored in Cs . The following condition should be satisfied to achieve ZVS of S2 and S3 :
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At t = t3 , to achieve ZCS of Do , the diode current iDo becomes zero before Do is turned off. The time interval from t3 to t4 should be ensured to achieve ZCS of Do . This time duration can be changed by the angular resonant frequency ωr . The critical condition is ip ( Ts ) = iLm ( Ts ). Then, the angular resonant frequency must satisfy the following condition: as
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where the critical angular resonant frequency ωrc = 2 πfrc is decided by
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where Ro,min is the minimum output resistance.
III. SIMULATION VERIFICATIONS
Fig. 6 shows the simulation results of the proposed converter when Vin is 350 V, Vo is 200 V, and D is 0.4. Fig. 6 (a) shows the switch voltages VS1 and VS2 and switch currents iS1 and iS2 for a 1.0 kW output power. Fig. 6 (b) shows the switch voltages VS3 and VS4 and switch currents iS3 and iS4 for a 1.0 kW output power. Switch currents are negative before the power switches are turned on. Switch currents flow through the body diodes of the power switches before the power switches are turned on. Thus, ZVS of power switches is achieved. Fig. 7 shows the simulation results of the proposed converter when Vin is 350 V, Vo is 450 V, and D is 0.6. Fig. 7 (a) shows the switch voltages VS1 and VS2 and switch currents iS1 and iS2 for a 1.0 kW output power. Fig. 7 (b) shows the switch voltages VS3 and VS4 and switch currents iS3 and iS4 for a 1.0 kW output power. As shown in Fig. 7 , ZVS of power switches is achieved. Moreover, the duty cycle of the converter can be extended to 0.6. The proposed converter operates with a wide duty cycle and reduced switching losses. Fig. 8 shows the simulated waveforms of the diode voltage VDo , diode current iDo , and primary current ip when Vin is 350 V, Vo is 200 V, and D is 0.4 for a 1.0 kW output power. For the series-resonance between Llk and Cc , Llk = 7.0 μH and Cc = 1.0 μF are selected. The resonant frequency fr (= ωr /2 π ) is decided as fr = 60.1 kHz. Before the output diode is turned off, the diode current becomes zero. ZCS of an output diode is achieved, which reduces the switching power losses of the converter.
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Simulation results for D = 0.4: (a) switch voltages VS1 and VS2 and switch currents iS1 and iS2 and (b) switch voltages VS3 and VS4 and switch currents iS3 and iS4.
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Simulation results for D = 0.6: (a) switch voltages VS1 and VS2 and switch currents iS1 and iS2 and (b) switch voltages VS3 and VS4 and switch currents iS3 and iS4.
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Simulated waveforms of the diode voltage VDo, diode current iDo, and primary current ip for D = 0.4.
IV. EXPERIMENTAL RESULTS
A 1.0 kW prototype circuit has been developed to verify the operation principles and performance of the proposed converter. Table I shows the electrical specification of the proposed converter. Table ІІ shows the parameters of the power circuit components.
ELECTRICAL SPECIFICATION OF THE PROPOSED CONVERTER
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ELECTRICAL SPECIFICATION OF THE PROPOSED CONVERTER
PARAMETERS OF THE POWER CIRCUIT COMPONENTS
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PARAMETERS OF THE POWER CIRCUIT COMPONENTS
Fig. 9 shows the experimental results of the proposed converter for an open-loop test. When D is 0.4, Vo is 200 V for Vin = 350 V. Fig. 9 (a) shows the switch voltages VS1 and VS2 and switch currents iS1 and iS2 for a 1.0 kW output power. Fig. 9 (b) shows the switch voltages VS3 and VS4 and switch currents iS3 and iS4 for a 1.0 kW output power. ZVS of power switches is achieved, which reduces the switching losses at the primary side. Fig. 10 shows the experimental results of the proposed converter for an open-loop test. When D is 0.6, Vo is 450 V for Vin = 350 V. Fig. 10 (a) shows the switch voltages VS1 and VS2 and switch currents iS1 and iS2 for a 1.0 kW output power. Fig. 10 (b) shows the switch voltages VS3 and VS4 and switch currents iS3 and iS4 for a 1.0 kW output power. The proposed converter can operate when the duty cycle is over 0.5. Fig. 11 shows the experimental waveforms of the diode voltage VDo , diode current iDo , and primary current ip when Vo is 200 V with D = 0.4 for a 1.0 kW output power. The resonant frequency fr is around fr = 60 kHz, which is above the switching frequency fr = 50 kHz. ZCS of output diode is also achieved, which reduces the switching power losses at the secondary side. Fig. 12 shows the experimental waveforms of the proposed converter for a closed-loop test. This figure also shows the output voltage Vo and output current io when the output power is changed abruptly. The output voltage Vo is regulated when the output power changes from 0.5 kW to 1.0 kW. Fig. 13 shows the measured power efficiency curves of the different power levels. The conventional two-switch flyback converter achieves the efficiency of 93.0 % for a 1.0 kW output power. On the contrary, the proposed converter realizes the efficiency of 94.5 % for a 1.0 kW output power. The proposed converter improves the converter efficiency by 1.5 %. The main factor for the efficiency improvement is the reduced switching losses. Given that the proposed converter is developed for high input voltage applications, the switching losses are more dominant than the conduction losses. The input voltage of the proposed converter is 350 V. For such a high input voltage, the switching losses are more significant than the conduction losses. This significance is because the average current of the switching devices is reduced as the input voltage of the converter is increased. The duty cycle range is also extended from 0 to 1 for the practical use of the proposed converter for a wide input voltage range.
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Experimental results for D = 0.4: (a) switch voltages VS1 and VS2 and switch currents iS1 and iS2 and (b) switch voltages VS3 and VS4 and switch currents iS3 and iS4.
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Experimental results for D = 0.6: (a) switch voltages VS1 and VS2 and switch currents iS1 and iS2 and (b) switch voltages VS3 and VS4 and switch currents iS3 and iS4.
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Experimental waveforms of the diode voltage VDo, diode current iDo, and primary current ip for D = 0.4.
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Experimental waveforms of the output voltage Vo and output current io when the output power is changed abruptly.
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Measured power efficiency curves of the different power levels.
V. CONCLUSION
This paper has proposed an actively clamped two-switch flyback converter. Operation principle and converter features of the proposed converter are described. The duty cycle range is extended by using an active-clamp circuit. ZVS of all power switches is achieved. ZCS of an output diode is also achieved. The proposed converter reduces switching power losses with an extended duty cycle range. Simulation verifications and experimental results are presented to verify the performance of the proposed converter. The proposed converter realizes the efficiency of 94.5 % for a 1.0 kW output power. This converter improves power efficiency by 1.5 % for a 1.0 kW output power compared with the conventional converter. The proposed converter is suitable for a high-efficiency isolated power supplies for a wide input voltage range.
Acknowledgements
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MISP) (2010-0028509).
BIO
Min-Kwon Yang was born in 1987 in Jeonju, South Korea, in 1987. He received his B.S. in Electronic Engineering from Chonbuk National University, Jeonju, South Korea, in 2012. He is currently working toward his Ph.D. in Electronic Engineering at Chonbuk Nation University. His current research interest is designing of switching power converters including the circuit design and control.
Woo-Young Choi was born in 1979 in Gwangju, South Korea. He received his B.S. in Electrical Engineering from Chonnam National University, Gwangju, South Korea, in 2004; and his Ph.D. in Electronic and Electrical Engineering from the Pohang University of Science and Technology, Pohang, South Korea, in 2009. Since 2010, he has been with the Division of Electronic Engineering at Chonbuk National University, Jeonju, South Korea, where is currently working as an Associate Professor. His research interest is power electronics system design for high-efficiency switching power converters.
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