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A ZVS Resonant Converter with Balanced Flying Capacitors
A ZVS Resonant Converter with Balanced Flying Capacitors
Journal of Power Electronics. 2015. Sep, 15(5): 1190-1199
Copyright © 2015, The Korean Institute Of Power Electronics
  • Received : February 28, 2015
  • Accepted : April 22, 2015
  • Published : September 20, 2015
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About the Authors
Bor-Ren Lin
Dept. of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan
linbr@yuntech.edu.tw
Zih-Yong Chen
Dept. of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan

Abstract
This paper presents a new resonant converter to achieve the soft switching of power devices. Two full-bridge converters are connected in series to clamp the voltage stress of power switches at Vin /2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two full-bridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter.
Keywords
I. INTRODUCTION
Three-level converters or inverters have been proposed for high voltage applications such as high speed railway electrical systems [1] , three-phase high power factor correction converters, ship electric power distribution systems [2] , reactive power compensators [3] - [5] and AC motor systems [6] - [8] . Three-level converters/inverters [3] - [8] with a neutral-point diode clamp, a capacitor clamp or series H-bridge topologies have been proposed and developed to decrease the voltage stress of power devices and to increase the switching frequency. As a result, the size of the passive components can be decreased. For modern power converters, a compact size, high power density and high circuit efficiency are normally required. Thus, three-level converters [9] - [14] with zero voltage switching (ZVS) have been proposed to reduce the switching losses on power devices at a desired load range. Based on the resonant behavior due to the leakage inductance and resonant capacitance, the power switches can be turned on under ZVS during the transition interval. However, the ZVS range of power switches depends on the load power and input voltage conditions. Thus, it is very difficult to design a ZVS three-level converter with a wide range of load conditions. Recently, resonant converters [14] - [16] have received a lot of attention due to their essential advantages in terms of a high conversion efficiency and a wide ZVS range of the load condition. If the switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side are operated under zero current switching (ZCS) and the power switches are operated under ZVS turn-on. Thus, the reverse recovery losses of the diode rectifier are improved and the switching losses of the power switches are reduced. However, the voltage stress of the power switches in a conventional resonant converter is equal to the input voltage. In conventional three-level resonant converters [17] , [18] , the input split voltages cannot be balanced automatically in every switching cycle.
This paper presents a new resonant converter with the functions of a low voltage stress of the power switches, low switching losses and balanced input capacitor voltages in every switching cycle. Two full-bridge resonant converters are connected in series at the high voltage side to limit the voltage stress of the power switch at Vin /2. The secondary sides of the two full-bridge converters are connected in parallel to share the load current and to reduce the size of the active and passive components. In order to balance the two input capacitor voltages, two flying capacitors are connected between the AC sides of the two full-bridge converter legs. Thus, the input capacitor voltages can be automatically balanced in each switching cycle. Pulse frequency modulation is adopted to regulate the output voltage. The input impedance of the resonant converter is controlled as an inductive load at the switching frequency. Thus, the power switches can be turned on under ZVS with a wide range of load conditions. If the switching frequency is lower than the series resonant frequency, the rectifier diodes can be turned off under ZCS. The system analysis, circuit characteristics and a design example of the prototype circuit are discussed in detail. Finally, experiments are provided to demonstrate the performance of the proposed converter.
II. PROPOSED CONVERTER
Fig. 1 (a) shows a block diagram of a general two-stage AC/DC converter. The front stage is a three-phase power factor corrector (PFC) to achieve a high power factor and to obtain a stable DC bus voltage Vin . The second stage is a DC/DC converter to provide a stable output voltage against load current variations. Fig. 1 (b) shows a circuit diagram of a conventional three-phase bidirectional PFC. In this circuit, energy can be transferred from an AC source to a DC load or from a DC load to an AC source. The output DC voltage Vin of a three-phase PFC is normally regulated at 750V-800V. Fig. 1 (c) presents a circuit diagram of the proposed new DC/DC converter. Two full-bridge resonant converters are connected in series at the high voltage side to reduce the voltage stress of the power switches and to achieve high circuit efficiency due to ZVS turn-on for each power switch. The secondary sides of these two converters are connected in parallel in order to reduce the current stress of the passive and active components. In order to automatically balance the two input split capacitor voltages vCin1 and vCin2 , two flying capacitors Cf1 and Cf2 are connected at the AC terminal points ( a , c ) and ( b, d ). Thus, the two split capacitor voltages and the two flying voltages are automatically balanced, v Cin1 = v Cin2 = v Cf1 = v Cf2 = Vin /2, in a switching cycle. C in1 and C in2 are input split capacitances. S 1 - S 8 are power MOSFETs. L r1 and L r2 are resonant inductances. C r1 and C r2 are resonant capacitances. C1 - C8 are the output capacitances of S 1 - S 8 , respectively. D 1 - D 4 are the rectifier diodes at the output side. L m1 and L m2 are the magnetizing inductances of the transformers T1 and T2 , respectively. Co is output capacitance. The first resonant converter includes C in1 , S 1 - S 4 , C1 - C4 , C r1 , L r1 , T1 , D 1 , D 2 and Co . The components of the second resonant converter are C in2 , S 5 - S 8 , C5 - C8 , C r2 , L r2 , T2 , D 3 , D 4 and Co . C f1 and C f2 are used to balance v Cin1 and v Cin2 in every switching cycle. The voltage stress of each power switch is clamped at Vin /2. Therefore, MOSFETs with 500V or 600V of voltage stress can be used at the 800V input voltage condition. The pulse frequency modulation scheme is adopted to regulate the output voltage. If the switching frequency is less than the series resonant frequency at the full load and maximum input voltage case, the power switches S 1 - S 8 are turned on at ZVS and the rectifier diodes D 1 - D 4 are turned off at ZCS. Thus, the switching losses of the power switches are reduced and the reverse recovery losses of the rectifier diodes are improved.
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Circuit diagram. (a) Two-stage AC/DC converter. (b) Front stage with a general three-phase PFC. (c) Proposed ZVS DC/DC converter with two full-bridge resonant circuits and two flying capacitors.
v Cin1 and v Cin2 v Cin 1
III. OPERATION PRINCIPLES
In this section, the system analysis and operation principle of the proposed converter are discussed assuming the following assumptions. 1) The transformers T1 and T2 have the same magnetizing inductances L m1 = L m2 = Lm and turns ratios n = np / n s1 = np / n s2 , 2) S 1 - S 8 are ideal and have the same output capacitances C1 =...= C8 = Coss , 3) the diodes D 1 - D 4 areideal, 4) the resonant inductances L r1 = L r2 = Lr , 5) the resonant capacitances C r1 = C r2 = Cr , 6) Co is large enough that Vo is a constant voltage, 7) V Cin1 = V Cin2 = V Cf1 = V Cf2 = Vin /2, and 8) C in1 = C in2 and C f1 = C f2 . Pulse frequency modulation is adopted to change the input impedance of the proposed converter so that the output voltage is regulated at a desired voltage value against different input voltage and load conditions. Based on the on/off states of S 1 - S 8 and D 1 - D 4 , six operating modes can be derived in a switching period. Fig. 2 shows the key PWM waveforms of the proposed converter. The duty cycle of S 1 - S 8 is 0.5. S 1 , S 4 , S 5 and S 8 have the same PWM waveforms. In the same manner, S 2 , S 3 , S 6 and S 7 have the same PWM waveforms. However, the PWM waveforms of S 1 and S 2 are complementary each other. The equivalent circuits of each operation mode are shown in Fig. 3 . Before time t 0 , S 1 - S 8 , D 2 and D 4 are all in the off-state. The capacitors C1 , C4 , C5 and C8 are discharged, and C2 , C3 , C6 and C7 are charged.
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Key waveforms of the proposed converter.
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Operation modes of the proposed converter in one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.
Mode 1 [t0 - t1]: At t 0 , C1 , C4 , C5 and C8 are discharged to zero voltage. Since i Lr1 and i Lr2 are both negative, the anti-parallel diodes of S 1 , S 4 , S 5 and S 8 are conducting. Therefore, S 1 , S 4 , S 5 and S 8 can be turned on at this moment to achieve ZVS. The flying capacitor voltages v Cf1 = V Cin1 and v Cf2 = v Cin2 . The voltage stresses of S 2 and S 3 are equal to V Cin1 , and the voltage stresses of S 6 and S 7 are equal to V Cin2 . In resonant circuit 1, i Lr1 > i Lm1 and the diode D 1 conducts. Thus, v Lm1 = nVo and i Lm1 is increasing in this mode. C r1 and L r1 are resonant with the initial voltage Vin /2- nVo - v Cr1 ( t 0 ). Similarly, C r2 and L r2 are resonant with the initial voltage Vin /2- nVo - v Cr2 ( t 0 ) in the second resonant circuit, and i Lm2 is also increasing. The input power is transferred to the output load through ( S 1 , L r1 , T1 , S 4 , D 1 ) in resonant circuit 1 and ( S 5 , L r2 , T2 , S 8 , D 3 ) resonant circuit 2. Thus, the resonant inductor currents and the capacitor voltages in this mode are expressed as:
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where
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Mode 2 [t1 - t2]: At t 1 , i Lr1 = i Lm1 and i Lr2 = i Lm2 . Then, the diodes D 1 - D 4 are off in this mode. Since S 1 and S 4 are still conducting, C r1 , L r1 and L m1 are resonant in resonant circuit 1. In the same manner, S 5 and S 8 are still conducting so that C r2 , L r2 and L m2 are resonant in resonant circuit 2. Thus, i Lr1 , i Lr2 , v Cr1 and v Cr2 are expressed as:
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where
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Mode 3 [t2 - t3]: At t 2 , S 1 , S 4 , S 5 and S 8 are turned off and the diodes D 2 and D 4 are conducting. Thus, v Lm1 = v Lm2 =- nVo . The magnetizing currents i Lm1 and i Lm2 decrease with a slope of - nVo / Lm . Since i Lr1 ( t 2 )>0 and i Lr2 ( t 2 )>0, C1 , C4 , C5 and C8 are charged and C2 , C3 , C6 and C7 are discharged.
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If the energy stored in L r1 and L r2 at t 2 is greater than the energy stored in C1 - C8 , then C2 , C3 , C6 and C7 can be discharged to zero voltage at time t 3 .
Mode 4 [t3 - t4]: At t 3 , C2 , C3 , C6 and C7 are discharged to zero voltage and the anti-parallel diodes of S 2 , S 3 , S 6 and S 7 are conducting. Before i Lr1 and i Lr2 become negative, S 2 , S 3 , S 6 and S 7 can be turned on at this moment under ZVS. Since D 2 and D 4 are conducting, v Lm1 = v Lm2 =- nVo . Thus, i Lm1 and i Lm2 decrease in this mode. The voltage stresses of S 1 and S 4 are equal to V Cin1 , and the voltage stresses of S 5 and S 8 are equal to V Cin2 . The flying capacitor voltages v Cf1 = V Cin2 and v Cf2 = v Cin1 . In circuit module 1, C r1 and L r1 are resonant with the initial voltage nVo - Vin /2- v Cr1 ( t 3 ). Similarly, C r2 and L r2 are resonant with the initial voltage nVo - Vin /2- v Cr2 ( t 3 ) in the second resonant circuit.
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The input power is transferred to the output load through S 3 , L r1 , T1 , S 2 and D 2 in resonant circuit 1 and through S 7 , L r2 , T2 , S 6 and D 4 in resonant circuit 2.
Mode 5 [t4 - t5]: At t 4 , i Lr1 = i Lm1 and i Lr2 = i Lm2 . Thus, the diodes D 1 - D 4 are off. Since S 2 , S 3 , S 6 and S 7 are still in the on-state, C r1 , L r1 and L m1 are resonant in circuit 1, and C r2 , L r2 and L m2 are resonant in circuit 2.
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The flying capacitor voltages v Cf1 = V Cin2 and v Cf2 = v Cin1 in this mode.
Mode 6 [t5 - Ts+t0]: At t 5 , S 2 , S 3 , S 6 and S 7 are turned off and the diodes D 1 and D 3 are conducting. The magnetizing voltages v Lm1 = v Lm2 = nVo . Thus, i Lm1 and i Lm2 increase in this mode. Since i Lr1 and i Lr2 are negative, C1 , C4 , C5 and C8 are discharged and C2 , C3 , C6 and C7 are charged.
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If the energy stored in L r1 and L r2 at t 5 is greater than the energy stored in C1 - C8 , then C1 , C4 , C5 and C8 can be discharged to zero voltage at time Ts + t 0 . Then, the operating modes of the proposed converter in a switching cycle are complete.
IV. CONVERTER PERFORMANCE ANALYSIS
The output voltage of the proposed converter is based on pulse frequency modulation. Thus, the fundamental harmonic approach with a variable switching frequency is used to approximately analyze the steady state of the proposed converter. The power transfer from the input terminal to the output load through two full-bridge resonant tanks is depended on the switching frequency. All of the harmonics of the switching frequency are neglected in the following discussion. Fig. 4 shows an equivalent circuit of the proposed converter for the derivation of the steady state model. The equivalent circuit components in the two resonant tanks are identical. Each resonant tank is supplied one-half of the input power to the output load. Since the duty ratio of each power switch is equal to 0.5, the input AC voltages vab and vcd of the resonant tanks are square waveforms with two voltage levels Vin /2 and - Vin /2. The AC voltages vab and vcd can be expressed as the fundamental frequency term and the harmonics term.
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Equivalent circuit of the proposed converter for the derivation of steady state model.
From (25), the fundamental root-mean-square ( rms ) value of vab and vcd is equal to
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. Due to the on-off states of D 1 - D 4 , the fundamental rms value of the magnetizing voltages is expressed as v Lm1,rms = v Lm2,rms =
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. Since the average output current of each center-tapped rectifier is equal to Io /2, the rms value of the secondary winding currents is equal to i T1,s,rms = i T2,s,rms =
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. Therefore, the load resistance Ro reflected to the transformer primary side can be expressed as:
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The resonant tank is excited by an effectively fundamental sinusoidal input voltage vf and it drives the effective AC resistive load Rac . The pulse frequency modulation (PFM) scheme is adopted to regulate the AC voltage gain of the proposed converter. The AC voltage gain of the resonant tank can be expressed as:
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where
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, k = Lr / Lm , C r1 = C r2 = Cr , L r1 = L r2 = Lr and fs is the switching frequency. The DC voltage gain Gdc of the proposed converter is given as:
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where Vf is the voltage drop on the rectifier diodes D 1 - D 4 . If the input and output DC voltages are given, the operating switching frequency can be obtained by Gdc = Gac .
A laboratory prototype is implemented with the following specifications: Vin =750V-800V, Vo =48V, Po =1500W and the series resonant frequency fr =120kHz. The primary and secondary winding turns of the transformers T1 and T2 are 34 turns and 4 turns, respectively. Thus, the minimum and maximum DC voltage gains of the resonant converter are expressed as:
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The AC equivalent resistance Rac at the full load condition is given as:
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In the prototype circuit, the selected inductance ratio of Lr and Lm is k = Lr / Lm =0.2. Based on (27), (29) and (30), the AC voltage gain curves of the proposed converter with different quality factors Q and frequency ratios F at k =0.2 are illustrated in Fig. 5 . From Fig. 5 , it is observed that the output voltage can be regulated if the quality factor Q ≤ 0.5 at a full load. Therefore, Q =0.5 at a full load is selected in the prototype circuit. The AC voltage gain of the proposed converter at the no load condition ( Q =0) is given as:
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Gain curves of proposed resonant converter with Vin,min=750V and Vin,max=800V.
Therefore, the output voltage Vo can be regulated at the no load condition. Based on the derived Rac , k , Q and fr , the resonant inductances, the magnetizing inductances and the resonant capacitances can be obtained.
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The voltage stress of S 1 - S 8 is equal to Vin,max /2=400V. MOSFETs (IRFP460) with 500V/20A ratings are selected for S 1 - S 8 . The voltage stress and average current of D 1 - D 6 are equal to 2( Vo + Vf ) = 98.2V and Io,max / 4 ≈ 7.8A , respectively. Diodes (KCU30A30) with 300V/30A ratings and a 1.1V voltage drop are adopted for D 1 - D 4 . The adopted capacitances C in1 = C in2 =470μF/450V, C f1 = C f2 =100nF/630V and Co =2200μF/100V.
V. EXPERIMENTAL RESULTS
Experiments with a prototype circuit, with the circuit components derived in the previous section, are provided to demonstrate the performance of the proposed converter. Fig. 6 shows the measured gate voltages of S 1 - S 8 at a full load with the input voltage Vin =750V and 800V conditions. Fig. 7 illustrates the measured gate voltage, drain voltage and switch current of S 1 at light (25%) and full (100%) loads with different input voltages. Before S 1 is turned on, i S1 is negative to discharge the drain-to-source capacitor of S 1 . Therefore, S 1 can be turned on under ZVS when the drain voltage v S1,ds is decreased to zero voltage. Since S 4 , S 5 and S 8 have the same PWM waveforms as S 1 , it is clear that S 4 , S 5 and S 8 are also turned on under ZVS from a 25% load to a full load. Fig. 8 shows the measured gate voltage, drain voltage and switch current of S 2 at light (25%) and full (100%) loads with different input voltages. S 2 is also turned on under ZVS from a 25% load to a full load. Since the PWM signals of S 3 , S 6 and S 7 are identical to the PWM signal of S 2 , it can be determined that S 3 , S 6 and S 7 are also turned on under ZVS. Fig. 9 gives the measured results of the gate voltages, AC terminal voltages, resonant inductor currents and resonant capacitor voltages at a full load. The two inductor currents and the two capacitor voltages are balanced under the test results. Fig. 10 gives the measured switch currents i S1 and i S2 , inductor current i Lr1 and flying capacitor current i Cf1 at a full load. In the same manner, the measured switch currents i S1 and i S2 , inductor current i Lr1 and flying capacitor current i Cf1 at a full load are shown in Fig. 11 . When the switches S 1 and S 5 are in the on-state and S 2 and S 6 are in the off-state, the flying capacitor voltage V Cf1 is equal to the input capacitor voltage V Cin1 with half of a switching period. Similarly, the flying capacitor voltage V Cf1 = V Cin2 when the switches S 1 and S 5 are in the off-state and S 2 and S 6 are in the on-state with half of a switching period. Therefore, both of the input capacitor voltages V Cin1 and V Cin2 are automatically balanced at Vin /2. Fig. 12 gives test results for the two input capacitor voltages v Cin1 and v Cin2 and the two flying capacitor voltages at the full load and 800V input voltage case. It is clear that the two input capacitor voltages v Cin1 and v Cin2 are balanced at 400V and v Cf1 = v Cf2 = v Cin1 = v Cin2 = Vin /2. Fig. 13 shows the measured diode currents and two circuit output currents at the full load condition. The output currents i o1 and i o2 are balanced. Fig. 14 shows the measured circuit efficiencies of the proposed converter under different load and input voltage conditions.
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Measured gate voltages of S1-S8 at full load and (a) Vin=750V (b) Vin=800V.
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Measured gate voltage, drain voltage and switch current of S1 at (a) 25% load and Vin=750V (b) 25% load and Vin=800V(c) 100% load and Vin=750V(d) 100% load and Vin=800V.
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Measured gate voltage, drain voltage and switch current of S2 at (a) 25% load and Vin=750V (b) 25% load and Vin=800V(c) 100% load and Vin=750V(d) 100% load and Vin=800V.
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Measured results of the gate voltages vS1,gs and vS2,gs, AC terminal voltages vab and vcd, resonant inductor currents iLr1 and iLr2, and resonant capacitor voltages vCr1 and vCr2 at full load.
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Measured switch currents iS1 and iS2, inductor current iLr1 and flying capacitor current iCf1 at full load.
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Measured switch currents iS3 and iS4, inductor current iLr1 and flying capacitor current iCf2 at full load.
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Measured results of input capacitor voltages and flying capacitor voltages at full load and 800V input voltage case.
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Measured diode currents and two circuit output currents at full load condition.
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Measured efficiencies of the proposed converter with different input terminal voltages and load conditions.
VI. CONCLUSION
This paper presents a new full-bridge resonant converter with the characteristics of low voltages stress MOSFETs, ZVS turn-on for the MOSFETs, no reverse recovery current on the rectifier diodes, balanced two input capacitor voltages and high circuit efficiency. Two half-bridge converter legs with two spilt capacitors are adopted to reduce the voltage stress of the MOSFETs at Vin /2. Therefore, the proposed converter is suitable for use in high input voltage applications. The two flying capacitors C f1 and C f2 are used to automatically balance the two input capacitor voltages in every switching cycle. The two resonant circuits are used to increase the load power and to achieve ZVS for all of the power semiconductors. The system analysis, a design example and experiments are presented to demonstrate the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224 -022 -MY3.
BIO
Bor-Ren Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics. His current research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, the 2009 IEEE–Power Electronics and Drive Systems Conference, the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEE-International Conference on Industrial Technology.
Zih-Yong Chen received his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC), in 2014. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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