This paper presents a new resonant converter to achieve the soft switching of power devices. Two full-bridge converters are connected in series to clamp the voltage stress of power switches at V_in /2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two full-bridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter. Three-level converters or inverters have been proposed for high voltage applications such as high speed railway electrical systems [1] , three-phase high power factor correction converters, ship electric power distribution systems [2] , reactive power compensators [3] - [5] and AC motor systems [6] - [8] . Three-level converters/inverters [3] - [8] with a neutral-point diode clamp, a capacitor clamp or series H-bridge topologies have been proposed and developed to decrease the voltage stress of power devices and to increase the switching frequency. As a result, the size of the passive components can be decreased. For modern power converters, a compact size, high power density and high circuit efficiency are normally required. Thus, three-level converters [9] - [14] with zero voltage switching (ZVS) have been proposed to reduce the switching losses on power devices at a desired load range. Based on the resonant behavior due to the leakage inductance and resonant capacitance, the power switches can be turned on under ZVS during the transition interval. However, the ZVS range of power switches depends on the load power and input voltage conditions. Thus, it is very difficult to design a ZVS three-level converter with a wide range of load conditions. Recently, resonant converters [14] - [16] have received a lot of attention due to their essential advantages in terms of a high conversion efficiency and a wide ZVS range of the load condition. If the switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side are operated under zero current switching (ZCS) and the power switches are operated under ZVS turn-on. Thus, the reverse recovery losses of the diode rectifier are improved and the switching losses of the power switches are reduced. However, the voltage stress of the power switches in a conventional resonant converter is equal to the input voltage. In conventional three-level resonant converters [17] , [18] , the input split voltages cannot be balanced automatically in every switching cycle. This paper presents a new resonant converter with the functions of a low voltage stress of the power switches, low switching losses and balanced input capacitor voltages in every switching cycle. Two full-bridge resonant converters are connected in series at the high voltage side to limit the voltage stress of the power switch at V_in /2. The secondary sides of the two full-bridge converters are connected in parallel to share the load current and to reduce the size of the active and passive components. In order to balance the two input capacitor voltages, two flying capacitors are connected between the AC sides of the two full-bridge converter legs. Thus, the input capacitor voltages can be automatically balanced in each switching cycle. Pulse frequency modulation is adopted to regulate the output voltage. The input impedance of the resonant converter is controlled as an inductive load at the switching frequency. Thus, the power switches can be turned on under ZVS with a wide range of load conditions. If the switching frequency is lower than the series resonant frequency, the rectifier diodes can be turned off under ZCS. The system analysis, circuit characteristics and a design example of the prototype circuit are discussed in detail. Finally, experiments are provided to demonstrate the performance of the proposed converter. Fig. 1 (a) shows a block diagram of a general two-stage AC/DC converter. The front stage is a three-phase power factor corrector (PFC) to achieve a high power factor and to obtain a stable DC bus voltage V_in . The second stage is a DC/DC converter to provide a stable output voltage against load current variations. Fig. 1 (b) shows a circuit diagram of a conventional three-phase bidirectional PFC. In this circuit, energy can be transferred from an AC source to a DC load or from a DC load to an AC source. The output DC voltage V_in of a three-phase PFC is normally regulated at 750V-800V. Fig. 1 (c) presents a circuit diagram of the proposed new DC/DC converter. Two full-bridge resonant converters are connected in series at the high voltage side to reduce the voltage stress of the power switches and to achieve high circuit efficiency due to ZVS turn-on for each power switch. The secondary sides of these two converters are connected in parallel in order to reduce the current stress of the passive and active components. In order to automatically balance the two input split capacitor voltages v_Cin1 and v_Cin2 , two flying capacitors C_f1 and C_f2 are connected at the AC terminal points ( a , c ) and ( b, d ). Thus, the two split capacitor voltages and the two flying voltages are automatically balanced, v _Cin1 = v _Cin2 = v _Cf1 = v _Cf2 = V_in /2, in a switching cycle. C _in1 and C _in2 are input split capacitances. S ₁ - S ₈ are power MOSFETs. L _r1 and L _r2 are resonant inductances. C _r1 and C _r2 are resonant capacitances. C₁ - C₈ are the output capacitances of S ₁ - S ₈ , respectively. D ₁ - D ₄ are the rectifier diodes at the output side. L _m1 and L _m2 are the magnetizing inductances of the transformers T₁ and T₂ , respectively. C_o is output capacitance. The first resonant converter includes C _in1 , S ₁ - S ₄ , C₁ - C₄ , C _r1 , L _r1 , T₁ , D ₁ , D ₂ and C_o . The components of the second resonant converter are C _in2 , S ₅ - S ₈ , C₅ - C₈ , C _r2 , L _r2 , T₂ , D ₃ , D ₄ and C_o . C _f1 and C _f2 are used to balance v _Cin1 and v _Cin2 in every switching cycle. The voltage stress of each power switch is clamped at V_in /2. Therefore, MOSFETs with 500V or 600V of voltage stress can be used at the 800V input voltage condition. The pulse frequency modulation scheme is adopted to regulate the output voltage. If the switching frequency is less than the series resonant frequency at the full load and maximum input voltage case, the power switches S ₁ - S ₈ are turned on at ZVS and the rectifier diodes D ₁ - D ₄ are turned off at ZCS. Thus, the switching losses of the power switches are reduced and the reverse recovery losses of the rectifier diodes are improved. v _Cin1 and v _Cin2 v _{Cin 1} In this section, the system analysis and operation principle of the proposed converter are discussed assuming the following assumptions. 1) The transformers T₁ and T₂ have the same magnetizing inductances L _m1 = L _m2 = L_m and turns ratios n = n_p / n _s1 = n_p / n _s2 , 2) S ₁ - S ₈ are ideal and have the same output capacitances C₁ =...= C₈ = C_oss , 3) the diodes D ₁ - D ₄ areideal, 4) the resonant inductances L _r1 = L _r2 = L_r , 5) the resonant capacitances C _r1 = C _r2 = C_r , 6) C_o is large enough that V_o is a constant voltage, 7) V _Cin1 = V _Cin2 = V _Cf1 = V _Cf2 = V_in /2, and 8) C _in1 = C _in2 and C _f1 = C _f2 . Pulse frequency modulation is adopted to change the input impedance of the proposed converter so that the output voltage is regulated at a desired voltage value against different input voltage and load conditions. Based on the on/off states of S ₁ - S ₈ and D ₁ - D ₄ , six operating modes can be derived in a switching period. Fig. 2 shows the key PWM waveforms of the proposed converter. The duty cycle of S ₁ - S ₈ is 0.5. S ₁ , S ₄ , S ₅ and S ₈ have the same PWM waveforms. In the same manner, S ₂ , S ₃ , S ₆ and S ₇ have the same PWM waveforms. However, the PWM waveforms of S ₁ and S ₂ are complementary each other. The equivalent circuits of each operation mode are shown in Fig. 3 . Before time t ₀ , S ₁ - S ₈ , D ₂ and D ₄ are all in the off-state. The capacitors C₁ , C₄ , C₅ and C₈ are discharged, and C₂ , C₃ , C₆ and C₇ are charged. Mode 1 [t₀ - t₁]: At t ₀ , C₁ , C₄ , C₅ and C₈ are discharged to zero voltage. Since i _Lr1 and i _Lr2 are both negative, the anti-parallel diodes of S ₁ , S ₄ , S ₅ and S ₈ are conducting. Therefore, S ₁ , S ₄ , S ₅ and S ₈ can be turned on at this moment to achieve ZVS. The flying capacitor voltages v _Cf1 = V _Cin1 and v _Cf2 = v _Cin2 . The voltage stresses of S ₂ and S ₃ are equal to V _Cin1 , and the voltage stresses of S ₆ and S ₇ are equal to V _Cin2 . In resonant circuit 1, i _Lr1 > i _Lm1 and the diode D ₁ conducts. Thus, v _Lm1 = nV_o and i _Lm1 is increasing in this mode. C _r1 and L _r1 are resonant with the initial voltage V_in /2- nV_o - v _Cr1 ( t ₀ ). Similarly, C _r2 and L _r2 are resonant with the initial voltage V_in /2- nV_o - v _Cr2 ( t ₀ ) in the second resonant circuit, and i _Lm2 is also increasing. The input power is transferred to the output load through ( S ₁ , L _r1 , T₁ , S ₄ , D ₁ ) in resonant circuit 1 and ( S ₅ , L _r2 , T₂ , S ₈ , D ₃ ) resonant circuit 2. Thus, the resonant inductor currents and the capacitor voltages in this mode are expressed as: where Mode 2 [t₁ - t₂]: At t ₁ , i _Lr1 = i _Lm1 and i _Lr2 = i _Lm2 . Then, the diodes D ₁ - D ₄ are off in this mode. Since S ₁ and S ₄ are still conducting, C _r1 , L _r1 and L _m1 are resonant in resonant circuit 1. In the same manner, S ₅ and S ₈ are still conducting so that C _r2 , L _r2 and L _m2 are resonant in resonant circuit 2. Thus, i _Lr1 , i _Lr2 , v _Cr1 and v _Cr2 are expressed as: where Mode 3 [t₂ - t₃]: At t ₂ , S ₁ , S ₄ , S ₅ and S ₈ are turned off and the diodes D ₂ and D ₄ are conducting. Thus, v _Lm1 = v _Lm2 =- nV_o . The magnetizing currents i _Lm1 and i _Lm2 decrease with a slope of - nV_o / L_m . Since i _Lr1 ( t ₂ )>0 and i _Lr2 ( t ₂ )>0, C₁ , C₄ , C₅ and C₈ are charged and C₂ , C₃ , C₆ and C₇ are discharged. If the energy stored in L _r1 and L _r2 at t ₂ is greater than the energy stored in C₁ - C₈ , then C₂ , C₃ , C₆ and C₇ can be discharged to zero voltage at time t ₃ . Mode 4 [t₃ - t₄]: At t ₃ , C₂ , C₃ , C₆ and C₇ are discharged to zero voltage and the anti-parallel diodes of S ₂ , S ₃ , S ₆ and S ₇ are conducting. Before i _Lr1 and i _Lr2 become negative, S ₂ , S ₃ , S ₆ and S ₇ can be turned on at this moment under ZVS. Since D ₂ and D ₄ are conducting, v _Lm1 = v _Lm2 =- nV_o . Thus, i _Lm1 and i _Lm2 decrease in this mode. The voltage stresses of S ₁ and S ₄ are equal to V _Cin1 , and the voltage stresses of S ₅ and S ₈ are equal to V _Cin2 . The flying capacitor voltages v _Cf1 = V _Cin2 and v _Cf2 = v _Cin1 . In circuit module 1, C _r1 and L _r1 are resonant with the initial voltage nV_o - V_in /2- v _Cr1 ( t ₃ ). Similarly, C _r2 and L _r2 are resonant with the initial voltage nV_o - V_in /2- v _Cr2 ( t ₃ ) in the second resonant circuit. The input power is transferred to the output load through S ₃ , L _r1 , T₁ , S ₂ and D ₂ in resonant circuit 1 and through S ₇ , L _r2 , T₂ , S ₆ and D ₄ in resonant circuit 2. Mode 5 [t₄ - t₅]: At t ₄ , i _Lr1 = i _Lm1 and i _Lr2 = i _Lm2 . Thus, the diodes D ₁ - D ₄ are off. Since S ₂ , S ₃ , S ₆ and S ₇ are still in the on-state, C _r1 , L _r1 and L _m1 are resonant in circuit 1, and C _r2 , L _r2 and L _m2 are resonant in circuit 2. The flying capacitor voltages v _Cf1 = V _Cin2 and v _Cf2 = v _Cin1 in this mode. Mode 6 [t₅ - T_s+t₀]: At t ₅ , S ₂ , S ₃ , S ₆ and S ₇ are turned off and the diodes D ₁ and D ₃ are conducting. The magnetizing voltages v _Lm1 = v _Lm2 = nV_o . Thus, i _Lm1 and i _Lm2 increase in this mode. Since i _Lr1 and i _Lr2 are negative, C₁ , C₄ , C₅ and C₈ are discharged and C₂ , C₃ , C₆ and C₇ are charged. If the energy stored in L _r1 and L _r2 at t ₅ is greater than the energy stored in C₁ - C₈ , then C₁ , C₄ , C₅ and C₈ can be discharged to zero voltage at time T_s + t ₀ . Then, the operating modes of the proposed converter in a switching cycle are complete. The output voltage of the proposed converter is based on pulse frequency modulation. Thus, the fundamental harmonic approach with a variable switching frequency is used to approximately analyze the steady state of the proposed converter. The power transfer from the input terminal to the output load through two full-bridge resonant tanks is depended on the switching frequency. All of the harmonics of the switching frequency are neglected in the following discussion. Fig. 4 shows an equivalent circuit of the proposed converter for the derivation of the steady state model. The equivalent circuit components in the two resonant tanks are identical. Each resonant tank is supplied one-half of the input power to the output load. Since the duty ratio of each power switch is equal to 0.5, the input AC voltages v_ab and v_cd of the resonant tanks are square waveforms with two voltage levels V_in /2 and - V_in /2. The AC voltages v_ab and v_cd can be expressed as the fundamental frequency term and the harmonics term. From (25), the fundamental root-mean-square ( rms ) value of v_ab and v_cd is equal to . Due to the on-off states of D ₁ - D ₄ , the fundamental rms value of the magnetizing voltages is expressed as v _Lm1,rms = v _Lm2,rms = . Since the average output current of each center-tapped rectifier is equal to I_o /2, the rms value of the secondary winding currents is equal to i _T1,s,rms = i _T2,s,rms = . Therefore, the load resistance R_o reflected to the transformer primary side can be expressed as: The resonant tank is excited by an effectively fundamental sinusoidal input voltage v_f and it drives the effective AC resistive load R_ac . The pulse frequency modulation (PFM) scheme is adopted to regulate the AC voltage gain of the proposed converter. The AC voltage gain of the resonant tank can be expressed as: where , k = L_r / L_m , C _r1 = C _r2 = C_r , L _r1 = L _r2 = L_r and f_s is the switching frequency. The DC voltage gain G_dc of the proposed converter is given as: where V_f is the voltage drop on the rectifier diodes D ₁ - D ₄ . If the input and output DC voltages are given, the operating switching frequency can be obtained by G_dc = G_ac . A laboratory prototype is implemented with the following specifications: V_in =750V-800V, V_o =48V, P_o =1500W and the series resonant frequency f_r =120kHz. The primary and secondary winding turns of the transformers T₁ and T₂ are 34 turns and 4 turns, respectively. Thus, the minimum and maximum DC voltage gains of the resonant converter are expressed as: The AC equivalent resistance R_ac at the full load condition is given as: In the prototype circuit, the selected inductance ratio of L_r and L_m is k = L_r / L_m =0.2. Based on (27), (29) and (30), the AC voltage gain curves of the proposed converter with different quality factors Q and frequency ratios F at k =0.2 are illustrated in Fig. 5 . From Fig. 5 , it is observed that the output voltage can be regulated if the quality factor Q ≤ 0.5 at a full load. Therefore, Q =0.5 at a full load is selected in the prototype circuit. The AC voltage gain of the proposed converter at the no load condition ( Q =0) is given as: Therefore, the output voltage V_o can be regulated at the no load condition. Based on the derived R_ac , k , Q and f_r , the resonant inductances, the magnetizing inductances and the resonant capacitances can be obtained. The voltage stress of S ₁ - S ₈ is equal to V_in,max /2=400V. MOSFETs (IRFP460) with 500V/20A ratings are selected for S ₁ - S ₈ . The voltage stress and average current of D ₁ - D ₆ are equal to 2( V_o + V_f ) = 98.2V and I_o,max / 4 ≈ 7.8A , respectively. Diodes (KCU30A30) with 300V/30A ratings and a 1.1V voltage drop are adopted for D ₁ - D ₄ . The adopted capacitances C _in1 = C _in2 =470μF/450V, C _f1 = C _f2 =100nF/630V and C_o =2200μF/100V. Experiments with a prototype circuit, with the circuit components derived in the previous section, are provided to demonstrate the performance of the proposed converter. Fig. 6 shows the measured gate voltages of S ₁ - S ₈ at a full load with the input voltage V_in =750V and 800V conditions. Fig. 7 illustrates the measured gate voltage, drain voltage and switch current of S ₁ at light (25%) and full (100%) loads with different input voltages. Before S ₁ is turned on, i _S1 is negative to discharge the drain-to-source capacitor of S ₁ . Therefore, S ₁ can be turned on under ZVS when the drain voltage v _S1,ds is decreased to zero voltage. Since S ₄ , S ₅ and S ₈ have the same PWM waveforms as S ₁ , it is clear that S ₄ , S ₅ and S ₈ are also turned on under ZVS from a 25% load to a full load. Fig. 8 shows the measured gate voltage, drain voltage and switch current of S ₂ at light (25%) and full (100%) loads with different input voltages. S ₂ is also turned on under ZVS from a 25% load to a full load. Since the PWM signals of S ₃ , S ₆ and S ₇ are identical to the PWM signal of S ₂ , it can be determined that S ₃ , S ₆ and S ₇ are also turned on under ZVS. Fig. 9 gives the measured results of the gate voltages, AC terminal voltages, resonant inductor currents and resonant capacitor voltages at a full load. The two inductor currents and the two capacitor voltages are balanced under the test results. Fig. 10 gives the measured switch currents i _S1 and i _S2 , inductor current i _Lr1 and flying capacitor current i _Cf1 at a full load. In the same manner, the measured switch currents i _S1 and i _S2 , inductor current i _Lr1 and flying capacitor current i _Cf1 at a full load are shown in Fig. 11 . When the switches S ₁ and S ₅ are in the on-state and S ₂ and S ₆ are in the off-state, the flying capacitor voltage V _Cf1 is equal to the input capacitor voltage V _Cin1 with half of a switching period. Similarly, the flying capacitor voltage V _Cf1 = V _Cin2 when the switches S ₁ and S ₅ are in the off-state and S ₂ and S ₆ are in the on-state with half of a switching period. Therefore, both of the input capacitor voltages V _Cin1 and V _Cin2 are automatically balanced at V_in /2. Fig. 12 gives test results for the two input capacitor voltages v _Cin1 and v _Cin2 and the two flying capacitor voltages at the full load and 800V input voltage case. It is clear that the two input capacitor voltages v _Cin1 and v _Cin2 are balanced at 400V and v _Cf1 = v _Cf2 = v _Cin1 = v _Cin2 = V_in /2. Fig. 13 shows the measured diode currents and two circuit output currents at the full load condition. The output currents i _o1 and i _o2 are balanced. Fig. 14 shows the measured circuit efficiencies of the proposed converter under different load and input voltage conditions. This paper presents a new full-bridge resonant converter with the characteristics of low voltages stress MOSFETs, ZVS turn-on for the MOSFETs, no reverse recovery current on the rectifier diodes, balanced two input capacitor voltages and high circuit efficiency. Two half-bridge converter legs with two spilt capacitors are adopted to reduce the voltage stress of the MOSFETs at V_in /2. Therefore, the proposed converter is suitable for use in high input voltage applications. The two flying capacitors C _f1 and C _f2 are used to automatically balance the two input capacitor voltages in every switching cycle. The two resonant circuits are used to increase the load power and to achieve ZVS for all of the power semiconductors. The system analysis, a design example and experiments are presented to demonstrate the effectiveness of the proposed converter. Bor-Ren Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics. His current research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, the 2009 IEEE–Power Electronics and Drive Systems Conference, the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEE-International Conference on Industrial Technology. Zih-Yong Chen received his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC), in 2014. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.