This paper presents a new resonant converter to achieve the soft switching of power devices. Two fullbridge converters are connected in series to clamp the voltage stress of power switches at
V_{in}
/2. Thus, power MOSFETs with a 500V voltage rating can be used for 800V input voltage applications. Two flying capacitors are connected on the AC side of the two fullbridge converters to automatically balance the two split input capacitor voltages in every switching cycle. Two resonant tanks are used in the proposed converter to share the load current and to reduce the current stress of the passive and active components. If the switching frequency is less than the series resonant frequency of the resonant tanks, the power MOSFETs can be turned on under zero voltage switching, and the rectifier diodes can be turned off under zero current switching. The switching losses on the power MOSFETs are reduced and the reverse recovery loss is improved. Experiments with a 1.5kW prototype are provided to demonstrate the performance of the proposed converter.
I. INTRODUCTION
Threelevel converters or inverters have been proposed for high voltage applications such as high speed railway electrical systems
[1]
, threephase high power factor correction converters, ship electric power distribution systems
[2]
, reactive power compensators
[3]

[5]
and AC motor systems
[6]

[8]
. Threelevel converters/inverters
[3]

[8]
with a neutralpoint diode clamp, a capacitor clamp or series Hbridge topologies have been proposed and developed to decrease the voltage stress of power devices and to increase the switching frequency. As a result, the size of the passive components can be decreased. For modern power converters, a compact size, high power density and high circuit efficiency are normally required. Thus, threelevel converters
[9]

[14]
with zero voltage switching (ZVS) have been proposed to reduce the switching losses on power devices at a desired load range. Based on the resonant behavior due to the leakage inductance and resonant capacitance, the power switches can be turned on under ZVS during the transition interval. However, the ZVS range of power switches depends on the load power and input voltage conditions. Thus, it is very difficult to design a ZVS threelevel converter with a wide range of load conditions. Recently, resonant converters
[14]

[16]
have received a lot of attention due to their essential advantages in terms of a high conversion efficiency and a wide ZVS range of the load condition. If the switching frequency is less than the series resonant frequency, the rectifier diodes at the secondary side are operated under zero current switching (ZCS) and the power switches are operated under ZVS turnon. Thus, the reverse recovery losses of the diode rectifier are improved and the switching losses of the power switches are reduced. However, the voltage stress of the power switches in a conventional resonant converter is equal to the input voltage. In conventional threelevel resonant converters
[17]
,
[18]
, the input split voltages cannot be balanced automatically in every switching cycle.
This paper presents a new resonant converter with the functions of a low voltage stress of the power switches, low switching losses and balanced input capacitor voltages in every switching cycle. Two fullbridge resonant converters are connected in series at the high voltage side to limit the voltage stress of the power switch at
V_{in}
/2. The secondary sides of the two fullbridge converters are connected in parallel to share the load current and to reduce the size of the active and passive components. In order to balance the two input capacitor voltages, two flying capacitors are connected between the AC sides of the two fullbridge converter legs. Thus, the input capacitor voltages can be automatically balanced in each switching cycle. Pulse frequency modulation is adopted to regulate the output voltage. The input impedance of the resonant converter is controlled as an inductive load at the switching frequency. Thus, the power switches can be turned on under ZVS with a wide range of load conditions. If the switching frequency is lower than the series resonant frequency, the rectifier diodes can be turned off under ZCS. The system analysis, circuit characteristics and a design example of the prototype circuit are discussed in detail. Finally, experiments are provided to demonstrate the performance of the proposed converter.
II. PROPOSED CONVERTER
Fig. 1
(a) shows a block diagram of a general twostage AC/DC converter. The front stage is a threephase power factor corrector (PFC) to achieve a high power factor and to obtain a stable DC bus voltage
V_{in}
. The second stage is a DC/DC converter to provide a stable output voltage against load current variations.
Fig. 1
(b) shows a circuit diagram of a conventional threephase bidirectional PFC. In this circuit, energy can be transferred from an AC source to a DC load or from a DC load to an AC source. The output DC voltage
V_{in}
of a threephase PFC is normally regulated at 750V800V.
Fig. 1
(c) presents a circuit diagram of the proposed new DC/DC converter. Two fullbridge resonant converters are connected in series at the high voltage side to reduce the voltage stress of the power switches and to achieve high circuit efficiency due to ZVS turnon for each power switch. The secondary sides of these two converters are connected in parallel in order to reduce the current stress of the passive and active components. In order to automatically balance the two input split capacitor voltages
v_{Cin1}
and
v_{Cin2}
, two flying capacitors
C_{f1}
and
C_{f2}
are connected at the AC terminal points (
a
,
c
) and (
b, d
). Thus, the two split capacitor voltages and the two flying voltages are automatically balanced,
v
_{Cin1}
=
v
_{Cin2}
=
v
_{Cf1}
=
v
_{Cf2}
=
V_{in}
/2, in a switching cycle.
C
_{in1}
and
C
_{in2}
are input split capacitances.
S
_{1}

S
_{8}
are power MOSFETs.
L
_{r1}
and
L
_{r2}
are resonant inductances.
C
_{r1}
and
C
_{r2}
are resonant capacitances.
C_{1}

C_{8}
are the output capacitances of
S
_{1}

S
_{8}
, respectively.
D
_{1}

D
_{4}
are the rectifier diodes at the output side.
L
_{m1}
and
L
_{m2}
are the magnetizing inductances of the transformers
T_{1}
and
T_{2}
, respectively.
C_{o}
is output capacitance. The first resonant converter includes
C
_{in1}
,
S
_{1}

S
_{4}
,
C_{1}

C_{4}
,
C
_{r1}
,
L
_{r1}
,
T_{1}
,
D
_{1}
,
D
_{2}
and
C_{o}
. The components of the second resonant converter are
C
_{in2}
,
S
_{5}

S
_{8}
,
C_{5}

C_{8}
,
C
_{r2}
,
L
_{r2}
,
T_{2}
,
D
_{3}
,
D
_{4}
and
C_{o}
.
C
_{f1}
and
C
_{f2}
are used to balance
v
_{Cin1}
and
v
_{Cin2}
in every switching cycle. The voltage stress of each power switch is clamped at
V_{in}
/2. Therefore, MOSFETs with 500V or 600V of voltage stress can be used at the 800V input voltage condition. The pulse frequency modulation scheme is adopted to regulate the output voltage. If the switching frequency is less than the series resonant frequency at the full load and maximum input voltage case, the power switches
S
_{1}

S
_{8}
are turned on at ZVS and the rectifier diodes
D
_{1}

D
_{4}
are turned off at ZCS. Thus, the switching losses of the power switches are reduced and the reverse recovery losses of the rectifier diodes are improved.
Circuit diagram. (a) Twostage AC/DC converter. (b) Front stage with a general threephase PFC. (c) Proposed ZVS DC/DC converter with two fullbridge resonant circuits and two flying capacitors.
v
_{Cin1}
and
v
_{Cin2}
v
_{Cin}
_{1}
III. OPERATION PRINCIPLES
In this section, the system analysis and operation principle of the proposed converter are discussed assuming the following assumptions. 1) The transformers
T_{1}
and
T_{2}
have the same magnetizing inductances
L
_{m1}
=
L
_{m2}
=
L_{m}
and turns ratios
n
=
n_{p}
/
n
_{s1}
=
n_{p}
/
n
_{s2}
, 2)
S
_{1}

S
_{8}
are ideal and have the same output capacitances
C_{1}
=...=
C_{8}
=
C_{oss}
, 3) the diodes
D
_{1}

D
_{4}
areideal, 4) the resonant inductances
L
_{r1}
=
L
_{r2}
=
L_{r}
, 5) the resonant capacitances
C
_{r1}
=
C
_{r2}
=
C_{r}
, 6)
C_{o}
is large enough that
V_{o}
is a constant voltage, 7)
V
_{Cin1}
=
V
_{Cin2}
=
V
_{Cf1}
=
V
_{Cf2}
=
V_{in}
/2, and 8)
C
_{in1}
=
C
_{in2}
and
C
_{f1}
=
C
_{f2}
. Pulse frequency modulation is adopted to change the input impedance of the proposed converter so that the output voltage is regulated at a desired voltage value against different input voltage and load conditions. Based on the on/off states of
S
_{1}

S
_{8}
and
D
_{1}

D
_{4}
, six operating modes can be derived in a switching period.
Fig. 2
shows the key PWM waveforms of the proposed converter. The duty cycle of
S
_{1}

S
_{8}
is 0.5.
S
_{1}
,
S
_{4}
,
S
_{5}
and
S
_{8}
have the same PWM waveforms. In the same manner,
S
_{2}
,
S
_{3}
,
S
_{6}
and
S
_{7}
have the same PWM waveforms. However, the PWM waveforms of
S
_{1}
and
S
_{2}
are complementary each other. The equivalent circuits of each operation mode are shown in
Fig. 3
. Before time
t
_{0}
,
S
_{1}

S
_{8}
,
D
_{2}
and
D
_{4}
are all in the offstate. The capacitors
C_{1}
,
C_{4}
,
C_{5}
and
C_{8}
are discharged, and
C_{2}
,
C_{3}
,
C_{6}
and
C_{7}
are charged.
Key waveforms of the proposed converter.
Operation modes of the proposed converter in one switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.
Mode 1 [t_{0}  t_{1}]:
At
t
_{0}
,
C_{1}
,
C_{4}
,
C_{5}
and
C_{8}
are discharged to zero voltage. Since
i
_{Lr1}
and
i
_{Lr2}
are both negative, the antiparallel diodes of
S
_{1}
,
S
_{4}
,
S
_{5}
and
S
_{8}
are conducting. Therefore,
S
_{1}
,
S
_{4}
,
S
_{5}
and
S
_{8}
can be turned on at this moment to achieve ZVS. The flying capacitor voltages
v
_{Cf1}
=
V
_{Cin1}
and
v
_{Cf2}
=
v
_{Cin2}
. The voltage stresses of
S
_{2}
and
S
_{3}
are equal to
V
_{Cin1}
, and the voltage stresses of
S
_{6}
and
S
_{7}
are equal to
V
_{Cin2}
. In resonant circuit 1,
i
_{Lr1}
>
i
_{Lm1}
and the diode
D
_{1}
conducts. Thus,
v
_{Lm1}
=
nV_{o}
and
i
_{Lm1}
is increasing in this mode.
C
_{r1}
and
L
_{r1}
are resonant with the initial voltage
V_{in}
/2
nV_{o}

v
_{Cr1}
(
t
_{0}
). Similarly,
C
_{r2}
and
L
_{r2}
are resonant with the initial voltage
V_{in}
/2
nV_{o}

v
_{Cr2}
(
t
_{0}
) in the second resonant circuit, and
i
_{Lm2}
is also increasing. The input power is transferred to the output load through (
S
_{1}
,
L
_{r1}
,
T_{1}
,
S
_{4}
,
D
_{1}
) in resonant circuit 1 and (
S
_{5}
,
L
_{r2}
,
T_{2}
,
S
_{8}
,
D
_{3}
) resonant circuit 2. Thus, the resonant inductor currents and the capacitor voltages in this mode are expressed as:
where
Mode 2 [t_{1}  t_{2}]:
At
t
_{1}
,
i
_{Lr1}
=
i
_{Lm1}
and
i
_{Lr2}
=
i
_{Lm2}
. Then, the diodes
D
_{1}

D
_{4}
are off in this mode. Since
S
_{1}
and
S
_{4}
are still conducting,
C
_{r1}
,
L
_{r1}
and
L
_{m1}
are resonant in resonant circuit 1. In the same manner,
S
_{5}
and
S
_{8}
are still conducting so that
C
_{r2}
,
L
_{r2}
and
L
_{m2}
are resonant in resonant circuit 2. Thus,
i
_{Lr1}
,
i
_{Lr2}
,
v
_{Cr1}
and
v
_{Cr2}
are expressed as:
where
Mode 3 [t_{2}  t_{3}]:
At
t
_{2}
,
S
_{1}
,
S
_{4}
,
S
_{5}
and
S
_{8}
are turned off and the diodes
D
_{2}
and
D
_{4}
are conducting. Thus,
v
_{Lm1}
=
v
_{Lm2}
=
nV_{o}
. The magnetizing currents
i
_{Lm1}
and
i
_{Lm2}
decrease with a slope of 
nV_{o}
/
L_{m}
. Since
i
_{Lr1}
(
t
_{2}
)>0 and
i
_{Lr2}
(
t
_{2}
)>0,
C_{1}
,
C_{4}
,
C_{5}
and
C_{8}
are charged and
C_{2}
,
C_{3}
,
C_{6}
and
C_{7}
are discharged.
If the energy stored in
L
_{r1}
and
L
_{r2}
at
t
_{2}
is greater than the energy stored in
C_{1}

C_{8}
, then
C_{2}
,
C_{3}
,
C_{6}
and
C_{7}
can be discharged to zero voltage at time
t
_{3}
.
Mode 4 [t_{3}  t_{4}]:
At
t
_{3}
,
C_{2}
,
C_{3}
,
C_{6}
and
C_{7}
are discharged to zero voltage and the antiparallel diodes of
S
_{2}
,
S
_{3}
,
S
_{6}
and
S
_{7}
are conducting. Before
i
_{Lr1}
and
i
_{Lr2}
become negative,
S
_{2}
,
S
_{3}
,
S
_{6}
and
S
_{7}
can be turned on at this moment under ZVS. Since
D
_{2}
and
D
_{4}
are conducting,
v
_{Lm1}
=
v
_{Lm2}
=
nV_{o}
. Thus,
i
_{Lm1}
and
i
_{Lm2}
decrease in this mode. The voltage stresses of
S
_{1}
and
S
_{4}
are equal to
V
_{Cin1}
, and the voltage stresses of
S
_{5}
and
S
_{8}
are equal to
V
_{Cin2}
. The flying capacitor voltages
v
_{Cf1}
=
V
_{Cin2}
and
v
_{Cf2}
=
v
_{Cin1}
. In circuit module 1,
C
_{r1}
and
L
_{r1}
are resonant with the initial voltage
nV_{o}

V_{in}
/2
v
_{Cr1}
(
t
_{3}
). Similarly,
C
_{r2}
and
L
_{r2}
are resonant with the initial voltage
nV_{o}

V_{in}
/2
v
_{Cr2}
(
t
_{3}
) in the second resonant circuit.
The input power is transferred to the output load through
S
_{3}
,
L
_{r1}
,
T_{1}
,
S
_{2}
and
D
_{2}
in resonant circuit 1 and through
S
_{7}
,
L
_{r2}
,
T_{2}
,
S
_{6}
and
D
_{4}
in resonant circuit 2.
Mode 5 [t_{4}  t_{5}]:
At
t
_{4}
,
i
_{Lr1}
=
i
_{Lm1}
and
i
_{Lr2}
=
i
_{Lm2}
. Thus, the diodes
D
_{1}

D
_{4}
are off. Since
S
_{2}
,
S
_{3}
,
S
_{6}
and
S
_{7}
are still in the onstate,
C
_{r1}
,
L
_{r1}
and
L
_{m1}
are resonant in circuit 1, and
C
_{r2}
,
L
_{r2}
and
L
_{m2}
are resonant in circuit 2.
The flying capacitor voltages
v
_{Cf1}
=
V
_{Cin2}
and
v
_{Cf2}
=
v
_{Cin1}
in this mode.
Mode 6 [t_{5}  T_{s}+t_{0}]:
At
t
_{5}
,
S
_{2}
,
S
_{3}
,
S
_{6}
and
S
_{7}
are turned off and the diodes
D
_{1}
and
D
_{3}
are conducting. The magnetizing voltages
v
_{Lm1}
=
v
_{Lm2}
=
nV_{o}
. Thus,
i
_{Lm1}
and
i
_{Lm2}
increase in this mode. Since
i
_{Lr1}
and
i
_{Lr2}
are negative,
C_{1}
,
C_{4}
,
C_{5}
and
C_{8}
are discharged and
C_{2}
,
C_{3}
,
C_{6}
and
C_{7}
are charged.
If the energy stored in
L
_{r1}
and
L
_{r2}
at
t
_{5}
is greater than the energy stored in
C_{1}

C_{8}
, then
C_{1}
,
C_{4}
,
C_{5}
and
C_{8}
can be discharged to zero voltage at time
T_{s}
+
t
_{0}
. Then, the operating modes of the proposed converter in a switching cycle are complete.
IV. CONVERTER PERFORMANCE ANALYSIS
The output voltage of the proposed converter is based on pulse frequency modulation. Thus, the fundamental harmonic approach with a variable switching frequency is used to approximately analyze the steady state of the proposed converter. The power transfer from the input terminal to the output load through two fullbridge resonant tanks is depended on the switching frequency. All of the harmonics of the switching frequency are neglected in the following discussion.
Fig. 4
shows an equivalent circuit of the proposed converter for the derivation of the steady state model. The equivalent circuit components in the two resonant tanks are identical. Each resonant tank is supplied onehalf of the input power to the output load. Since the duty ratio of each power switch is equal to 0.5, the input AC voltages
v_{ab}
and
v_{cd}
of the resonant tanks are square waveforms with two voltage levels
V_{in}
/2 and 
V_{in}
/2. The AC voltages
v_{ab}
and
v_{cd}
can be expressed as the fundamental frequency term and the harmonics term.
Equivalent circuit of the proposed converter for the derivation of steady state model.
From (25), the fundamental rootmeansquare (
rms
) value of
v_{ab}
and
v_{cd}
is equal to
. Due to the onoff states of
D
_{1}

D
_{4}
, the fundamental
rms
value of the magnetizing voltages is expressed as
v
_{Lm1,rms}
=
v
_{Lm2,rms}
=
. Since the average output current of each centertapped rectifier is equal to
I_{o}
/2, the
rms
value of the secondary winding currents is equal to
i
_{T1,s,rms}
=
i
_{T2,s,rms}
=
. Therefore, the load resistance
R_{o}
reflected to the transformer primary side can be expressed as:
The resonant tank is excited by an effectively fundamental sinusoidal input voltage
v_{f}
and it drives the effective AC resistive load
R_{ac}
. The pulse frequency modulation (PFM) scheme is adopted to regulate the AC voltage gain of the proposed converter. The AC voltage gain of the resonant tank can be expressed as:
where
,
k
=
L_{r}
/
L_{m}
,
C
_{r1}
=
C
_{r2}
=
C_{r}
,
L
_{r1}
=
L
_{r2}
=
L_{r}
and
f_{s}
is the switching frequency. The DC voltage gain
G_{dc}
of the proposed converter is given as:
where
V_{f}
is the voltage drop on the rectifier diodes
D
_{1}

D
_{4}
. If the input and output DC voltages are given, the operating switching frequency can be obtained by
G_{dc}
=
G_{ac}
.
A laboratory prototype is implemented with the following specifications:
V_{in}
=750V800V,
V_{o}
=48V,
P_{o}
=1500W and the series resonant frequency
f_{r}
=120kHz. The primary and secondary winding turns of the transformers
T_{1}
and
T_{2}
are 34 turns and 4 turns, respectively. Thus, the minimum and maximum DC voltage gains of the resonant converter are expressed as:
The AC equivalent resistance
R_{ac}
at the full load condition is given as:
In the prototype circuit, the selected inductance ratio of
L_{r}
and
L_{m}
is
k
=
L_{r}
/
L_{m}
=0.2. Based on (27), (29) and (30), the AC voltage gain curves of the proposed converter with different quality factors
Q
and frequency ratios
F
at
k
=0.2 are illustrated in
Fig. 5
. From
Fig. 5
, it is observed that the output voltage can be regulated if the quality factor Q ≤ 0.5 at a full load. Therefore,
Q
=0.5 at a full load is selected in the prototype circuit. The AC voltage gain of the proposed converter at the no load condition (
Q
=0) is given as:
Gain curves of proposed resonant converter with V_{in,min}=750V and V_{in,max}=800V.
Therefore, the output voltage
V_{o}
can be regulated at the no load condition. Based on the derived
R_{ac}
,
k
,
Q
and
f_{r}
, the resonant inductances, the magnetizing inductances and the resonant capacitances can be obtained.
The voltage stress of
S
_{1}

S
_{8}
is equal to
V_{in,max}
/2=400V. MOSFETs (IRFP460) with 500V/20A ratings are selected for
S
_{1}

S
_{8}
. The voltage stress and average current of
D
_{1}

D
_{6}
are equal to 2(
V_{o}
+
V_{f}
) = 98.2V and
I_{o,max}
/ 4 ≈ 7.8A , respectively. Diodes (KCU30A30) with 300V/30A ratings and a 1.1V voltage drop are adopted for
D
_{1}

D
_{4}
. The adopted capacitances
C
_{in1}
=
C
_{in2}
=470μF/450V,
C
_{f1}
=
C
_{f2}
=100nF/630V and
C_{o}
=2200μF/100V.
V. EXPERIMENTAL RESULTS
Experiments with a prototype circuit, with the circuit components derived in the previous section, are provided to demonstrate the performance of the proposed converter.
Fig. 6
shows the measured gate voltages of
S
_{1}

S
_{8}
at a full load with the input voltage
V_{in}
=750V and 800V conditions.
Fig. 7
illustrates the measured gate voltage, drain voltage and switch current of
S
_{1}
at light (25%) and full (100%) loads with different input voltages. Before
S
_{1}
is turned on,
i
_{S1}
is negative to discharge the draintosource capacitor of
S
_{1}
. Therefore,
S
_{1}
can be turned on under ZVS when the drain voltage
v
_{S1,ds}
is decreased to zero voltage. Since
S
_{4}
,
S
_{5}
and
S
_{8}
have the same PWM waveforms as
S
_{1}
, it is clear that
S
_{4}
,
S
_{5}
and
S
_{8}
are also turned on under ZVS from a 25% load to a full load.
Fig. 8
shows the measured gate voltage, drain voltage and switch current of
S
_{2}
at light (25%) and full (100%) loads with different input voltages.
S
_{2}
is also turned on under ZVS from a 25% load to a full load. Since the PWM signals of
S
_{3}
,
S
_{6}
and
S
_{7}
are identical to the PWM signal of
S
_{2}
, it can be determined that
S
_{3}
,
S
_{6}
and
S
_{7}
are also turned on under ZVS.
Fig. 9
gives the measured results of the gate voltages, AC terminal voltages, resonant inductor currents and resonant capacitor voltages at a full load. The two inductor currents and the two capacitor voltages are balanced under the test results.
Fig. 10
gives the measured switch currents
i
_{S1}
and
i
_{S2}
, inductor current
i
_{Lr1}
and flying capacitor current
i
_{Cf1}
at a full load. In the same manner, the measured switch currents
i
_{S1}
and
i
_{S2}
, inductor current
i
_{Lr1}
and flying capacitor current
i
_{Cf1}
at a full load are shown in
Fig. 11
. When the switches
S
_{1}
and
S
_{5}
are in the onstate and
S
_{2}
and
S
_{6}
are in the offstate, the flying capacitor voltage
V
_{Cf1}
is equal to the input capacitor voltage
V
_{Cin1}
with half of a switching period. Similarly, the flying capacitor voltage
V
_{Cf1}
=
V
_{Cin2}
when the switches
S
_{1}
and
S
_{5}
are in the offstate and
S
_{2}
and
S
_{6}
are in the onstate with half of a switching period. Therefore, both of the input capacitor voltages
V
_{Cin1}
and
V
_{Cin2}
are automatically balanced at
V_{in}
/2.
Fig. 12
gives test results for the two input capacitor voltages
v
_{Cin1}
and
v
_{Cin2}
and the two flying capacitor voltages at the full load and 800V input voltage case. It is clear that the two input capacitor voltages
v
_{Cin1}
and
v
_{Cin2}
are balanced at 400V and
v
_{Cf1}
=
v
_{Cf2}
=
v
_{Cin1}
=
v
_{Cin2}
=
V_{in}
/2.
Fig. 13
shows the measured diode currents and two circuit output currents at the full load condition. The output currents
i
_{o1}
and
i
_{o2}
are balanced.
Fig. 14
shows the measured circuit efficiencies of the proposed converter under different load and input voltage conditions.
Measured gate voltages of S_{1}S_{8} at full load and (a) V_{in}=750V (b) V_{in}=800V.
Measured gate voltage, drain voltage and switch current of S_{1} at (a) 25% load and V_{in}=750V (b) 25% load and V_{in}=800V(c) 100% load and V_{in}=750V(d) 100% load and V_{in}=800V.
Measured gate voltage, drain voltage and switch current of S_{2} at (a) 25% load and V_{in}=750V (b) 25% load and V_{in}=800V(c) 100% load and V_{in}=750V(d) 100% load and V_{in}=800V.
Measured results of the gate voltages v_{S1,gs} and v_{S2,gs}, AC terminal voltages v_{ab} and v_{cd}, resonant inductor currents i_{Lr1} and i_{Lr2}, and resonant capacitor voltages v_{Cr1} and v_{Cr2} at full load.
Measured switch currents i_{S1} and i_{S2}, inductor current i_{Lr1} and flying capacitor current i_{Cf1} at full load.
Measured switch currents i_{S3} and i_{S4}, inductor current i_{Lr1} and flying capacitor current i_{Cf2} at full load.
Measured results of input capacitor voltages and flying capacitor voltages at full load and 800V input voltage case.
Measured diode currents and two circuit output currents at full load condition.
Measured efficiencies of the proposed converter with different input terminal voltages and load conditions.
VI. CONCLUSION
This paper presents a new fullbridge resonant converter with the characteristics of low voltages stress MOSFETs, ZVS turnon for the MOSFETs, no reverse recovery current on the rectifier diodes, balanced two input capacitor voltages and high circuit efficiency. Two halfbridge converter legs with two spilt capacitors are adopted to reduce the voltage stress of the MOSFETs at
V_{in}
/2. Therefore, the proposed converter is suitable for use in high input voltage applications. The two flying capacitors
C
_{f1}
and
C
_{f2}
are used to automatically balance the two input capacitor voltages in every switching cycle. The two resonant circuits are used to increase the load power and to achieve ZVS for all of the power semiconductors. The system analysis, a design example and experiments are presented to demonstrate the effectiveness of the proposed converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022 MY3.
BIO
BorRen Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics. His current research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, the 2009 IEEE–Power Electronics and Drive Systems Conference, the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEEInternational Conference on Industrial Technology.
ZihYong Chen received his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC), in 2014. His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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