This study presents a practical implementation of a multimode twophase interleaved boost converter for fuel cell electric vehicle application. The main operating modes, which include two continuous conducting modes and four discontinuous conducting modes, are discussed. The boundaries and transitions among these modes are analyzed with consideration of the inductor parasitic resistance. The safe operational area is analyzed through a comparison of the different operating modes. The output voltage and power characteristics with openloop or closedloop operation are also discussed. Key performance parameters, including the DC voltage gain, input ripple current, output ripple voltage, and switch stresses, are presented and supported by simulation and experimental results.
I. INTRODUCTION
Fuel cell electric vehicles (FCEVs) have been extensively used nowadays to replace the traditional internal combustion enginebased vehicles because of the advantages of the former in the aspects of high energy density, zero emissions, and high efficiency
[1]

[5]
. Fuel cell (FC) stacks can provide power for the motors, either standalone or combined with renewable energy sources, such as photovoltaic modules or wind turbines
[6]
. Among various FC technologies available for vehicle application, the proton exchange membrane fuel cell (PEMFC) is regarded as the best candidate because of its high power density and low operating temperatures
[7]

[9]
.
Fig. 1
illustrates a typical voltampere characteristic of a 6 kW PEMFC stack, which comprises 65 FCs. The output voltage of the FC stack varies with the stack output current, which is determined with the FCEV output power demand.
Fig. 1
shows that the output voltage of the FC stack in the lowpower region is higher than that in the highpower region.
Voltampere characteristic of fuel cell stacks based on power demands.
FC stacks exhibit good power capability for steadystate operation; however, their dynamic response is relatively low
[10]

[12]
. Thus, energy storage systems (ESS), including batteries or supercapacitors, are required to integrate with the FC stacks to provide high transient current and recover energy during the regenerative braking
[13]
.
Fig. 2
shows the FCEV system topology, including the main power source (PEMFC), high power DCDC converter connecting FC with the highvoltage DC bus, inverter, and motor. An auxiliary power source, including a battery stack or ultracapacitor, is also connected to the highvoltage DC bus via bidirectional DCDC converter for its rapid dynamic response. The total power of the EV DC bus
P_{DC}
is provided by two sources, namely, FC stacks
P_{FC}
and supercapacitors
P_{ESD}
.
Vehicle system topology of FCEV.
For the FC application, a highpower DCDC power interface is the key component to achieve excellent power management and full usage of the FC stacks. High voltage ratio is one of the most important requirements for this DCDC converter.
Fig. 1
shows that FC is the main energy source to power the vehicles, and its voltage changes in a wide range. The current ripple and its harmonic content are also determining factors for the FC lifetime
[14]
,
[15]
. Volume, cost, weight, manufacturing complexity, and efficiency are also major concerns for the highpower DCDC converter.
Several topologies have been discussed in prior studies, including conventional boost converter
[16]
, buckboost converter
[17]
, halfbridge
[18]
or fullbridge converter
[19]
, and pushpull converter
[20]
. Considering the increasing demands in power density, nonisolated DCDC converter is preferred for FCEV application. For the conventional boost converter (CBC), the major concern is the boost inductor because it is the heaviest component in the highpower DCDC converter. A low inductance is preferred to reduce the inductor size and weight. However, this condition will result in high input current ripple and affect the FC stack lifetime. The CBC efficiency is also lower for a higher duty cycle
[21]
,
[22]
. A multidevice structure with interleaved control was proposed in
[12]
to reduce the input current ripples and the passive component size. However, the component number is doubled, which will lower the system reliability. A highgain threelevel boost converter for FCEV vehicle applications was discussed in
[23]
. However, the current control for this topology is complicated and the neutralpoint voltage balance is still a design challenge. An interleaved reducedcomponentcount DCDC converter was discussed in
[24]
in FCEV with a multivoltage electric net. However, this system is difficult to use for high power applications.
From the previous analysis, an interleaved boost converter (IBC) can be used to improve the power density and transient response
[25]
,
[26]
. For lowpower application, the interleaved windingcoupled boost converter is commonly used
[27]

[29]
. However, for FCEV application, the inductor current reaches 600 A, and the coupled inductor is difficult to manufacture. IBC can be controlled to operate in two modes, namely, continuous conduction mode (CCM) or discontinuous conduction mode (DCM). A total of two CCMs and four DCMs are present for a twophase IBC. The input current ripple patterns of a twophase IBC are highly complicated. Thus, discussing the key performance parameters is essential, which include the DC voltage gain, input ripple current, output ripple voltage, and switch stresses that consider the parasitic resistance effects.
In the current study, a practical implementation of a multimode twophase IBC is presented for FCEV applications. Various modes, including two CCMs and four DCMs, are discussed with their equivalent circuits. The effects of the inductor parasitic resistance in the voltage conversion ratio are analyzed. The safe operational area is analyzed through a comparison of the different operation modes. The output voltage and power characteristics with openloop or closedloop operation are discussed. Simulation and experimental result are also presented.
II. IBC OPERATING MODES
Fig. 3
depicts the topology of the twophase IBC. This converter consists of two CBCs interleaved with one IGBT and diodes connected in parallel. The phaseshift interleaved operation will double the inductor current ripple frequency and reduce the size of the inductor. A rapid dynamic response for the converter can also be achieved because of the increased system bandwidth.
Topology of a twophase interleaved boost converter.
For the twophase interleaved IBC, the phase shift between the gate drive signals for
Q1
and
Q2
is180°. The input current is the sum of the two phase currents.
Fig. 1
shows that the operating voltage of the FC stack is changing with different power regions of FCEV. IBC should regulate its duty ratio
D
to provide a certain voltage to the motor inverter. One constraint is that the input current
i_{in}
must be designed in CCM because FC is the main power source in the FCEV system. However, each phase current can operate in either CCM or DCM. Thus, a total of two CCMs and four DCMs are present based on the duty ratio range and input current distribution.
Fig. 4
illustrates the typical IBC waveforms for two CCMs.
Fig. 4
(a) shows that in the lowpower region case, only one inductor current is increasing during 0−
δ_{1}
and all switches are off during
δ_{1}
−
π
. Thus, during
δ_{1}
−
π
, both the inductor and input currents are decreasing. However,
Fig. 4
(b) shows that for the highpower region, at least one phase has an increased inductor current for each stage. During 0−
δ_{1}
and
δ_{2}
−
π
, two inductor currents are increasing for these two stages.
Typical IBC waveforms with CCM. (a) CCMI:0<D<0.5; (b)CCMII:0.5≤D<1.
Fig. 5
illustrates the typical IBC waveforms for DCM. Four operating modes are present based on the duty ratio range and input current distribution. The main differences in these modes are reflected on the boost inductor current waveforms. For DCM, each inductor current has three states, namely, rising, falling, and zero. These three states are symbolized as “R”, “F”, and “Z,” respectively. Thus, considering all the possible combinations of two IBCs, a total of eight operations are possible: “RR,” “RF,” “RZ,” “FR,” “FF,” “FZ,” “ZR,” and “ZF.”
Fig. 6
illustrates the equivalent circuits. These eight equivalent circuits can explain all the operating modes, whether CCM or DCM. DCMII is used as an example to analyze the operation briefly.
Typical IBC waveforms with DCM. (a) DCMI; (b) DCMII; (c) DCMIII; and (d) DCMIV.
Equivalent circuits of the IBC. (a) “RR”; (b) “RF”; (c) “RZ”; (d) “FR”; (e) “FF”; (f) “FZ”; (g) “ZR”; (h) “ZF.”
“
RF
” operation during [0−
δ_{1}
]:
Q_{1}
is turned on and current
i_{L1}
is increasing linearly from zero. Diode
D_{2}
is conducting to freewheel the current
i_{L2}
. Thus,
i_{L2}
is decreasing to zero. Based on the voltsecond balance, the duration of the current
i_{L1}
decreasing to zero is defined as
M
and can be expressed as
where the voltage conversion ratio
d
=
V_{2}
/
V_{1}
. The output capacitor current
i_{C}
during this stage is expressed as
“
RZ
” operation during [
δ_{1}
−
δ_{2}
]:
Q_{1}
is still on and current
i_{L1}
is increasing to the maximum
I_{max_L1}
. Diode
D_{2}
is off during this stage. The input current
i_{in}
is the same as
i_{L1}
. The output capacitor current
i_{C}
is the opposite of the load current
i_{o}
. The current
I_{max_L1}
can be expressed as:
“
FZ
” operation during [
δ_{2}−π
]: Current
i_{L2}
remains constantly zero. Diode
D_{1}
is conducting to freewheel the current
i_{L1}
. Thus, the current
i_{L1}
is decreasing linearly. The output capacitor current
i_{C}
during this stage is expressed as
A similar operation can be analyzed for the rest stages of “
FR
,” “
ZR
,” and “
ZF
.”
TABLE I
shows that all operating modes can be explained by using the eight possible operations.
OPERATING MODES AND MAIN SUBCIRCUITS
OPERATING MODES AND MAIN SUBCIRCUITS
III. MODES DISTRIBUTION AND BOUNDARIES
 A. DCM and CCM
The input current
i_{in}
, which is the sum of
i_{L1}
and
i_{L2}
, can be expressed as
With the dynamics of the currents
i_{L1}
and
i_{L2}
shown in
Fig. 3
, the analytical expressions of current
i_{in}
at the switching angles for each operating mode of IBC can be derived.
TABLE II
shows the expressions of the input current at the switching angles.
EXPRESSIONS OF THE INPUT CURRENT AT THE SWITCHING ANGLES (PU)
EXPRESSIONS OF THE INPUT CURRENT AT THE SWITCHING ANGLES (PU)
For mode I, the relationship of the voltage conversion ratio
d
and the duty cycle
D
can be expressed as
However, the average current of input current
i_{in}
for DCMII can be expressed as
If the power losses in the components are neglected and the equivalent load resistance is
R
, then the IBC power transfer characteristic can be expressed as
Thus,
Define
k
=
R
/
L_{s}f_{s}
; thus, (10) can be simplified as
As shown in (11), the voltage conversion ratio for DCMII is affected by the circuit parameters and load conditions.
Fig. 7
(a) shows the simulated waveforms of “
i_{L1}
,” “
i_{L2}
,” “
i_{in}
,” “
i_{C}
,” and “
v_{out}
” under the condition of “
v_{in}
= 100 V,
v_{out}
= 400 V,
P_{o}
= 2.91 kW.” IBC operates in CCMII. However, for the same
P_{o}
, IBC will operate in DCMIII, as shown in
Fig. 7
(b). By using DCM, the inductance will be reduced from 300 μH to 180 μH, and the input current ripple is merely slightly
Comparison of the simulated waveforms with CCMII and DCMIII. (a) Simulated inductor current and input current waveforms with CCMII; (b) Simulated inductor current and input current waveforms with DCMIII; (d) Comparison of the output voltage ripple; (e) Comparison of the output capacitor current.
increased.
Fig. 7
(c) shows that the output voltage ripple with DCMIII is lower than that with CCMII. The reduction of inductance is beneficial for the size reduction and power density improvement. The power devices can also be operated with ZCS; thus, the switching loss of IGBTs and the reverse recovery loss of the diodes can be reduced
[30]
.
 B. Mode Distribution and Their Boundaries
A total of four criteria determine the mode distribution.
(1)
Boundary I
: The line of D = 0.5 is the boundary line of CCMI and CCMII, DCMIII, and the other three DCMs;
(2)
Boundary II
: The line D = M will distinguish DCMI with DCMII and DCMIV;
(3)
Boundary III
: The difference between DCMII and DCMIV is the current slope of i
_{L1}
and i
_{L2}
during [0, δ
_{1}
]. The boundary line is expressed as
Combining (1) and (13), the boundary line can be derived
(4)
Boundary IV
: For each mode, the total rising and falling duration should be shorter than one switching period. Thus,
The analytical expressions of the voltage conversion ratio and mode boundaries can be obtained and summarized in
TABLE III
.
VOLTAGE CONVERSION RATIO,MODE BOUNDARIES, AND INPUT CURRENT RIPPLES
VOLTAGE CONVERSION RATIO,MODE BOUNDARIES, AND INPUT CURRENT RIPPLES
Based on the boundaries analysis, the modes distributions with their boundaries are shown in
Fig. 8
. The boundary line with expression (16) is changing with the voltage conversion ratio
d
. Expression (1) indicates the relationship between
D
and
M
, which is valid for all DCMs. However, the variable pairs (
D
,
M
) are affected by
d
, the circuit parameters, and load conditions.
Fig. 9
illustrates the mode distribution for various
d
. Two conclusions can be drawn from
Fig. 9
.
Modes distribution with their boundary lines.
Modes distribution for various voltage conversion ratios. (a) d=1.2; (b) d=1.5; (c) d=4; (d) d=10.
(1) DCMI and DCMII are valid for “
d
≤2.”The DCMII distribution is wider for a higher
d
.
(2) DCMIII and DCMIV are valid for “
d
>2.” The DCMIII distribution is wider when the voltage conversion ratio
d
is larger.
Fig. 10
shows the measured waveforms for the different operating modes. The inductor currents
i_{L1}
and
i_{L2}
, and input current
i_{in}
are illustrated and compared. The measured conditions are
V_{out}
= 520 V,
V_{in}
= 280 V to 320 V,
f_{s}
= 10 kHz, and
L_{s}
= 50 μH. The voltage conversion ratio is less than 2; thus, DCMI and DCMII are valid, as shown in
Figs. 10
(a) and (b), respectively. Their output power values are 23 kW and 38 kW, respectively. In the test, the dutycycle ratios are tuned as 38% and 40%. With further increase of the output power, the converter is operating in CCM and the waveforms are shown in
Fig. 10
(c). The inductor current is always larger than zero at any instant. The experimental results verified the effectiveness of the previous theoretical analysis.
Experimental waveforms of inductor current i_{L1} and i_{L2} and input current i_{in} with different operating modes: (a) DCMII with P_{o} = 23 kW; (b) DCMI with P_{o} = 38 kW; and (c) CCM with P_{o} = 57 kW.
IV. KEY DESIGN ISSUES AND VERIFICATION
 A. Effects of Inductor Parasitic Resistance
Expressions (10) and (11) indicate that the DCM output voltage is determined by both dutycycle
D
and circuit parameters
k
. However, each inductor inevitably has the parasitic resistance
r_{i}
(
i
= 1, 2); thus, the output voltage is also affected.
Fig. 6
shows that the state space equations are derived from the equivalent circuits. The IBC steadystate characteristic is expressed as:
where
D_{p}
represents the falling time of the inductor current and is expressed as
Fig. 11
shows the comparison of the theoretical and experimental measured output voltage ratio
d
versus the dutycycle
D
under the condition of “
k
= 40.” The black dotted line represents the ideal voltage conversion ratio. The red dashed line represents the derived
d
by using expression (17). The experimental results are shown with the blue line with square symbol.
Fig. 11
indicates that the experimental measured
d
is consistent with expression (17). Compared with the ideal result, discrepancy is noted, which is mainly caused by the parasitic resistance of IBC.
Comparison of the theoretical and experimental results of d versus D.
 B. Output Voltage Ripple
The output voltage ripple is determined by the current flowing through the output capacitor
i_{C}
, which is the combination of the current
i_{B}
and the load current
i_{o}
.
Fig. 5
illustrates the typical current waveform of
i_{C}
with DCMII, which is negative during interval
ΔT
, and positive during other intervals.
Fig. 5
shows that the capacitor current meets the following expression:
Thus,
The output voltage ripple is derived as
For DCMII, the output voltage ripples can be derived and expressed as
Similarly, the output voltage ripples with DCMI can be derived as
Fig. 12
shows the comparison of calculated input current ripple with simulated and experimental measured results when “
V_{1}
= 320 V,
V_{2}
= 520 V, and
C_{o}
= 600 μF.”
Fig. 12
indicates that the expressions derived for the input current ripple are correct regardless of the operating mode. The output power boundary for DCMI and DCMII is
P_{o}
= 55 kW. The inductance in this design is set at 50 μH because the DCM modes are used for the lowpower region. The simulation and experimental results indicate that the output voltage ripple ratio is wellregulated within 1%. If only CCMs are used, then the inductance should reach 300 μH. Thus, the hybrid mode shows significant advantages in both keeping low output voltage ripples and improving power density.
Output voltage ripples versus output power.
 C. Input Current Ripple
Based on the input current expressions presented in
TABLE II
, the input current ripple with CCMI is expressed as
The input current ripple with DCMI is expressed as
The average input current with DCMI is obtained by
Thus,
Fig. 13
shows the comparison of the calculated input current ripple with simulated and experimental measured results when “
V_{1}
= 320 V and
V_{2}
= 520 V.”
Fig. 13
indicates that the expressions derived for the input current ripple are valid for all operating modes. The input ripple ratio for the rated power 150 kW is also wellregulated within 20%.
Input current ripple. (a) Absolute input current versus output power. (b) Input current ripple versus output power.
 D. Output Power
With DCM, the average output power of IBC can be expressed as
For the voltage closeloop operation, the voltage conversion ratio
d
is constant. The load resistance
R
is decreased with an increasing
D
to obtain an increased output power. With openloop operation, for a given
V_{1}
and
R
,
V_{o}
and
P_{o}
will increase with
D
based on (17) and (30).
Fig. 14
shows the relationship of the output power with dutycycle
D
for both the openloop and voltage closedloop operations. Their base values are the output power values under the condition of “
D
= 0.05.”
Fig. 14
indicates that the output power will be increased with
D
for both the openloop and closedloop operations. However, with the closedloop control, the changing speed of the output power is faster than that with the openloop control.
Comparison of the output power versus D for the openloop and closedloop controls.
 E. SOA Design
Figs. 4
and
5
show the dynamics of the current. Thus, the inductor peak current
i_{Lpeak}
in a switching period can be determined. For CCM, DCMI, and DCMIII,
i_{Lpeak}
corresponds to
i_{L}
(
δ_{1}
); for the other modes,
i_{Lpeak}
corresponds to
i_{L}
(
δ_{2}
). The inductor rms current in a switching period
I_{rms}
can be expressed as:
Fig. 15
shows the inductor peak current
i_{Lpeak}
and inductor rms current
i_{Lrms}
of IBC as a function of
L_{s}
. IGBTs are used as the main power device; thus, the switching frequency is set at 10 kHz.
Fig. 15
shows that both
i_{Lpeak}
and
i_{Lrms}
are decreased with the inductance. The inductance determines the output power range.
Fig. 15
shows the maximum output power with “
L_{s}
= 100 μH” is 36 kW, while the maximum output power is 68 kW when “
L_{s}
= 50μH.” The comparison results shown in
Fig. 7
indicate that the inductance will be significantly reduced by using DCM instead of CCM for the same output power. The reduction of inductance is beneficial for the size reduction and power density improvement. In this design, a hybrid mode is adopted, which considers the entire power range. DCM is used for the lowpower region and CCM is adopted for the highpower region. The boundary for DCM and CCM is set at close to “
P_{o}
= 70 kW.”
SOA design of IBC with DCM. (a) Relationship of the inductor peak current i_{Lpeak} with L_{s}; (b) Relationship of the inductor rms current i_{Lrms} with L_{s}.
 F. Efficiency
Fig 16
(a) is the system efficiency curve, which indicates that the entire efficiency is approximately between 95% and 98%; the efficiency is over 97% when the output power is larger than half of the rated power.
Fig. 16
(b) shows the estimated power loss distribution of the prototype with
P_{o}
= 20 kW using the proposed hybrid mode for IBC. DCM is used for the lowpower region and CCM is used for the highpower region. The main power losses include the IGBT conduction loss
P_{cond_IGBT}
, IGBT switching losses
P_{sw_IGBT}
, diode conduction loss
P_{cond_Diode}
, IGBT switching losses
P_{sw_diode}
, losses of inductor
P_{mag_L}
, and other losses, including the parasitic resistor losses. By using DCM, both the turnon switching loss of IGBTs and the reverse recovery loss of the diodes can be eliminated. Thus, the efficiency of IBC for the lowpower region can be improved from 90% to close to 92%.
System efficiency curve and power loss breakdown distribution. (a) System efficiency curve; (b) power loss distribution.
V. CONCLUSION
This study presents the operation, design, and performance characteristics of a multimode twophase IBC for FCEV applications. Different modes, including two CCMs and four DCMs, are discussed with their equivalent circuits. Four criteria to determine the mode distribution are also discussed. The mode distributions for various
d
are illustrated and verified with the experimental results. The effects of the inductor parasitic resistance in the voltage conversion ratio and mode boundaries are analyzed. The safe operational area is analyzed through a comparison of the different operation modes. The output voltage and power characteristics with the openloop or closedloop operations are discussed. A hybrid mode is adopted in this design. DCM is used for the lowpower region and CCM is adopted for the highpower region. The input inductance is reduced from 300 uH to 50 uH. The input ripple ratio for the rated power 150 kW is wellregulated within 20% and the output voltage ripple ratio is wellregulated within 1%. The system efficiency curve indicates that the entire efficiency is approximately between 95% and 98%; the rated efficiency is over 97%.
Acknowledgements
This study was supported by both the State Key Laboratory of Electrical Insulation and Power Equipment (EIPE15203) and the Jiangsu Province University Natural Science and Research Program (13KJB470013).
BIO
Huiqing Wen obtained a BS and MS in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2002 and 2006, respectively. In 2009, he obtained a PhD in Electrical Engineering from the Chinese Academy of Science, Beijing, China. From 2009 to 2010, he was an electrical engineer working with the GE (China) Research and Development Center Company, Ltd., Shanghai, China. From 2010 to 2011, he was an engineer at the China Coal Research Institute, Beijing, China. From 2011 to 2012, he was a postdoctoral fellow at the Masdar Institute of Science and Technology, Abu Dhabi, United Arab Emirates. He is currently a lecturer at the Xi’an JiaotongLiverpool University, Suzhou, China. His research interests include bidirectional DCDC converter, power electronics in flexible AC transmission (FACTS) applications, electrical vehicles (EVs), and highpower threelevel electrical driving system.
Bin Su was born in Wenzhou, China in 1981. He obtained a PhD in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2010. He has authored or coauthored nine published technical papers. His research interests include topologies, modeling, and control in power electronics.
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