The hybrid cascaded multilevel inverter (HCMLI) is a popular converter topology that is being increasingly used in high power medium voltage drives. The intricacy of the control technique for a HCMLI increases with the number of levels and due to fluctuating dc voltages. This paper presents a novel offline quadrant search based space vector modulation technique to synthesize a sinusoidal output from a dispersed pattern of voltage vectors due to different voltages in the auxiliary unit. Such an investigation has never been reported in the literature and it is being attempted for the first time. The method suggested distributes the voltage vectors for a reduced total harmonic distortion at minimal computation. In addition, the proposed algorithm determines the maximum modulation index in the linear modulation range in order to synthesize a sinusoidal output for both normal and abnormal vector patterns. It is better suited for a wide range of practical applications. It is particularly well suited for renewable source fed inverters which utilize large capacitor banks to maintain the dc link, which are prone to such slow fluctuations. The proposed quadrant search space vector modulation technique is simulated using MATLAB/SIMULINK and implemented using a Nexys2 Spartan3E FPGA for a developed prototype.
I. INTRODUCTION
Multilevel inverters (MLI) have emerged as a solution to construct medium and high power converters using low power semiconductor devices
[1]

[3]
with an increase in the quality of the output AC voltage
[4]
. This breed of inverters has a wide range of applications in energy conversion, transportation, mining, petrochemicals, etc. They are also employed as active power filters and static compensators in power systems. In recent years researchers have developed different MLI topologies. All of the topologies are either revisions or hybridizations of three basic topologies
[5]
viz. Diode Clamped (DC), Flying Capacitor (FC) and Cascaded H Bridge (CHB). Among these basic topologies, the FC and CHB are referred to as multi cell converters, since they are built using many smaller converters called power cells. Due to the increased redundancies and modularity of the CHB topology, it is more attractive since it can enable fault tolerant operation and increase the output levels by only adjusting the DC voltage ratios between the power cells. The major issue with the CHB MLI is that it requires large number of isolated DC sources
[6]

[8]
.
A three phase CHB MLI can be realized using various structures.
Type 1
, Cascading CHBs to construct a single phase MLI and connecting three such single phase inverters in the phase shifting mode
[9]
.
Type 2
, By having a six pulse inverter as a central inverter unit and cascading a single phase CHB as an auxiliary unit with each phase
[10]
.
Considering the number of realizable levels that can be achieved for a particular component count, the three phase inverters of type 2 seem to be superior since the output of six pulse inverter itself has five levels. Since number of required switches and DC voltage sources is lower for the six pulse inverter, it can be used as a high voltage cell in an asymmetric MLI to minimize the switching losses. The quality of the output voltage depends on the number of levels. Therefore, a larger number of levels in the output voltage can be achieved by setting the DC source voltage ratio to 3:1, which is called the maximal distension
[11]
,
[12]
. For all of the integer voltage ratios up to the maximal distension, the voltage vectors are distributed over a hexagonal pattern. If the voltage ratio is a noninteger or exceeds the maximal distension, the voltage vector pattern becomes patched
[13]
, and if the DC source voltages in the auxiliary units are unequal, the vector pattern becomes clustered.
There are studies on the control of MLIs for such unevenly distributed vector patterns obtained by setting different voltages between the main and auxiliary cells
[14]
. Based on the switching frequencies, low frequency approaches such as selective harmonic elimination
[15]

[21]
; nearest vector and nearest level methods; and high frequency methods such as Sinusoidal PWM (SPWM), sub harmonic PWM (SHPWM), space vector pulse width modulation (SVPWM), and carrier based PWM were developed for harmonic reduction. In SPWM and SHPWM control algorithms, the power cells in each phase have to be dealt individually. SVPWM is generally preferred since it deals with all of the three phases and power cells together. Several SVPWM control methods have been proposed for MLIs with equal DC voltage sources
[22]

[26]
. A dual SVM control strategy
[23]
has been proposed for asymmetric MLIs with a voltage ratio of the maximal distension for which the voltage vectors are uniformly distributed. For abnormally distributed voltage vectors due to noninteger voltage ratios and voltage ratios greater than the maximal distension the modulation can be achieved by using suitably selected noninteger ratios or by locating an equilateral triangle out of the unordered vectors
[22]

[24]
. In
[27]
,
[28]
, an offset voltage injection technique was studied to balance the output voltage of a multilevel cascaded inverter. However, the use of an integrator in the compensation method reduces the dynamic characteristics in drive applications. A multilevel multiphase feed forward space vector modulation technique was proposed to compensate the voltage imbalance in
[29]
.
This paper makes two significant contributions. Primarily, the proposed novel algorithm can be applied to multilevel inverters irrespective of or their topology or level. Secondly, the proposed algorithm has the ability to produce a sinusoidal output irrespective of the distention ratio. The main objective of the proposed control algorithm is to provide a generalized solution for multilevel inverters when powered by isolated DC sources such as capacitors, fuel cells, and solar panels, which are easily exposed to voltage variations depending on their system dynamics.
This paper presents a generalized quadrant search based SVPWM algorithm considering three phase cascaded MLIs of type 2 powered by isolated DC voltage sources for both auxiliary and central units which results in dispersed vector patterns. Section II describes the topology of the HCMLI considered for this work. It also describes the switching states and vector patterns. In Section III, the algorithm is discussed in detail. The performance of the algorithm is validated by simulation and experimental results which are discussed in Section IV. Section V concludes this paper.
II. POWER CIRCUIT CONFIGURATION AND ANALYSIS OF VOLTAGE VECTORS
Fig. 1
shows the topology of the 3φ hybrid cascaded multilevel inverter considered for this work. It comprises of a six pulse inverter as a central unit and a single phase H Bridge inverter as an auxiliary unit connected in series with each phase of the central inverter. The number of levels can be increased by connecting additional H bridges in series. The central inverter and auxiliary units are powered by isolated DC voltage sources of V
_{dc}
, R
_{a}
V
_{dc}
, R
_{b}
V
_{dc}
and R
_{c}
V
_{dc}
, respectively. R
_{a}
, R
_{b}
and R
_{c}
are the voltage ratios of the auxiliary unit to the central unit of the respective phases. A maximum of four and six levels are attained when both the central and auxiliary units are equally powered and at the maximum distension, as shown in
Fig. 2
(a) and
Fig. 2
(b).
Table I
shows a comparison of the commercially available four level inverter MLI topologies. From this table it is evident that due to the capacitorless power circuit, the voltage balancing problem can be completely avoided. The number of isolated DC voltage sources is high, which is considered to be a drawback of the considered topology.
Topology of 3ɸ Hybrid cascaded Multilevel Inverter (HCMLI).
(a) R_{a}=R_{b}=R_{c}= 1. (b) R_{a}=R_{b}=R_{c}= 0.3. (c) R_{a}=R_{b}=R_{c}=0.8. (d) R_{a}=R_{b}=R_{c}= 0.4. (e) R_{a}=0.8, R_{b}=0.5 and R_{c}=0.4. (f) R_{a}=0.3, R_{b}=0.7 and R_{c}=0.9.
COMPARISON OF THE COMMERCIALLY AVAILABLE FOUR LEVEL MULTILEVEL TOPOLOGIES
COMPARISON OF THE COMMERCIALLY AVAILABLE FOUR LEVEL MULTILEVEL TOPOLOGIES
The switching states of a branch in the central unit are SA0, SB0 and SC0 and in the auxiliary unit they are SA1, SB1, and SC1. The state of the central unit can be assigned as 0 or 1 depending on whether the switches (Sp) are connected to a negative or positive terminal of the DC source and the state of the auxiliary unit can be 1, 0 or 1 as described in
Table II
. Among the 2
^{K}
(where K is the number of switches) available switching states only 2b (where b is the number of branches) of the states are valid for satisfying the following conditions.

1. The sources must not be short circuited.

2. The load must not be left open.
SWITCHING STATES OF THE INVERTER UNITS
SWITCHING STATES OF THE INVERTER UNITS
The output voltage vectors of a star connected load in terms of the switching state is given by Equation (1):
Where:
R
_{a}
, R
_{b}
, and R
_{c}
are the ratios of the auxiliary unit to the central unit DC source voltage of the respective phases.
By calculating the phase voltages using equation (1), the space vectors corresponding to any state of a MLI can be obtained using equation (2). The voltage vector patterns obtained for the considered topology for different ratios are shown in
Fig. 2
(a)
2
(f).
Various space vector modulation schemes have been proposed for MLIs
[14]

[17]
. None of these methods have addressed the issue of different voltage sources (R
_{a}
≠ R
_{b}
≠ R
_{c}
) in the auxiliary cells.
Fig. 2
(e) and
Fig. 2
(f) portray the vector pattern for unequal voltage ratios (R
_{a}
≠ R
_{b}
≠ R
_{c}
) in the auxiliary units.
III. PROPOSED QUADRANT SEARCH SPACE VECTOR ALGORITHM
Fig. 3
shows a flowchart of the proposed algorithm. The major steps involved in this algorithm are as follows:

1. Determine the maximum output voltage that can be synthesized using the available voltage vectors.

2. Identification of the three nearest enclosing vectors using a quadrant search.

3. Calculation of the duty cycle for the identified vectors.
Flowchart of the proposed Algorithm.
 A. Determination of the Maximum Output Voltage
If the DC link voltages between the central unit and the auxiliary unit are equal, integers and less than or equal to the maximal distention then the vectors that can produce the maximum output voltage will form a hexagon, as shown in
Fig. 4
. The maximum synthesizable output voltage is given by Equation (3).
Maximum synthesizable output voltage.
In the case of noninteger voltage ratios between the auxiliary and the central units, the vector distribution is dispersed as shown in
Fig. 5
Maximum output voltage – Unbalanced Condition.
In which case, equation (3) is modified by a factor
X
:
Where
X
is a factor by which the length of the maximum synthesizable output voltage reduces, as shown in
Fig. 6
, in order to obtain a sinusoidal output.
Reduction in the maximum output voltage.
Hence, to obtain the maximum synthesizable voltage an algorithm is framed which is discussed below. The steps involved in this algorithm are shown in
Fig. 7
.
Flow chart to determine R_{max}.
The angles between 0˚ to 360˚ are divided into M equal sectors. The maximum voltage vector in each sector (m
_{i}
where i = 1, 2, 3…... M) is identified. Three specific values of M are selected (72, 18 and 6) to illustrate how a circle of the minimum radius fits into a maximum, moderate and minimum number of points. If the scan angle is selected randomly there may be the possibility of choosing a minimum R
_{max}
. For the balanced case, R
_{max}
is obtained at M=6 as shown in
Fig. 8
. For the unbalanced case the maximum R
_{max}
is obtained when M=18 as shown in
Fig. 9
. To avoid such scenarios, the R
_{max}
values of various scan angles ranging from 1˚ to 60˚ are found and the maximum among them is selected. The above discussion is illustrated for balanced (R
_{a}
=R
_{b}
=R
_{c}
=1) and unbalanced voltage ratios (R
_{a}
=0.8, R
_{b}
=0.5, R
_{c}
=0.4) in
Fig. 8
and
Fig. 9
, respectively.
Maximum voltage vectors for different values of M under balance condition.
Maximum voltage vectors for different values of M under Unbalance condition.
The minimum voltage point (V
_{pi}
) on the line joining
m_{i}
and
m
_{i+1}
, in adjacent sectors is determined. There are two cases for determining V
_{pi}
.
Let:
α = angle between the lines joining
m_{i}
, origin and
m_{i}
,
m
_{i+1}
β = angle between the lines joining
m
_{i+1}
, origin and
m
_{i+1}
,
m_{i}
Փ = angle between
m_{i}
and the real axis
θ = angle between
m
_{i+1}
and the real axis
V
_{i}
= vector length of
m_{i}
V
_{i+1}
= vector length of
m
_{i+1}
Case 1
: If the lines joining the origin (zero vector) and the points m
_{i}
and m
_{i+1}
subtend an acute angle, then the length of the perpendicular distance of the line joining the vectors m
_{i}
and m
_{i+1}
to the origin is the minimum point, as shown in
Fig. 10
a. The distance (V
_{i,i+1}
) between the two vectors
m_{i} and m
_{i+1}
can be calculated using equation (4).
If
the angles α and β are acute.
Vector diagram to identify minimum point.
V_{pi}
is given by equation (5).
Where
.
Case II:
If
, then the minimum voltage point V
_{pi}
= V
_{i}
, as shown in
Fig. 10
(c).
If V
_{i}
≤ V
_{i+1}
, then V
_{pi}
=V
_{i+1}
, as shown in
Fig. 10
(b).

a. The above procedure is carried out for all of the M sectors and the values of Vpiin each sector are determined. The minimum among the values of Vpiin all of the sectors is the radius (Rmmax) of the maximum inscribable circle. Rmmaxgives the maximum output voltage that can be synthesized for a particular value of M.

The above procedure is repeated for different values of M as shown inFig. 8(a)(c) andFig. 9(a)(c), and the values of Rmmaxthat correspond to each of the values of M are determined.

b. To synthesize the maximum output voltage, Rmax, which is maximum value among Rmmax, is selected.Fig. 11andFig. 12show a plot between the different values of M and the corresponding values of Rmmax.
Radius of Maximum Inscribable circle R_{max} = 346.4V.
Radius of Maximum Inscribable circle R_{max} = 220V.
 B. Quadrant Search for Vectors (V1, V2and V3)
The reference vector of a constant magnitude rotates at 2πf
_{r}
to achieve a three phase balanced output voltage with a frequency of f
_{r}
. At any instant, the reference voltage is synthesized using three switching vectors, V
_{1}
, V
_{2}
and V
_{3}
, so that the three vectors enclose the reference vector with a lesser area. It is also used to locate the reference vector point in a way that is similar to a human eye trying to enclose a point within three points.
The whole plane is shifted with the reference point (vector) as the origin, as shown in
Fig. 13
. Now the nearest vectors are obtained by using simple coordinate geometry. The two nearest values are identified as the first vector (V
_{1}
) and the second vector (V
_{2}
). Then it is possible to locate V
_{3}
, the quadrant in which V
_{1}
and V
_{2}
lie with reference to the shifted origin, the equation of which ensures reduced voltage distortion in the output voltage. The mechanism line joining the shifted reference and the two vectors V
_{1}
and V
_{2}
has to be determined as E1 and E2 and their corresponding slopes S1 and S2. Based on the data, the quadrant in which the third point V
_{3}
exist is determined, which results in
combinations (four Quadrants with two point combinations = 12 possibilities), as shown in the
Fig. 14
(a)(h).
Reference as shifted origin.
Graphical representation of CASE A. (a) Quadrant A combination. (b) Quadrant B Combination. (c) Location of V_{3} when V_{1} and V_{2} are in quadrant 1 and 2. (d) Location of V_{3} when V_{1} and V_{2} are in quadrant 1 and 3. (e) Location of V3 when V1 and V2 are in quadrant 1 and 4. (f) Location of V3 when V1 and V2 are in quadrant 2 and 3. (g) Location of V3 when V1 and V2 are in quadrant 2 and 4. (h) Location of V_{3} when V_{1} and V_{2} are in quadrant 3 and 4.
Case A:
The vectors V
_{1}
and V
_{2}
lie in the same quadrant as in
Fig. 14
(a), and the locations of V
_{1}
and V
_{2}
are interchanged as shown in
Fig. 14
(b). Possible Case A combinations are analyzed based on the line equations and their corresponding slopes when V1 and V2 lie in the same quadrant and are tabulated in
Table III
.
POSSIBLE POSITION OF VECTOR V3 FOR DIFFERENT LOCATIONS OF V1 AND V2
For all Quadrant A combinations if (S1) >(S2) and E1<= 0 and E2>=0 then all vectors covered in the shaded region can be V3 For all Quadrant B combinations if (S1) <(S2) and E1>= 0 and E2<=0 then all vectors covered in the shaded region can be V3 1 = higher value, 0 = lesser value
Case B:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 1 and 2 and vice versa are shown in
Fig. 14
(c).
Case C:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 1 and 3 and vice versa are shown in
Fig. 14
(d).
Case D:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 1 and 4 and vice versa are shown in
Fig. 14
(e).
Case E:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 2 and 3 and vice versa are shown in
Fig. 14
(f).
Case F:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 2 and 4 and vice versa are shown in
Fig. 14
(g).
Case G:
A graphical representation of vectors V
_{1}
and V
_{2}
in Quadrant 3 and 4 and vice versa are shown in
Fig. 14
(h).
All of the possible quadrant combinations
case (B–G)
are analyzed based on the line equation and their corresponding slopes and are tabulated in
Table IV
.
POSSIBLE POSITION OF VECTOR V3FOR DIFFERENT LOCATIONS OF V1AND V2
POSSIBLE POSITION OF VECTOR V_{3} FOR DIFFERENT LOCATIONS OF V_{1} AND V_{2}
In
Fig. 14
(a)(h), the shaded regions indicate the quadrant in which the third vectors V
_{3}
are located. Having found the quadrant, the nearest of the selected V
_{3}
vectors is determined. The data obtained in
Table III
and
Table IV
are based on a geometric analysis of the distributed voltage vectors.
 C. Calculation of the Duty Cycle for the Switching Vectors
The ON time of the switches depends on the duty cycles of the three switching vectors. From
Fig. 15
, by vector addition to synthesize the reference voltage (
V_{r}
), equation (6) must be satisfied. By solving equations (7), (8) and (9), D
_{1}
, D
_{2}
and D
_{3}
can be determined.
This implies that:
Where Di is the duty cycle and Xi, Yi are the coordinates of Vi with reference to Vr (where i = 1, 2, 3) and since V1, V2 and V3 encloses Vr.
Reference vector Synthesis.
Equations (6) and (7) suggest a way to use PWM to generate a three phase voltage of which the average value follows a given three phase reference by switching among the vectors V
_{1}
, V
_{2}
and V
_{3}
with the duty cycles of D
_{1}
, D
_{2}
and D
_{3}
, respectively.
The modulation index (m
_{a}
) is given by:
The range of m
_{a}
is 0≤
m_{a}
≤0.866
IV. SIMULATION AND EXPERIMENTAL RESULTS
The performance of the proposed modulation technique has been validated by both simulation and experimental verification. A conventional test was conducted, as shown in
Fig. 16
, for the 3φ squirrel cage induction motor to estimate its equivalent circuit parameters. The estimated motor parameters are shown in
Table V
. The same parameters are used for simulation in Matlab/Simulink. A Nexys2 Spartan3E FPGA was used to implement the algorithm.
Conventional test to estimate the motor parameters.
MOTOR SPECIFICATIONS
A 3ɸ hybrid cascaded multilevel inverter was built using four smart power IGBTs with built in gate driver (FSBB20CH60B) modules. The rating of any power device depends on the commutation voltage, which is defined by the DC voltage of the unit in which the device is connected. Since the maximum commutation voltage among all of the switches under all of the considered cases was found to be 200V in the simulation. Hence, power IGBTs (18) of 600V, 20A were selected. The modules were fixed with a suitable heat sink and snubber circuit for protection. A diode rectifier rated at 600V, 35A was provided at the converter input for AC voltage to DC bus voltage conversion. All of the PWM signals are isolated using an IC 6N137. Sensors are provided for current measurement. An Agilent Infinii vision oscilloscope was used to capture the waveforms.
The simulation and experimental verifications were done at no load, as shown in
Fig. 17
and
Fig. 18
, for the four different cases listed in
Table VI
.
Simulation of the Algorithm by MATLAB/Simulink.
Experimental setup for verification of the Algorithm.
SIMULATION PARAMETERS
Case IBalanced Condition (R_{a} = R_{b} = R_{c} = 1)
Simulation and experimental verifications were carried out by setting V
_{dc}
=200V, R
_{a}
V
_{dc}
=R
_{b}
V
_{dc}
=R
_{c}
V
_{dc}
=200V and operating the machine at no load. R
_{max}
for this case was found to be 346.6V. At a modulation index of m
_{a}
= 0.66, V
_{L(peak)}
= 578V, V
_{L (rms)}
= 408V. In addition, I
_{L (peak)}
= 0.714A, I
_{L (rms)}
= 0.505A and speed of the motor was 1473 rpm. As shown in
Fig. 19
and
Fig. 20
similar results were obtained in both the simulation and the experiment. The THD of the load current was found to be 0.82%.
Simulation results obtained for balanced voltage ratios (R_{a}=R_{b}=R_{c}=1) with motor load. (a) Load current. (b) Speed of the motor. (c) Line voltages. (d) and (e) Enlarged view of current at (00.1sec) and (0.9 1 sec). (f) THD of load current (0.82%).
Line voltage and Load current for (R_{a}=R_{b}=R_{c}= 1) at no load & ma = 0.66.
Case IIAbove the Maximum distention (R_{a} = R_{b} = R_{c} = 0.8)
Voltages of V
_{DC}
= 200V, R
_{A}
V
_{DC}
=R
_{b}
V
_{DC}
=R
_{C}
V
_{DC}
=160V were applied for both the simulation and experimental setups and the machine was operated at no load. The Rmax for this case was found to be 300.5V. At a modulation index of ma = 0.77, VL (peak) = 266.9V, VL (rms) = 188.7V. In addition, IL (peak) = 0.72A, IL (rms) = 0.51A and speed of the motor was 1473 rpm. From
Fig. 21
and
Fig. 22
it is evident that similar results were obtained from both the simulation and the experiment. The THD of the load current was 1.60%.
Simulation results for voltage ratios (R_{a}=R_{b}=R_{c}=0.8) with motor load. a) Load current, b) Speed of the motor, c) line voltages d and e) Enlarged view of current at (00.1sec) and (1.9 2 sec) (f) THD of load current (1.60%).
Line voltage and Load current for (R_{a}=R_{b}=R_{c}=0.8) at no load & ma = 0.77.
Case III Unbalance ratios Ra = 0.3, Rb = 0.7 and Rc = 0.9
Assuming that a voltage fluctuation has occurred, an unbalance in the voltage among the auxiliary units was created by adjusting the isolated DC voltage sources to Vdc = 200V, RaVdc = 60V, RbVdc = 140V and RcVdc = 180V. The radius of the maximum inscribable circle Rmax for this case was found to be 230.6V. For ma = 0.5, VL (peak) = 254V, VL (rms) = 179.6. In addition, IL (peak) = 0.58A, IL (rms) = 0.41A and speed of the motor was 1400 rpm. From
Fig. 23
and
Fig. 24
it can be seen that due to DC voltage fluctuations the line voltage is distorted but the load current remains sinusoidal verifying the capability of the proposed algorithm. The THD of the load current was found to be 0.62% as shown in
Fig. 23
(f).
Simulation results for voltage ratios (R_{a}=0.3, R_{b}=0.7 and R_{c}=0.9) with motor load. (a) Load current. (b) Speed of the motor. (c) line voltages. (d) and (e) Enlarged view of current at (00.1sec) and (1.8 – 1.9 sec). (f) THD of load current (0.62%).
Line voltage and Load current for (R_{a}=0.3, R_{b}=0.7 and R_{c}=0.9) at no load & ma = 0.5.
Case III Unbalance ratios Ra = 0.8, Rb = 0.5 and Rc = 0.4
To demonstrate that a voltage fluctuation has occurred, an unbalance in voltage among the auxiliary units was created by setting the isolated DC voltage sources to different voltages, Vdc = 200V, RaVdc = 160V, RbVdc = 100V and RcVdc = 80V. The radius of the maximum inscribable circle Rmax for this case was found to be 220.V. For ma = 0.5, VL (peak) = 298V, VL (rms) = 210V. In addition, IL (peak) = 0.51A, IL (rms) = 0.36A and speed of the motor was 1400 rpm. From
Fig. 25
and
Fig. 26
it can be seen that the line voltage is distorted due to DC voltage fluctuations but the load current is still sinusoidal verifying the capability of the proposed algorithm. The THD of the load current was found to be 0.49% as shown in
Fig. 26
(f).
Line voltage and Load current for (R_{a}=0.8, R_{b}=0.5 and R_{c}=0.4) at no load & ma = 0.5.
Simulation results for voltage ratios (Ra=0.8, Rb=0.5 and Rc=0.4) with motor load. (a) Load current. (b) Speed of the motor. (c) line voltages. (d) and (e) Enlarged view of current at (00.1sec) and (1.9 2 sec),(f) THD of load current (0.49%).
V. CONCLUSION
An offline quadrant search space vector algorithm has been investigated for a 3ɸ Hybrid cascaded MLI. The MLI has two stages which are a central six pulse inverter cascaded with a 1ɸ H Bridge inverter as an auxiliary unit in each phase. The process of space vector modulation is for the identification of the three nearest vectors. The proposed algorithm can be extended to any three phase multilevel inverters irrespective of topology, number of levels and distention ratios. The difference between topologies is only the switching states corresponding to the vectors. The results show that the proposed technique generates an output with an improved quality when compared to other techniques proposed in the literature. In addition, this technique is also suitable for any voltage ratio which produces evenly, islanded and clustered voltage vectors. The voltage level in each step of the output voltage is not the same as in the case of clustered voltage vectors. An experimental investigation was carried out to validate the proposed algorithm and it yielded significant results.
BIO
Johnson Anitha Roseline received her Bachelor degree in 2002 from the University of Madras, Chennai, India, in 2002. She received and Master degree in 2006 from Anna University. She is presently working as an Assistant Professor in the Department of Electrical and Electronics Engineering at the SSN College of Engineering, Chennai, India. She has 12 years of academic experience. Her current research interests include power electronics and control.
Subramanian Vijayenthiran received his Bachelor degrees in Electrical and Electronics Engineering from Anna University, Chennai, India, in 2013. He is presently working as Research Assistant in the Department of Electrical and Electronics Engineering at the SSN College of Engineering, Chennai, India. His current research interest include robotics and power electronics.
Rajini V received her B.E. and M.E. degrees from Annamalai University, Chidambaram, India, and her Ph.D. degree from Anna University, Chennai, India. She is presently a Professor at the SSN College of Engineering, Chennai, India. She has 22 years of academic experience. Her current research interests include power electronics and high voltage engineering.
Senthil Kumaran Mahadevan received his Bachelor and Master degrees in Electrical and Electronics Engineering from the University of Madras, Chennai, India, in 1999 and 2001, respectively, and his Ph.D. degree from Anna University, Chennai, India, in 2013. He is presently working as an Assistant Professor in the Department of Electrical and Electronics Engineering at the SSN College of Engineering, Chennai, India. His current research interests include electric drives, control and signal processing,
Lai J. S.
,
Peng F. Z.
1996
“Multilevel converters – A new breed of power converters”
IEEE Trans. Ind. Appl.
32
(3)
509 
517
DOI : 10.1109/28.502161
Rodriguez J.
,
Franquelo L. G.
,
Kouro S.
,
Leon J. I.
,
Portillo R. C.
,
Prats M. A. M.
,
Perez M. A.
2009
“Multilevel converters: An enabling technology for highpower applications”
Proc. IEEE
97
(11)
1786 
1817
DOI : 10.1109/JPROC.2009.2030235
Maharjan L.
,
Inoue S.
,
Akagi H.
2008
“A transformerless energy storage system based on a cascade multilevel PWM converter with star configuration”
IEEE Trans. Ind. Appl.
44
(5)
1621 
1630
DOI : 10.1109/TIA.2008.2002180
Franquelo L. G.
,
Rodriguez J.
,
Leon J. I.
,
Kouro
,
Portillo S.R.
,
Prats M. A. M.
2008
“The age of multilevel converters arrives”
IEEE Ind. Electron. Mag.
2
(2)
28 
39
DOI : 10.1109/MIE.2008.923519
Rodriguez J.
,
Lai J.S.
,
Peng F. Z.
2002
“Multilevel inverters: a survey of topologies, controls, and applications”
IEEE Trans. Ind. Electron.
49
(4)
724 
738
DOI : 10.1109/TIE.2002.801052
Teodorescu R.
,
Blaabjerg F.
,
Pedersen J. K.
,
Cengelci E.
,
Enjeti P. N.
2002
“Multilevel inverter by cascading industrial VSI”
IEEE Trans. Ind. Electron.
49
(4)
832 
838
DOI : 10.1109/TIE.2002.801069
Bose B. K.
2009
“Power electronics and motor drives recent progress and perspective”
IEEE Trans. Ind. Electron.
56
(2)
581 
588
DOI : 10.1109/TIE.2008.2002726
Lai Y. S.
,
Shyu F. S.
2002
“Topology for hybrid multilevel inverter”
Proc. Inst. Elect. Eng.—Elect. Power Appl.
149
(6)
449 
458
DOI : 10.1049/ipepa:20020480
Rabinovici R.
,
Baimel D.
,
Tomasik J.
,
Zuckerberger A.
2010
“Series space vector modulation for multilevel cascaded Hbridge inverters”
IET Power Electron.
3
(6)
843 
857
DOI : 10.1049/ietpel.2009.0220
Liu H.
,
Tolbert L. M.
,
Khomfoi S.
,
Ozpineci B.
,
Du Z.
“Hybrid cascaded multilevel inverter with PWM control method”
Proc. IEEE 39th Power Electron. Spec. Conf.
2008
162 
166
Corzine K. A.
,
Sudhoff S. D.
,
Whitcomb C. A.
1999
“Performance characteristics of a cascaded twolevel converter”
IEEE Trans. Energy Convers
14
(5)
433 
439
DOI : 10.1109/60.790893
Kou X.
,
Corzine K. A.
,
Wielebski M. W.
2003
“Overdistention operation of cascaded multilevel inverters”
Proc. IEEE Int. Elect. Mach. Drives Conf.
1535 
1542
Lu S.
,
Mariethoz S.
,
Corzine K. A.
2010
“Asymmetrical cascade multilevel converters with non integer or dynamically changing DC voltage ratios: Concepts and modulation techniques”
IEEE Trans. Ind. Electron.
57
(7)
2411 
2418
DOI : 10.1109/TIE.2010.2041734
Du Z.
,
Tolbert L. M.
,
Chiasson J. N.
2006
“Active harmonic elimination for multilevel converters”
IEEE Transactions on Power Electronics
21
(2)
459 
469
DOI : 10.1109/TPEL.2005.869757
Aghdam M. G. H.
,
Fathi S. H.
,
Gharehpetian G. B.
“Elimination of harmonics in a multilevel inverter with unequal DC sources using the homotopy algorithm”
IEEE International Symposium on Industrial Electronics
2007
578 
583
Tang T.
,
Han J.
,
Tan X.
“Selective harmonic elimination for a cascade multilevel inverter”
IEEE International Symposium on Industrial Electronics
2006
977 
981
Wells J. R.
,
Nee B. M.
,
Chapman P. L.
2005
“Selective harmonic control: A general problem formulation and selected solutions”
IEEE Trans. Power Electron.
20
(6)
1337 
1345
DOI : 10.1109/TPEL.2005.857541
Dahidah M. S. A.
,
Agelidis V. G.
2008
“Selective harmonic elimination PWM control for cascaded multilevel voltage source converters: A generalized formula”
IEEE Trans. Power Electron.
23
(4)
1620 
1630
DOI : 10.1109/TPEL.2008.925179
Kang D. W.
,
Kim H. C.
,
Kim T. J.
,
Hyun D. S.
2005
“A simple method for acquiring the conducting angle in a multilevel cascaded inverter using step pulse waves”
IEE Proceedings on Electric Power Applications
152
103 
111
DOI : 10.1049/ipepa:20040984
Liu Y.
,
Hong H.
,
Huang A. Q.
2009
“Realtime calculation of switching angles minimizing THD for multilevel inverters with step modulation”
IEEE Trans. Ind. Electron.
56
(2)
285 
293
DOI : 10.1109/TIE.2008.918461
Ishida T.
,
Miyamoto T.
,
Oota T.
,
Matsuse K.
,
Sasagawa K.
,
Huang L.
“A control strategy for a fivelevel double converter with adjustable DC link voltage”
Industry Applications Conference
2002
530 
536
Mondal S. K.
,
Pinto J. O. P.
,
Bose B. K.
2002
“A neuralnetworkbased space vector pwm controller for a threelevel voltagefed inverter induction motor drive”
IEEE Trans. Power Electron.
38
(3)
660 
669
Celanovic N.
,
Boroyevich D.
2001
“A fast space vector modulation algorithm for multilevel three phase converters”
IEEE Trans. Ind. Appl.
37
(2)
637 
641
DOI : 10.1109/28.913731
Wei S.
,
Wu B.
,
Li F.
,
Liu C.
2003
“A general space vector pwm control algorithm for multilevel inverters,”
Applied Power Electronics Conference and Exposition, Eighteenth Annual IEEE
1
562 
568
Mekhilef S.
,
Kadir M. N. A.
2011
“Novel vector control method for threestage hybrid cascaded multilevel inverter”
IEEE Trans. Ind. Electron.
58
(4)
1339 
1349
DOI : 10.1109/TIE.2010.2049716
Vazquez S.
,
Leon J. I.
,
Franquelo L. G.
,
Padilla J. J.
,
Carrasco J. M.
2009
“DC voltage ratio control strategy for multilevel cascaded converters fed with a single dc source”
IEEE Trans. Ind. Electron.
56
(7)
2513 
2521
DOI : 10.1109/TIE.2009.2017549
Cho Y.
,
Labella T.
,
Lai J.S.
,
Senesky M. K.
2014
“A carrierbased neutral Voltage Modulation strategy for multilevel cascaded inverters under unbalanced DC sources”
IEEE Trans. Ind. Electron.
61
(2)
625 
636
DOI : 10.1109/TIE.2013.2254091
Park Y. M.
,
Ryu H. S.
,
Lee H. W.
,
Jung M. G.
,
Lee S. H.
2010
“ Design of a cascaded hbridge multilevel inverter based on power electronics building blocks and control for high performance”
Journal of Power Electronics
10
(3)
262 
269
DOI : 10.6113/JPE.2010.10.3.262
Carnielutti F.
,
Pinheiro H.
,
Rech C.
2012
“Generalized Carrierbased modulation strategy for cascaded multilevel converters operating under fault conditions”
IEEE Trans. Ind. Electron.
59
(2)
679 
689
DOI : 10.1109/TIE.2011.2157289