This paper presents a new hybrid soft switching dcdc converter with a low circulating current and high circuit efficiency. The proposed hybrid converter includes two subconverters sharing two power switches. One is a threelevel PWM converter and the other is a
LLC
converter. The
LLC
converter and the threelevel converter share the laggingleg switches and extend the zerovoltage switching (ZVS) range of the laggingleg switches from nearly zero to full load since the
LLC
converter can be operated at
f_{sw}
(switching frequency) ≈
f_{r}
(series resonant frequency). A passive snubber is used on the secondary side of the threelevel converter to decrease the circulating current on the primary side, especially at high input voltage and full load conditions. Thus, the conduction losses due to the circulating current are reduced. The output sides of the two converters are connected in series. Energy can be transferred from the input voltage to the output load within the whole switching period. Finally, the effectiveness of the proposed converter is verified by experiments with a 1.44
k
W prototype circuit.
I. INTRODUCTION
Fullbridge converters with a high power density and high efficiency have been proposed and used in many industry products such as server power units
[1]
, telecommunication power units
[2]
, and electric vehicle (EV) and plugin hybrid electric vehicle (PHEV) battery chargers
[3]
,
[4]
. Singlephase power factor correction (PFC) is normally adopted in the front stage to eliminate the current harmonics, increase the input power factor and keep the dc bus voltage at a constant voltage against line voltage and load current variations. For medium/high power ratings, power converters with a threephase ac utility are adopted to reduce the current rating from the ac source. The power factors of these converters are normally required to improve the power quality of utility systems. Threephase PFC with a unidirectional or bidirectional power flow and bridge/bridgeless circuit topologies can be adopted in the front stage. However, the dc bus voltage of the threephase PFC will be higher than 750V or 800V. Thus, the power switches in the dcdc converters of the rear stage must have 900V or 1200V voltage stress. Threelevel dcdc converters
[5]

[7]
with low voltage stress of the active switches are widely used in industry applications due to their high switching frequency and small size demands. Phaseshift pulsewidth modulation (PWM) is normally adopted to generate the gate voltages of threelevel converters. The main drawback of phaseshift PWM is that the laggingleg switches have a narrow range of ZVS operation due to the limited energy stored in the primary leakage inductance. To overcome this problem, a large leakage inductance
[8]
or an external resonant inductance
[3]
can be placed on the primary side to extend the ZVS range of the laggingleg switches. However, this approach also increases the duty cycle loss and decreases the effective duty cycle on the secondary side. In
[9]
,
[10]
, auxiliary circuits are added on the primary side to increase the ZVS load range. The switching power losses of the switches are improved. However, the power losses of the additional auxiliary circuits will decrease the total circuit efficiency. Recently, an
LLC
converter and a fullbridge converter sharing laggingleg switches have been studied in
[11]
,
[12]
. Thus, the ZVS range of the switches can be extended from zero to full load conditions. The other main problem of the phaseshift PWM scheme for fullbridge converters and threelevel converters is its high circulating current during the freewheeling interval. To overcome this drawback, active or passive clamp circuits
[4]
and
[13]
can be added on the secondary side to limit voltage overshoots and oscillations across the output diodes when they are turned off, and to improve the circulating current losses on the primary side. However, an additional gate driver is needed to control the secondary active switch which will increase the circuit complexity and decrease the circuit reliability.
A hybrid threelevel ZVS converter is studied in this paper to have the advantages of wide range of ZVS operation and low circulating current losses. The proposed hybrid converter combines a conventional threelevel PWM converter and a halfbridge
LLC
converter with fixed switching frequency sharing of the laggingleg switches to reduce the switch counts. Since the switching frequency of the
LLC
converter is greater than the series resonant frequency, the active switches at the laggingleg can be turned on under ZVS from zero to full load conditions. The output voltages of the halfbridge
LLC
converter and the threelevel PWM converter are connected in series. Thus, energy can be transferred from the input to the output load within the whole switching cycle. A passive snubber is adopted on the secondary side to provide a positive rectified voltage during the freewheeling interval to decrease the primary side current. Thus, the high circulating current in the conventional threelevel PWM converter is rapidly reduced and the converter efficiency is improved. In the meantime, the rectified voltage on the secondary side during the freewheeling interval is positive instead of zero in the conventional threelevel converter. The output inductance in the proposed hybrid converter can also be reduced. Finally, experiments with a 1.44
k
W prototype circuit are provided to demonstrate the performance of the proposed converter.
II. PROPOSED CONVERTER
Fig. 1
shows a general threephase acdc converter for industry power units. The frontstage is a threephase power factor corrector to achieve a low total harmonic distortion of the threephase line currents, a high power factor and a stable high dc bus voltage. The second stage is a high frequency link dcdc converter based on a fullbridge converter with IGBT power switches or a threelevel PWM converter with power MOSFETs to provide a stable low dc bus voltage and high load current. In order to reduce the converter size and weight, a threelevel PWM converter with power MOSFETs and a high switching frequency is generally used to achieve this demand.
Fig. 2
shows a circuit diagram of the proposed high frequency dcdc converter to overcome the disadvantages of conventional threelevel PWM converters. There are two subconverters in the proposed dcdc converter. One is a threelevel PWM converter (
C
_{d1}
,
C
_{d2}
,
D
_{1}
,
D
_{2}
,
C_{f}
,
S
_{1}

S
_{4}
,
T
_{1}
,
L
_{r1}
,
D
_{r1}
,
D
_{r2}
,
C_{c}
,
D_{a}
,
D_{b}
,
L_{o}
and
C
_{o1}
) and the other is an
LLC
circuit (
C_{f}
,
S
_{2}
,
S
_{3}
,
L
_{r2}
,
C_{r}
,
T
_{2}
,
D
_{r3}
,
D
_{r4}
and
C
_{o2}
).
S
_{1}
and
S
_{4}
are in the leadingleg, and
S
_{2}
and
S
_{3}
are in the laggingleg. The
LLC
circuit is operated at a fixed switching frequency so that the output voltage
V
_{o2}
is unregulated. However, the total output voltage
V_{o}
is regulated by the threelevel PWM circuit using the phaseshift PWM scheme. The energy stored in the output inductor
L_{o}
is reflected to the primary side to help the leadingleg switches turnon at ZVS from light load to full load conditions. The
LLC
circuit, sharing the laggingleg switches
S
_{2}
and
S
_{3}
of the threelevel PWM circuit, is operated at a fixed switching frequency. The adopted switching frequency
f_{sw}
is close to the series resonant frequency
f_{r}
in the
LLC
circuit. The laggingleg switches
S
_{2}
and
S
_{3}
can be turned on at ZVS from nearly zero to full load conditions. Thus, power switches
S
_{1}

S
_{4}
in the proposed circuit have a wide range of ZVS operation when compared to the ZVS range in the conventional threelevel converter. In order to reduce the circulating current of the threelevel converter, a passive snubber circuit including
C_{c}
,
D_{a}
and
D_{b}
is used on the secondary side to provide a dc voltage during the freewheeling interval. During the freewheeling interval, the rectified voltage
v_{r}
=
v_{Cc}
. The reflected voltage
n
_{1}
v_{r}
is applied to
L
_{r1}
on the primary side to reduce the circulating current to zero, and the output inductor voltage
v_{Lo}
=
v_{Cc}

v
_{o1}
instead of 
v
_{o1}
. Thus, the high circulating current losses in the conventional threelevel converter are improved in the proposed converter. Since the output voltages of the threelevel circuit and the
LLC
circuit are connected in series, the input energy of the
LLC
circuit can be delivered to the output load in the whole switching cycle.
Threephase acdc converter with twostage conversion.
Circuit diagram of the proposed hybrid ZVS converter.
III. OPERATION PRINCIPLES
In the proposed converter, the turnon time of each power switch is equal to half of a switching period. The PWM signal of
S
_{2}
(
S
_{3}
) is phaseshifted with respect to the PWM signal of
S
_{1}
(
S
_{4}
).
S
_{1}
(
S
_{2}
) and
S
_{4}
(
S
_{3}
) operate complementarily with a short dead time to avoid short circuits. The operation principles of the proposed converter are based on the following assumptions. 1) MOSFETs
S
_{1}

S
_{4}
and rectifier diodes
D
_{r1}

D
_{r4}
,
D
_{1}

D
_{2}
and
D_{a}

D_{b}
are ideal, 2) capacitor voltages
v
_{Cd1}
,
v
_{Cd2}
,
v_{Cf}
,
V
_{o1}
and
V
_{o2}
are constant, the turns ratios of
T
_{1}
and
T
_{2}
are
n
_{1}
=
n
_{p1}
/
n
_{s1}
and
n
_{2}
=
n
_{p2}
/
n
_{s2}
, respectively, and 3)
C
_{1}
=
C
_{2}
=
C
_{3}
=
C
_{4}
=
C_{oss}
and
V
_{Cd1}
=
V
_{Cd2}
=
V_{Cf}
=
V_{in}
/2.
Fig. 3
illustrates the key PWM waveforms of the proposed converter in a switching cycle. According to the switching states of
S
_{1}

S
_{4}
,
D
_{r1}

D
_{r4}
,
D
_{1}

D
_{2}
and
D_{a}

D_{b}
, the converter has seven operation modes in each half of a switching period.
Fig. 4
gives the equivalent circuits for the seven operation modes.
Key waveforms of the proposed converter during one half of switching cycle.
Operation modes of the proposed converter in a half switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7.
Mode 1 [t_{0}  t_{1}]:
Prior to
t
_{0}
, the power semiconductors
S
_{1}
,
S
_{2}
,
D
_{r1}
and
D
_{r3}
are conducting. Both of the inductor currents
i_{Lr1}
and
i_{Lr2}
are positive.
S
_{1}
is turned off at
t
_{0}
.
C
_{1}
and
C
_{4}
are charged and discharged, respectively, by
i_{Lr1}
. The energy stored in the output inductor
L_{o}
and the primary inductor
L
_{r1}
is used to discharge
C
_{4}
to zero voltage. The ZVS condition of
S
_{4}
is illustrated in (1).
This mode ends at
t
_{1}
when
v
_{C1}
=
V_{in}
/2 and
v
_{C4}
=0. The time interval of mode 1 is given in (2).
The dead time between
S
_{1}
and
S
_{4}
must be greater than Δ
t
_{01}
to achieve the ZVS operation of
S
_{4}
.
Mode 2 [t_{1}  t_{2}]:
Mode 2 starts at
t
_{1}
when
v
_{C1}
=
V_{in}
/2,
v
_{C4}
=0, and
D
_{1}
and
D_{a}
are on. Since
i
_{Lr1}
is positive, the output diode of
S
_{4}
is conducting. At this moment,
S
_{4}
can be turned on under ZVS. In this mode, the primary side voltages
v_{ab}
=0 and
v_{ac}
=
v_{Cf}
=
V_{in}
/2 in the steady state. Since
D_{a}
is on, the rectified voltage
v_{r}
=
v_{Cc}
and
v_{Lo}
=
v_{Cc}

V
_{o1}
<0. The inductor current
i_{Lo}
decreases with a slope of (
v_{Cc}

V
_{o1}
)/
L_{o}
. The reflected secondary windings voltage 
n
_{1}
v_{Cc}
is applied to
L
_{r1}
so that the primary side current
i_{Lr1}
rapidly decreases to zero with a slope of 
n
_{1}
v_{Cc}
/
L
_{r1}
. The time interval in mode 2 is obtained in (3).
In the conventional threelevel converter, the primary current
i
_{Lr1}
in this mode is kept at the same value of
i
_{Lr1}
(
t
_{1}
) because
v
_{Lr1}
=0. Thus, the conventional threelevel converter has large circulating current losses during the freewheeling interval. The energy stored in the clamped capacitor
C_{c}
is transferred to the output load through
L_{o}
and
D_{a}
. The secondary winding current
i_{a}
decreases in this mode. The
LLC
converter is still in the resonant mode to transfer energy from the input to the output load.
Mode 3 [t_{2}  t_{3}]:
Mode 3 starts at
t
_{2}
when the secondary winding current
i_{a}
decreases to zero, and the capacitor current
i_{Cc}
=
i_{Lo}
. The primary side current
i
_{Lr1}
is approximately zero and the primary and secondary sides of
T
_{1}
are disconnected. There is no circulating current loss in this mode. The output inductor voltage
v_{Lo}
=
v_{Cc}

V
_{o1}
<0 and
i_{Lo}
decreases. The
LLC
circuit continuously transfers energy from
C_{f}
to the output load.
Mode 4 [t_{3}  t_{4}]:
Mode 4 starts at
t
_{3}
when
S
_{2}
is turned off.
i
_{Lr2}
charges
C
_{2}
to
V_{in}
/2 and discharges
C
_{3}
to zero. The
LLC
converter is operated at
f_{sw}
(switching frequency) ≈
f_{r}
(series resonant frequency). Thus, the inductor current
i
_{Lr2}
is lagging with respect to the input fundamental voltage
v_{ac,f}
.
Mode 5 [t_{4}  t_{5}]:
Mode 5 starts at
t
_{4}
when the capacitor
C
_{3}
is discharged to zero. Since
i
_{Lr1}
(
t
_{4}
)+
i
_{Lr2}
(
t
_{4}
)>0, the antiparallel diode of
S
_{3}
is conducting.
S
_{3}
can be turned on under ZVS due to the help of the
LLC
converter. In this mode,
D_{a}
,
D
_{r2}
and
D
_{r4}
are on,
v_{ab}
=
V_{in}
/2,
v_{ac}
=0, and
v_{r}
=
v_{Cc}
. The output inductor voltage
v_{Lo}
=
v_{Cc}

V
_{o1}
<0 and
i_{Lo}
decreases. The primary inductor voltage
v
_{Lr1}
=
n
_{1}
v_{Cc}

V_{in}
/2<0 so that
i
_{Lr1}
decreases with a slope of (
n
_{1}
v_{Cc}

V_{in}
/2)/
L
_{r1}
until
i_{a}
=
i_{Lo}
. In the
LLC
converter,
C_{r}
and
L
_{r2}
are resonant with the input voltage
v_{ac}
=0, and
i
_{Lr2}
decreases in this mode. During this time interval,
i_{a}
increases from zero to
i_{Lo}
, and
i_{Cc}
increases from 
i_{Lo}
to zero. The time interval in this mode is given as:
In this mode, the threelevel converter and the
LLC
converter transfer energy from the input to the output load. The ac terminal voltage
v_{ab}
=
V_{in}
/2 and diode
D_{a}
conducts to obtain the rectified voltages
v_{r}
=
v_{Cc}
. The duty loss in mode 5 is given as:
Mode 6 [t_{5}  t_{6}]:
Mode 6 starts at
t_{5}
when
i_{a}
=
i_{Lo}
and
i_{Cc}
=0. Diode
D_{a}
is off. The reflected primary inductance
L
_{r1}
/(
n_{1}
)
^{2}
and
C_{c}
are resonant with the resonant frequency
. Thus, the diode
D_{b}
is conducting in this mode. The output inductor current
i_{Lo}
increases with a slope of
v_{Cc}
/
L_{o}
. The half of a resonant period, 1/(2
f_{R}
), is designed to be less than the minimum effective duty cycle time (
δ_{eff,min}T_{sw}
/2). Then, the capacitor current
i_{Cc}
will be decreased to zero before
S
_{4}
is turned off. The rectified voltage
v_{r}
=
v_{Cc}
+
V
_{o1}
, and the primary inductor current
i
_{Lr1}
=(
i_{Lo}
+
i_{Cc}
)/
n
_{1}
. In this mode, energy is transferred from the input voltage to the output load through both the threelevel converter and the
LLC
circuit.
Mode 7 [t_{6}  t_{7}]:
Mode 7 starts at
t
_{6}
when
i_{Cc}
=0, and diode
D_{b}
is off. The rectified voltage
v_{r}
≈
V_{in}
/(2
n
_{1}
)>
v_{Cc}
, and
D_{a}
is reverse biased. The output inductor voltage
v_{Lo}
=
V_{in}
/(2
n
_{1}
)
V
_{o1}
>0, and
i_{Lo}
increases in this mode. This mode ends at
t
_{7}
when
S
_{4}
is turned off. Then, the circuit operations of the proposed converter in the first half of a switching period are completed.
IV. CONVERTER PERFORMANCE ANALYSIS
There are two circuits, a threelevel PWM circuit and an
LLC
circuit, in the proposed converter. The threelevel converter transfers energy from the input voltage
V_{in}
to the output
V
_{o1}
in modes 57 during the first half of the switching cycle. The
LLC
converter transfers energy from the capacitor
C_{f}
to the output
V
_{o2}
within a full switching period. Since the
LLC
converter is operated as an unregulated dcdc converter with a switching frequency
f_{sw}
that is close to the series resonant frequency
f_{r}
, the laggingleg switches
S
_{2}
and
S
_{3}
are easily turned on at ZVS from zero to full load, and the circulating current of the
LLC
converter is at its minimum due to
f_{sw}
≈
f_{r}
. Based on the fundamental frequency analysis of the
LLC
converter, the ac voltage gain of the
LLC
converter at the switching frequency is equal to unity. Thus, the designed dc voltage gain of the
LLC
circuit is equal to the ac voltage gain of the
LLC
circuit at the series resonant frequency, i.e.
M_{dc,LLC}
=4
n
_{2}
V
_{o2}
/
V_{in}
=1. The unregulated output voltage
V
_{o2}
of the
LLC
converter is obtained as:
The ZVS condition of the leadingleg switches
S
_{1}
and
S
_{4}
is achieved by the primary inductance
L
_{r1}
and output inductance
L_{o}
given in (1). The other ZVS condition of
S
_{1}
and
S
_{4}
is that the dead time between
S
_{1}
and
S
_{4}
must be greater than Δ
t
_{01}
given in (2). The charge and discharge times of
S
_{1}

S
_{4}
are much less than the time intervals in the other modes, and only modes 2, 3, 5, 6 and 7 are considered in the following analysis. In mode 6, the average capacitor voltage
V_{Cc}
=
V_{in}
/(2
n
_{1}
)
V
_{o1}
. The flux balance condition on the output inductance
L_{o}
is given as:
where
δ
_{6}
is the duty cycle in mode 6. Substitute
V_{Cc}
=
V_{in}
/(2
n
_{1}
)
V
_{o1}
into (7). Then, the output voltage
V
_{o1}
of the threelevel converter is obtained as:
where the effective duty cycle
δ_{eff}
=
δ

δ
_{5}
, and
δ
is the duty ratio of the proposed converter when (
S
_{1}
and
S
_{2}
) or (
S
_{3}
and
S
_{4}
) are in the onstate. The output voltages of the threelevel converter and the
LLC
converter are connected in series so that the output voltage
V_{o}
of the proposed converter is expressed as:
The dc voltage conversion ratio of the proposed converter is obtained as:
The ripple current of the output inductor
L_{o}
is approximated as:
From (11), the output inductance L
_{o}
is obtained in (12).
The ripple currents, the maximum currents and the minimum currents of the magnetizing inductances
L
_{m1}
and
L
_{m2}
are obtained as:
The average diode currents of
D
_{1}

D
_{4}
D_{b}
are shown in (16) and (17).
The voltage stresses of
D
_{1}

D
_{4}
,
D_{a}
and
D_{b}
are given as:
V. EXPERIMENTAL RESULTS
First, the design procedure of the proposed converter is shown in this section to derive the main circuit components in a laboratory prototype. The electric specifications of the prototype circuit are
V_{in}
=750V800V,
V_{o}
=48V and
I_{o,rated}
=30A. The switching frequency
f_{sw}
=100kHz. The output voltage of the
LLC
converter is assumed as 20V. The selected series resonant frequency of the
LLC
converter is equal to the switching frequency
f_{sw}
. The DC gain of the
LLC
converter at
f_{r}
is equal to unity. Based on (6), the turns ratio of
T
_{2}
is obtained in (21).
The primary inductance, primary winding turns and secondary winding turns of
T
_{2}
are 480
μ
H, 30 turns and 3 turns, respectively. In the
LLC
converter, the series resonant inductance
L
_{r2}
=80
μ
H and the series resonant capacitance
C_{r}
=32nF. The series resonant frequency of the
LLC
converter is close to 100
k
Hz. The maximum effective duty cycle
δ_{eff}
is assumed to be 0.4. From (9), the turns ratio of
T
_{1}
is derived in (22).
The magnetizing inductance, primary winding turns and secondary winding turns of
T
_{1}
are 1.3mH, 64 turns and 6 turns, respectively. The assumed duty cycle loss in mode 5 is 0.01. The necessary primary inductance
L
_{r1}
can be obtained from (5) and is given in (23).
The selected primary inductance
L
_{r1}
is 10μH in the prototype circuit. From (12), the output inductance
L_{o}
is obtained in (24) with Δ
i_{Lo}
/
I_{o,rated}
=0.2.
In the prototype circuit, the adopted output inductance
L_{o}
is 5μH. Power MOSFETs (IRFP460) with
V_{DS}
=500V and
I_{D,rms}
=20A are used for the switches
S
_{1}

S
_{4}
. Fast recovery diodes (VF30200C) with
V_{RRM}
=200V and
I_{F}
=30A are used as the rectifier diodes
D
_{1}

D
_{6}
,
D_{a}
and
D_{b}
. The selected clamped diodes
D
_{1}
and
D
_{2}
are MUR860. The selected input split capacitances are
C
_{d1}
=
C
_{d2}
=360
μ
F/450V, the flying capacitance
C_{f}
=1
μ
F and the output capacitances are
C
_{o1}
=
C
_{o2}
=2200
μ
F.
Experimental results based on a laboratory prototype with the above circuit parameters are presented to verify the circuit performance.
Fig. 5
gives the measured PWM signals of
S
_{1}

S
_{4}
and the ac side voltages
v_{ab}
and
v_{ac}
at 25% and 100% loads. It can be seen that there are three voltage levels on
v_{ab}
and two voltage levels on
v_{ac}
. The measured voltage and current of
S
_{1}
(leadingleg switch) at 15% and 100% loads are illustrated in
Fig. 6
.
Fig. 7
gives the measured voltage and current of
S
_{2}
(laggingleg switch) at 15% and 100% loads. From
Figs. 6
and
7
,
S
_{1}
and
S
_{2}
are all turned on at ZVS at a 15% load. (
S
_{1}
,
S
_{4}
) and (
S
_{2}
,
S
_{3}
) are in the leadingleg and laggingleg, respectively. Thus,
S
_{1}

S
_{4}
are all turned on at ZVS from 15% to full load conditions.
Fig. 8
shows the test results of the ac side voltages
v_{ab}
and
v_{ac}
, the resonant capacitor voltage
v_{Cr}
, and the primary currents
i
_{Lr1}
and
i
_{Lr2}
at 25% and 100% loads. There is no circulating current on
i
_{Lr1}
in the freewheeling interval (
v_{ab}
=0), and the primary current
i
_{Lr2}
is a quasisinusoidal current. From the measured primary inductor current
i
_{Lr1}
in
Fig. 8
(b), it is clear than there are seven operation modes in the first half switching cycle and these measured waveforms verify the operation mode discussions in section III.
Fig. 9
illustrates the experimental results of the diode currents
i
_{D1}

i
_{D4}
, clamped capacitor current
i_{Cc}
, output inductor current
i_{Lo}
, threelevel converter output current
i_{TL,o}
=
i_{Lo}
+
i_{Db}
,
LLC
converter output current
i_{LLC,o}
and load current
I_{o}
at full load. The measured circuit efficiencies of the proposed converter are 94.5%, 95.3% and 93.2% at a 25% load, a 50% load and a 100% load, respectively. The measured maximum efficiency is 95.9% at an 80% load.
Measured PWM signals of S_{1}S_{4} and ac side voltages v_{ab} and v_{ac} at (a) 25% load. (b) 100% load.
Measured voltage and current of S_{1} (leadingleg switch) at (a) 15% load (b) 100% load.
Measured voltage and current of S_{2} (laggingleg switch) at (a) 15% load (b) 100% load.
Measured waveforms of ac side voltages v_{ab} and v_{ac}, resonant capacitor voltage v_{Cr}, and the primary currents i_{Lr1} and i_{Lr2} at (a) 25% load (b) 100% load.
Measured waveforms of diode currents i_{D1}i_{D4}, clamped capacitor current i_{Cc}, output inductor current i_{Lo}, threelevel converter output current i_{TL,o}, LLC converter output current i_{LLC,o} and load current I_{o} at full load.
VI. CONCLUSION
A hybrid ZVS converter is presented in this paper to reduce the circulating current loss in the freewheeling interval and to extend the ZVS range of the laggingleg switches. The proposed hybrid converter includes a conventional threelevel converter and a
LLC
converter with shared laggingleg switches. The switching frequency of the
LLC
converter is close to the series resonant frequency to reduce the circulating current at the primary side and to help the laggingleg switches turn on at ZVS from light load to full load conditions. A passive snubber is used on the secondary side of the threelevel converter to reduce the circulating current during the freewheeling interval due to the fact that a reflected rectifier voltage is applied to the leakage inductance. The outputs of the two converters are connected in series to transfer energy from the input to the output load within the whole switching cycle. When compared to the conventional threelevel PWM converter, the proposed hybrid converter has less circulating current losses and a wider range of ZVS operation. Finally, the effectiveness and performance of the proposed converter are verified by experimental results with a 1.44
k
W prototype circuit.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022 MY3.
BIO
BorRen Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. His current research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards, in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, the 2007 Taiwan Power Electronics Conference, the 2009 IEEE–Power Electronics and Drive Systems Conference, the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEEInternational Conference on Industrial Technology.
JiaSheng Chen is presently working toward his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC). His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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