This paper presents a high frequency design approach for improving efficiency over a wide load range in the selfdriven phaseshifted fullbridge converters for server power systems. In the proposed approach, a detailed ZVS analysis of the lagging leg switches in both the continuous conduction mode (CCM) and the discontinuous conduction mode (DCM) is presented. The optimum dead time and the determination of the appropriate operation mode are given for high efficiency according to the load conditions. Finally, the optimum operation conditions are defined to achieve a highefficiency. A laboratory prototype operating at 80 kHz, rated 1 kW (12 V83.3 A), is built to verify proposed theoretical analysis and evaluations. The experimental results show that the maximum efficiency is achieved as 95% and 83.5% at full load and 5% load conditions, respectively.
I. INTRODUCTION
Recently, research efforts on the power converters used in server power systems have focused on achieving a high efficiency over a wide load range due to the worldwide depletion of energy sources and global warming. In addition, in server power systems, increasing energy consumption due to higher energy demand and rising energy costs require a highefficiency power conversion. Furthermore, the server power systems utilized in information technology usually use parallel structures that share the total load in the case of a failure. This structure also increases the reliability of the system. Therefore, highefficiency power conversion over a wide load range is becoming an important key parameter in converter design in order to save energy and reduce the size of cooling elements
[1]

[6]
.
The phaseshifted fullbridge (PSFB) converter is widely used for server power systems and data center applications due to its high conversion efficiency, high power density, simple control structure and low electromagnetic interference (EMI)
[2]

[16]
. In general, the PSFB converter is used as the second stage dcdc conversion of twostage server power systems with a low output voltage and a high output current. In these systems, the conduction loss of the rectifiers is dominated into the total conversion losses under heavy load conditions. Thus, only designs where the secondary side conduction losses are taken into consideration can achieve a high conversion efficiency
[4]
.
However, under the light load conditions, the switching and core losses constitute the main part of the total losses
[5]

[7]
. Since the zero voltage switching (ZVS) turnon of the primary switches depends on the load conditions, the lagging leg switches are turned on with hard switching under light load conditions. In order to improve the light load efficiency, various methods have been proposed in the literature
[6]

[11]
. However, these methods require additional circuit components and complex control circuit designs to achieve extended ZVS turnon for the lagging leg switches. Operation in the DCM under light load conditions is another simple option to maintain the ZVS turnon of the lagging leg switches. Besides, DCM operation reduces the core loss by extending the dead time
[5]
,
[12]
. In
[5]
, an active control method for the synchronous rectifiers at the secondary side was developed and it was found to improve the efficiency under light load conditions. However, the selfdriven method was not discussed.
The use of a synchronous rectifier (SR) is a wellknown option to reduce the high conduction losses especially in the low output voltage applications. In
[4]
, a design optimization achieving 99% efficiency at 25 kHz operation frequency was reported. In that study, parallel connected SRs help to reduce high conduction loss at the secondary side. However, the active gate driver design for the parallel connected SRs increases complexity of the system because large PCB surface is needed for SRs drivers and their isolated power supply. The selfdriving method seems to be more attractive when compared to the active gate drive method thanks to its simplicity and easy implementation, especially for cases where SRs are connected in parallel. Various selfdriving techniques using current driven or voltage driven techniques for the low output voltage and high output current applications have been proposed. The current driven methods require output current sensing with a current transformer and extra circuit components to convert the sensing current into an appropriate gate drive voltage
[2]
,
[14]
,
[18]
,
[19]
. In these studies, cost and the complexity of the driver circuit is high due to the additional circuit components. The voltage driven method uses the power transformer directly or the auxiliary winding is used to generate driving signals which in turn results in a cheap and simple solution
[17]
,
[20]
. In
[20]
, a method using the auxiliary winding to drive the SRs was proposed. That technique provides conduction of both SRs when the primary voltage is zero during the dead time. On the other hand, the conventional selfdriver method uses the secondary voltage of the power transformer directly.
In this study, a selfdriven synchronous rectified PSFB converter design approach is presented in order to obtain a high efficiency over a wide load range for server power systems. A detailed ZVS analysis of the lagging leg switches in the CCM and the DCM is presented to determine the appropriate operation mode and the optimum dead time according to the load conditions. To reduce the high conduction loss, the SRs are used for the center taped rectifier on the secondary side. A selfdriven circuit is considered to avoid the need for an additional active control circuit on the secondary side. The selfdriver method proposed in
[20]
is applied to generate control signals for the SRs. Finally, a prototype operating at 80 kHz with 1 kW (12 V83.3 A) of output power has been built to validate the theoretical performance analysis and evaluations.
The rest of this paper is organized as follows: Section II gives a ZVS analysis of the lagging leg switches in the CCM and the DCM. Section III evaluates the dead time optimization and the appropriate mode selection. Section IV presents the experimental results. Section V provides the conclusion.
II. ZVS ANALYSIS OF THE LAGGING LEG SWITCHES IN CCM AND DCM
The general operation principle of a PSFB converter with a center tapped rectifier is well known and proposed in many papers in the literature
[3]
,
[4]
. Therefore, so the analysis given here is focused on the interval achieving ZVS turnon of the switches in the lagging leg.
A power stage circuit diagram of the synchronous rectified PSFB PWM DCDC converter is shown in
Fig. 1
. Here, S
_{1}
S
_{4}
are the primary side switches, and they include antiparallel diodes and parasitic capacitors. SR
_{1}
and SR
_{2}
represent the synchronous rectifier reducing conduction losses on the secondary side. L
_{M}
is the mutual inductance, L
_{s}
is the equivalent inductance which is the sum of the leakage inductance of the transformer and additional inductance connected in series to the primary side. N is the turns ratio of the high frequency power transformer, L
_{o}
and C
_{o}
are the output filter components, V
_{in}
is the input voltage source, and V
_{o}
is the output voltage.
The power stage circuit diagram of PSFB PWM DCDC converter.
In the analysis, semiconductor devices, inductors and capacitors are accepted as ideal. It is also assumed that output inductance is high enough and its current is constant for one switching cycle. The equivalent circuit diagrams and the related key waveforms in the CCM and the DCM are shown in
Fig. 2
and
Fig. 3
, respectively.
(a) The equivalent circuit diagram achieving ZVS turnon in the lagging leg. (b) The related key waveforms in CCM.
(a) The equivalent circuit diagram achieving ZVS turnon in the lagging leg. (b) The related key waveforms in DCM.
In the CCM, before S
_{2}
is turnedoff, S
_{1}
is turnedoff so that the output capacitor of S
_{1}
and S
_{4}
is charged and discharged, respectively.Then,converter startsworkingin the freewheeling mode. The primary side of the transformer is short circuited by the conduction of the antiparallel diode of S
_{4}
and the conduction of the S
_{2}
MOSFET. As shown in
Fig. 2
(a), after S
_{2}
is turned off, the primary current charges and discharges the output capacitor of S
_{2}
and S
_{3}
, respectively. The antiparallel diode of S
_{3}
conducts after the output capacitor of S
_{3}
discharges completely, and the ZVS turnon for S
_{3}
can be achieved. However, both SR
_{1}
and SR
_{2}
are turned on during this stage for the output current commutation. Thus, the secondary side of the transformer is short circuited and the load current cannot reflect to the primary side in this interval. Therefore, the primary current quickly decreases and the stored energy in L
_{s}
alone should be sufficient to completely charges/discharges the output capacitor of the lagging leg switches:
In the above equations,
I_{pcr}
is the critical primary current and
C_{lagg}
defines the equivalent output capacitance during resonance. Thus, the required critical current value,
I_{pcr}
, or the load condition to charge/discharge the output capacitors of the switches can be determined by:
In order to achieve the ZVS turnon, the dead time in the CCM,
δ
_{RCCM}
, should be one quarter of the resonance period as follows:
During the output current commutation, there is no power transfer from the input to the output due to the fact that both of the SRs conduct at the same time and the voltage of the secondary side of transformer is zero. This time is defined as the lost duty ratio time interval. Therefore, the voltage gain can be written as:
Where, ΔD is the lost duty ratio including
δ_{RCCM}
. The difference between the total duty ratio,
D
, and
ΔD
gives the effective duty ratio,
D_{eff}
.
Where
I_{p1}
is the minimum value of the primary current,
I_{p3}
is the primary current value after the capacitors of the lagging leg switches charge/discharge completely, and they can be defined as:
In the above equation,
I_{o}
is the output current and Δ
I_{o}
is the output current variation.
I_{p2}
is the operation point of the primary current when freewheeling interval is completed. At this operation point, to provide ZVS turnon of the lagging leg switches, primary current should be least equal to the critical primary current defined as:
In the DCM, the current flowing through the SRs flows discontinuously so that both of the SRs should be turned off to prevent the discharge of the output filter capacitor with the conduction of the SRs. Therefore, the magnetizing inductance of the transformer participates to the resonance between L
_{S}
and both the output capacitors of the lagging leg switches and the SRs. Since the SRs are off during the freewheeling interval and their output capacitors are reflected to the primary side in the DCM operation, as shown in
Fig. 3
(a), the output capacitor of the SRs also has to be charged/discharged while the output capacitor of the lagging leg switches charges/discharges to provide the ZVS turnon for the primary switches. In this operation, the interval for the output current commutation between the SRs does not occur and the secondary of the transformer is not shortcircuited when compared to the CCM operation principle. Therefore, the current stored in the magnetizing inductance is sufficient to charges/discharges the output capacitors when compared to the conventional CCM operation. However, the charge/discharge time of the capacitors is larger than the CCM operation due to the small current value in
L_{M}
. Therefore, an extended delay time can achieve the ZVS turnon of the lagging leg switches in the DCM operation
[5]
. The energy required to achieve the ZVS of the lagging leg switches can be written as:
Where
I_{LMcr}
represents the critical magnetizing current value to achieve the ZVS, and it can be defined as:
In the above equations,
L_{s}
is neglected because it is very small near
L_{M}
. The delay time to be extended should be least one quarter of the resonance period as defined by:
III. DEAD TIME OPTIMIZATION AND APPROPRIATE MODE DETERMINATION
Under heavy load conditions, ZVS turnon can be easily achieved. However, if the primary current reaches zero or change its direction before the dead time completes, a primary current with an inverse direction recharges the output capacitors as shown in
Fig. 4
(a). In a similar way, when the load gets smaller, the output capacitors cannot be charged/discharged completely before the primary current reaches zero as shown in the
Fig. 4
(b). Therefore, the lagging leg switches are turned on with hard switching under light load conditions and with no optimized dead time. This load dependence problem is a wellknown disadvantage of PSFB DCDC converters. Some conventional solutions are usually applied to solve this problem like increasing L
_{s}
and adding additional capacitors to the output capacitors. However, these solutions change the conduction and the switching losses in a different way. Consequently, a detailed dead time optimization taking into consideration the overall efficiency and a wide load range can help to cope with the load dependent ZVS turnon operation of the lagging leg switches at the design stage.
(a) ZVS turnon of S_{3} with the large dead time. (b) Under the light load condition.
 A. CCM Operation
In the conventional design procedure, the high efficiency is optimized according to a constant dead time giving a desired voltage gain to regulate the output voltage under heavy load conditions. In this approach, the ZVS turnon of the lagging leg switches can be achieved by a suitable
L_{s}
inductor determined for a desired soft switching load range. Therefore, the ZVS turnon of the lagging leg switches is very strongly dependent on the dead time and
L_{s}
inductance.
The required dead time is also determined by the switch characteristics. In this study, SiC MOSFETs and Cool MOSFETs are evaluated as switching components due to their capability in terms of high frequency operation when compared to IGBTs. In these switches, the dead time, t
_{deadlagg}
, between S
_{2}
and S
_{3}
can be defined by:
In the formula,
t_{doff}
defines the turnoff delay time, and
t_{rv}
is the rising time of the switch voltage. The dead time,
t_{deadlagg}
, should be larger than the ZVS time interval and it should end before the primary current reaches zero. Here, the ZVS time interval is very short and it can be neglected. Thus, the linear time interval can be defined as follows:
Table I
shows a calculated performance comparison of Cool MOSFETs and SiC MOSFETs based on the dead time requirements and the losses. Each switch is selected for 400 V of DC input voltage, 1 kW of output power, and an 80 kHz switching frequency. In the calculations, transformer turns ratio, N, is 25, and the snubber inductance, L
_{s}
, is 10 μH.
PERFORMANCE COMPARISON OF COOL MOSFET AND SICMOSFET IN PSFB CONVERTER
PERFORMANCE COMPARISON OF COOL MOSFET AND SICMOSFET IN PSFB CONVERTER
According to results summarized in
Table I
, the SiC MOSFET has a lower power loss although its voltage rate is higher than the Cool MOSFET. Therefore, SiC device seems to be more suitable and reliable for server power systems using PSFB converters.
Fig. 5
shows the calculated maximum dead time variation as a function of L
_{s}
, and the critical primary current required for the ZVS of the lagging leg switches. The maximum dead time increases while L
_{s}
increases, and the critical primary current I
_{pcr}
decreases. If the desired ZVS range of the lagging leg switches is determined until the 60% load condition, L
_{s}
should be selected as 10 μH. According to the calculated results, the dead time for the lagging leg switches can be selected as 160 ns to achieve ZVS turnon until the 60% load condition.
The maximum dead time variation as the function of L_{s} and the critical primary current.
The L
_{s}
inductance variation effects on the conduction and switching losses over a wide load range should be taken into account to obtain the best efficiency for all of the load conditions.
Fig. 6
shows the switching losses over a wide load range as a function of L
_{s}
. The switching losses increase slightly while L
_{s}
decreases due to reductions in the critical load conditions. Under the critical load condition, the MOSFETs are turned on with hard switching. However, SiC MOSFETs have a small output capacitance so the turnon switching loss is not as dominant when compared to that over a wide L
_{s}
range. However, increasing the switching loss under a 20% load condition seems to be more dominant than that under 60% and 100% load conditions.
The switching loss variation as the function of L_{s} and the load condition.
Fig. 7
shows the conduction loss variation as a function of L
_{s}
. The change in the conduction loss over a wide L
_{s}
range is very slight and almost constant. This is due to the fact that the change in the lost duty ratio is very small because of the small output capacitance of the SiC MOSFETs. The SiC MOSFET presents the advantages of a small lost duty ratio and a low switching loss.
The conduction loss variation as the function of L_{s} and the load condition.
 B. DCM Operation
In the DCM operation, the ZVS of the lagging leg can be achieved by an extension of the dead time for load conditions that are lighter than 1% as proposed in
[5]
. In this approach, the effective duty ratio should be reduced according to the voltage gain and the necessary dead time should be determined to charge/discharge the output capacitors of the lagging leg switches and SRs. The voltage conversion ratio can be found by the voltagesec balance on the output inductor as follows:
Solving (14) for D yields:
The stored energy increases while L
_{M}
and the output capacitors of the lagging leg switches and SRs decrease. Thus, the SiC MOSFETs, which have small output capacitors, can help to reduce the need for the large energy stored in L
_{M}
to achieve ZVS turnon when compared to the Cool MOSFETs. The required dead time for the DCM operation can be calculated by (11).
Fig. 8
shows the variation of the switching loss according to the load conditions in the CCM and CCM+DCM operations. The DCM operation maintains the ZVS operation under the 60% critical load condition and switching loss is lower when compared to the CCM operation condition. However, in the DCM operation, the SRs should be turned off to prevent the discharge of the output filter capacitor through the SRs. This results in high conduction losses due to the conduction of the body diodes. Therefore, with DCM operation under a 60% load condition, it is not possible to obtain a high efficiency.
The switching loss comparison of CCM and CCM+DCM operation over wide load range.
Because both of the SRs are in the off state, there is no output current commutation interval on the secondary side in the DCM. The absence of an output current commutation can compensate for the body diode’s conduction losses. However, it is still not enough when compared to the parallel connected SRs implemented in this study.
Fig. 9
shows the variation of the conduction losses in the CCM and CCM+DCM operations. The DCM operation is applied under the 5% load condition and the conduction loss suddenly increases when the body diodes starts to conduct. However, the reducing core loss and the switching loss are dominant in the overall loss, and the efficiency under the 5% load condition is higher than the CCM operation as shown in the
Fig. 10
.
Conduction loss comparison of CCM and CCM+DCM operation over wide load range.
Efficiency comparisons of CCM and CCM+DCM operation over wide load range.
According to the theoretical evaluation given above, the synchronous rectified PSFB DCDC converter can be designed to operate in the CCM up to the 5% load condition, and in the DCM under the %5 load condition to obtain the best efficiency over a wide load range.
IV. EXPERIMENTAL RESULTS
A server adapter with a 12 V output voltage and rated at 1 kW is built to validate the theoretical analysis given above. The components and operation conditions evaluated for the prototype are summarized in
Table II
. A 400 V DC input voltage is applied to the input of the selfdriven synchronous rectified PSFB converter. The selfdriven method proposed in
[20]
is used to drive five parallel connected SR at the secondary side.
THE COMPONENTS AND THE OPERATION CONDITIONS EVALUATED FOR THE SERVER ADAPTER PROTOTYPE
THE COMPONENTS AND THE OPERATION CONDITIONS EVALUATED FOR THE SERVER ADAPTER PROTOTYPE
The primary current and the voltage waveforms in the CCM and the DCM are given in
Fig. 11
(a) and
Fig. 11
(b), respectively. In these figures, it is observed that the experimental results are in good agreement with the theoretical analysis.
The primary current and the voltage waveforms in (a) CCM under the full load condition and (b) DCM under 1% load condition.
The ZVS turn on of the S
_{2}
switch in the lagging leg while operating in the CCM, is shown in
Fig. 12
. The dead time is fixed at 160 ns to achieve ZVS turnon under the full load condition. The switch is turned on while its body diode is conducting and the ZVS turn on is achieved.
ZVS turnon of S_{2} switch in CCM and under the full load condition.
In
Fig. 13
, the ZVS turn on of the S
_{2}
switch in the DCM operation is given. Since both of the SRs are off in the DCM, L
_{M}
attends the resonance between L
_{s}
and the output capacitors of the primary MOSFETs and the SRs. Thus, ZVS turn on can be achieved easily by the energy stored in L
_{M}
. In the DCM operation, the dead time of the lagging leg is extended to 2.4 μs. Thus, the output capacitor of the MOSFET is discharged completely and S
_{2}
is turned on while its body diode is conducting.
ZVS turnon of S_{2} switch in DCM and at 1% load condition.
A comparison of the measured and calculated efficiency for the selfdriven synchronous rectified PSFB converter operating in the CCM+DCM and the diode rectified conventional PSFB converter operating in the CCM is given in
Fig. 14
. In the conventional design, a Schottky diode with a 0.77 V voltage drop is used at the secondary side instead of the SRs. The proposed design approach shows better performance over a wide load range. The efficiency is 4% and 5% higher than the conventional design under 5% load and full load conditions, respectively.
The efficiency comparison for the proposed design approach and the conventional diode bridge design as analytically and experimentally.
V. CONCLUSION
A selfdriven synchronous rectified PSFB converter design approach is proposed to obtain a high efficiency over a wide load range. The CCM and DCM operations are analyzed based on the ZVS turn on of the lagging leg switches. The dead time optimization in each operation mode is discussed based on the high efficiency and load condition. In addition, to reduce the conduction loss, SRs are used for the center tapped rectifier and a selfdriver is applied to drive the SRs on the secondary side. Finally, the given theoretical analysis is verified by an experimental setup for 1 kW output power, 12 V output voltage and 400 V DC input voltage. The measured and calculated efficiency performance of the proposed design approach for the selfdriven synchronous rectified PSFB converter is better than that of the diode rectified conventional PSFB converter. The optimization of the dead time according to the load condition can help to improve the efficiency over a wide load range in low voltage and high power applications such as server power systems. Selfdriven SRs also reduce the total cost, volume and weight of the overall converter system.
BIO
Sevilay Cetin was born in Denizli, Turkey. She received her B.S. and M.S. degrees in Electrical and Electronics Engineering from Pamukkale University, Denizli, Turkey, in 2001 and 2005, respectively. She received her Ph.D. degree in Electrical Engineering, from Yildiz Technical University, Istanbul, Turkey, in 2011. She was a Post Doctoral Research Associate in the NY State Center for Future Energy Systems, Rensselaer Polytechnic Institute, Troy, New York, from 2013 to 2014. She is presently working as an Assistant Professor in the Technology Faculty, Pamukkale University, Denizli, Turkey. Her current research interests include both DCDC and ACDC converter topologies, soft switching techniques, and high efficiency and high power density energy conversion in various industrial areas.
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