A high stepup dcdc converter is proposed for photovoltaic power systems in this paper. The proposed converter consists of an input current doubler, a symmetrical switchedcapacitor doubler and an activeclamp circuit. The input current doubler minimizes the input current ripple. The symmetrical switchedcapacitor doubler is composed of two symmetrical quasiresonant switchedcapacitor circuits, which share the leakage inductance of the transformer as a resonant inductor. The rectifier diodes (switchedcapacitor circuit) are turned off at the zero current switching (ZCS) condition, so that the reverserecovery problem of the diodes is removed. In addition, the symmetrical structure results in an output voltage ripple reduction because the voltage ripples of the charge/pump capacitors cancel each other out. Meanwhile, the voltage stress of the rectifier diodes is clamped at half of the output voltage. In addition, the activeclamp circuit clamps the voltage surges of the switches and recycles the energy of the transformer leakage inductance. Furthermore, pulsewidth modulation plus phase angle shift (PPAS) is employed to control the output voltage. The operation principle of the converter is analyzed and experimental results obtained from a 400W prototype are presented to validate the performance of the proposed converter.
I. INTRODUCTION
Recently, photovoltaic (PV) power systems has become an attractive candidate due to the increases in energy demand and the concern over environmental pollution around the world. Various kinds of configurations are being developed in gridconnected systems. Generally, a system can be employed as a smallscale distributed generation (DG) system, where the most important design constraint of the PV DG system is to obtain a high voltage gain. For a typical PV module, the opencircuit voltage is about 21~28 V
[1]
,
[2]
. However, the public DC bus voltage is usually set to 200V or 400V
[3]
,
[4]
. Therefore, a high stepup dcdc converter with a high voltage conversion ratio, a low inputcurrent ripple, a low outputvoltage ripple and a high efficiency is required to realize the gridconnected function and to achieve a low total harmonic distortion (THD).
Until now, various currentfed stepup conversion topologies have been proposed in photovoltaic (PV) power systems
[6]

[10]
. These topologies have desirable advantages such as a high voltage conversion ratio, a low input current ripple, a high power capability and galvanic isolation between the input and output sides. However, they have a common serious problem caused by the leakage inductance of the transformer. It is well known that converters with a power transformer suffer high voltage surges across the switches in currentfed topologies such as the currentfed pushpull converter, currentfed fullbridge converter and currentfed half bridge converter. Thus, a snubber circuit is required to absorb the surge energy to protect the switching devices from a permanent breakdown. Moreover, in currentfed power conversion topologies, the snubber circuit has to accommodate the entire boost current until the transformer leakage inductor current is built up to the level of the boost inductor current. Hence, a welldesigned snubber circuit is essential for solving these problems. However this greatly increases the circuit design complexity and cost. Most importantly, because the rectifier diodes are turned off at hard switching, the exiting reverserecovery problem will shade the efficiency improvement
[11]

[14]
.
Many voltagefed converters have also been proposed with stepup dcdc topologies for high gain
[15]

[19]
. However, these voltagefed converters may not be optimal due to a large input current ripple, which is not beneficial for MPPT control. Reducing the input current ripple in a voltagefed converter requires an additional LC filter across the photovoltaic cell stack, which lowers the power efficiency. Additionally, a high frequency transformer with a high turns ratio is required, which increases the voltage stress on the primary elements, and imposes a heavy penalty on the efficiency. As with the currentfed topologies, the reverserecovery problem is not solved.
Based on those considerations, some resonant converters have been proposed
[20]

[22]
. However, some disadvantages prevent their popularity. Even the dual resonant circuit applications in
[20]
,
[21]
produce a double output voltage, and two windings are required for the transformer which results in design complexity and a bottleneck for power density. The authors of
[22]
provide an ingenious method to achieve a high stepup through a resonant circuit. Unfortunately, the primary inverter bridge fails to realize the soft switching and a transformer with a high turnsratio is required. Recently, a novel class of resonant converters including the serial resonant converter (SRC), parallel resonant converter (PRC) and series parallel resonant converter (SPRC, also known as an LCC resonant converter) has been developed
[23]

[25]
. By adjusting the frequency, these resonant circuits can realize ZCS for all of the rectifier diodes, and voltage/current spikes can be suppressed in the primary switches due to a sinusoidal current though the switches instead of a square current. In addition, these circuits enjoy a relative high efficiency. However, some drawbacks limit their wide application:

1) The drifting of component parameters such as the transformer parasitic parameters including the stray inductors in wires and the layout of components can lead to difficulties in resonant loop design.

2) For the SRC, the large frequency change to maintain the output regulation becomes a serious drawback especially in no load or light load conditions. For the PRC, the light load efficiency is very low.

3) The conversion ratio is confined. For the SRC, the maximum is 1. For the SPRC, the design complexity is increased when compared to SRC or PRC. As a result, high turn ratio transformers are required to attain a high gain, which shades their advantages.

4) At the same power factor, the amplitude of the sinusoid current is 3~4 times the square current. This introduces the main switches to a serious radio frequency interface (RFI) problem.
To solve above problems mentioned, a novel isolated converter with an input current doubler, a resonant switchedcapacitor circuit and an activeclamp circuit is proposed in this paper. The operation of the proposed converter is analyzed in section II, and the control scheme is described in section III. Then, the performance is discussed in section IV. Finally, some experimental results and waveforms are presented to verify the performance of the proposed converter in section V.
II. PROPOSED CONVERTER AND OPERATION PRINCIPLE
The proposed converter and its simplified circuit model are shown in
Fig. 1
. It is composed of a current doubler and a switchedcapacitor circuit. The current doubler circuit is plotted in the left dashed block of
Fig. 1
. Two outofphase pulses with an adjustable width are supplied to drive the main switches
S
_{2}
and
S
_{4}
. The auxiliary switches
S
_{1}
,
S
_{3}
are driven complementarily by the main switches
S
_{2}
,
S
_{4}
, respectively. The inductors
L
_{1}
,
L
_{2}
are connected to the main switches
S
_{2}
,
S
_{4}
, respectively. The activeclamp circuit is composed of the clamp capacitor
C_{c}
and the auxiliary switches
S
_{1}
,
S
_{3}
. The switchedcapacitor circuit is plotted in the right dashed block of
Fig. 1
, which is composed of the rectifier diodes
D
_{1}
,
D
_{2}
,
D
_{3}
,
D
_{4}
and the capacitors
C
_{1a}
,
C
_{1b}
,
C
_{2a}
,
C
_{2b}
. This circuit provides two complementary seriesresonant loops to achieve the ZCS turnoff for all the rectifier diodes. One loop is the transformer leakage inductance
L_{lk}
resonating with
C
_{1a}
, and the other loop is the transformer leakage inductance
L_{lk}
resonating with
C
_{1b}
.
Proposed converter and its equivalent circuit. (a) Proposed converter. (b) Simplified circuit model. (c) Voltagelevelextension topology with N SC blocks.
By adding a different number of the SC blocks, which functions as a rectifier, as shown in the dotted box in
Fig.1
(c), the voltagelevelextension topology can be obtained. For every block that is added to the converter, 4 times
ν_{s}
will be added to the output voltage, where 4 diodes and 4 capacitors are utilized. Assume that the various rectifiers output the same power and the same voltage. The voltage on the primarywinding of the transformer is
V_{p}
, the output voltage is
V_{o}
and
V_{o}
=4
V_{p}
, and output current is
I_{o}
. A performance comparison between the SC rectifier and conventional rectifiers (a full bridge rectifier and a full wave rectifier) is shown in
Table I
.
PERFORMANCE COMPARISON BETWEEN SC RECTIFIER AND CONVENTIONAL RECTIFIERS
PERFORMANCE COMPARISON BETWEEN SC RECTIFIER AND CONVENTIONAL RECTIFIERS
From
Table I
, it can be concluded that the proposed SC rectifier benefits in terms of the turn ration of the transformer when compared with conventional rectifiers. Meanwhile, lower voltage stress of the diodes, soft switching realization for the diodes and less output voltage ripple make the proposed SC rectifier a better candidate for rectification.
To analyze the steadstate operation of the proposed converter, several assumptions are made during one switching period
T_{s}
.

1) The magnetizing current is nearly zero because the magnetizing inductance is relatively large and bidirectionally excited. Therefore, the magnetizing inductance can be neglected and the transformerTis modeled as an ideal transformer with a leakage inductanceLlk.

2) The main switchesS2,S4and the auxiliary switchesS1,S3are operated by the dual asymmetrical pulsewidth modulation method with a short dead time. Assume that the duty cycle of the main switchesS2,S4isD. The switchesS1,S3work complementarily with the switchesS2,S4. The details are discussed in section III.

3) All of the switchesS1S4are considered to be ideal switches with body diodes Ds1Ds4 and parallel capacitancesCs1Cs4.

4) The ripple component of the clampcapacitor voltageνCcis negligible because the clamp capacitorCchas a relatively large value.

5) The capacitance of the resonant capacitorsC1a,C1bare identical (C1a=C1b=C1). The output capacitorsC2a,C2bhave the same value (C2a=C2b=C2). In addition, the capacitance of the output capacitors is larger than that of the resonant capacitors. Furthermore, the equivalent series resistance (ESR) of the capacitors is assumed to be zero.
The steadystate operation of the proposed converter during one switching period
T_{s}
can be divided into ten stages. The equivalent circuits and the key waveforms in each operation stage are described in
Fig. 2
and
Fig. 3
, respectively.
Operation stages of the proposed converter. (a) Stage 1. (b) Stage 2. (c) Stage 3. (d) Stage 4. (e) Stage 5. (f) Stage 6. (g) Stage 7. (h) Stage 8. (i) Stage 9. (j) Stage 10.
Key waveforms of the proposed converter.
Stage 1 [t_{0}, t_{1}]
: At
t
_{0}
,
S
_{4}
is turned on. Then, the inductor current
i
_{L1}
flows through S
_{4}
, and the inductor current
i
_{L2}
flows through
S
_{2}
. Since both of the main switches
S
_{2}
,
S
_{4}
are in the onstate, the primary voltage
ν_{p}
of the transformer is zero. In addition, both the primary current of the transformer
i_{p}
and the secondary current of the transformer is are zero. Then, the inductor currents
i
_{L1}
,
i
_{L2}
increase linearly as follows:
Where,
V_{in}
is the output voltage of a photovoltaic battery.
Stage 2 [t_{1}, t_{2}]
: At
t
_{1}
,
S
_{2}
is turned off.
i
_{L2}
begins to discharge
C
_{s1}
and charge
C
_{s2}
linearly. After
i
_{L2}
fully charges
C
_{s2}
to
V_{Cc}
, and
C
_{s1}
discharges to 0 V, it flows through the antiparallel diode of the switch
S
_{1}
. Therefore, the zero voltage across
S
_{1}
is maintained, and the switch
S
_{1}
can be turned on at ZVS in the next stage.
During this stage, the input power is transferred to the output side. Since the voltage across the primary winding of the transformer is
ν_{p}
=
V_{Cc}
, the secondary winding voltage is:
Where, the turns ratio N of the transformer is given by N2/N1. There are two resonant loops. One is the leakage inductor
L
_{lk}
,
C
_{1a}
,
D
_{1}
and the other one is
L
_{lk}
,
C
_{1b}
,
D
_{4}
,
C
_{2b}
. The resonant capacitors
C
_{1a}
is charged by
ν_{s}
. At the same time,
ν_{s}
and
C
_{1b}
in series charge
C
_{2b}
. Both
D
_{1}
,
D
_{4}
conduct. The state equations can be written as follows:
Here,
i_{s}
,
ν
_{C1a}
and
ν
_{C1b}
are obtained as follows:
Where,
I_{s,peak}
is the peak current of the secondary transformer. The angular frequency
ω_{r}
and the resonant impedance
Z_{r}
are given by:
i_{Cc}
can be easily obtained as:
Stage 3 [t_{2}, t_{3}]:
At
t
_{2}
,
S
_{1}
is turned on while its body diode conducts. Hence, the switch
S
_{1}
is turnedon at the ZVS condition.
i
_{L1}
increases continuously as in (1), and
i
_{L2}
decreases linearly as follows:
The two resonanceloops (
ν_{s}
,
L_{k}
,
D
_{1}
,
C
_{1a}
and
ν_{s}
,
L_{k}
,
C
_{1b}
,
D
_{4}
,
C
_{2b}
) continue to resonate. In addition,
i_{p}
,
i_{Cc}
,
i_{s}
,
ν
_{C1a}
,
ν
_{C1b}
satisfy (6) (7) (8) (10) (11).
Stage 4 [t_{3}, t_{4}]:
At
t
_{3}
, the currents
i
_{D1}
,
i
_{D4}
of the diodes D1, D4 become zero, and
i_{p}
decreases to zero. In addition,
i
_{L1}
still increases linearly and
i
_{L2}
still decreases linearly, as shown in
Fig. 3
. Furthermore, the antiparallel diode of the switch
S
_{1}
conducts again. Since the resonance of the two loops is terminated at
t
_{3}
, the diodes
D
_{1}
,
D
_{4}
are turned off at ZCS, whose reverserecovery problem has been removed.
Stage 5 [t_{4}, t_{5}]:
At
t
_{4}
, the antiparallel diode of
S
_{1}
begins to conduct. Hence, the switch
S
_{1}
is turned off at ZVS.
Stage 6 [t_{5}, t_{6}]:
At
t
_{5}
,
S
_{2}
is turned on. This stage is analogous to stage 1. Therefore, the analysis of this stage is omitted.
Stage 7 [t_{6}, t_{7}]:
At
t
_{6}
,
S
_{4}
is turned off. In addition,
i
_{L1}
begins to charge
C
_{s3}
and discharge
C
_{s4}
linearly. After
i
_{L1}
fully charges
C
_{s4}
to
V_{Cc}
and discharges
C
_{s3}
to 0 V, it flows through the antiparallel diode of the switch
S
_{3}
. Therefore, the zero voltage across the switch
S
_{3}
is maintained, and the switch
S
_{3}
can be turned on at ZVS in the next stage.
Like stage 2, during this stage, the input power is transferred to the output side. Since the voltage across the primary winding of the transformer is
ν_{p}
=
V_{Cc}
, the secondary winding voltage is:
There are two resonant loops. One loop is formed by
C
_{1a}
,
D
_{3}
,
C
_{2a}
,
L
_{lk}
.
C
_{1a}
and
ν_{s}
. It charges
C
_{2a}
in series. The other loop is formed by
C
_{1b}
,
D
_{2}
,
L
_{lk}
and
ν_{s}
.
C
_{1b}
is charged by
ν_{s}
. Since the output capacitors
C
_{2a}
,
C
_{2b}
are sufficiently large when compared to the resonant capacitors
C
_{1a}
,
C
_{1b}
, the capacitors of the two resonant loops can be equivalent as
C
_{1a}
,
C
_{1b}
, respectively. The state equations can be written as follows:
Here,
C
_{1a}
is equal to
C
_{1}
, and
C
_{1b}
is the same as
C
_{1a}
.
Consequently,
ν
_{C1a}
and
ν
_{C1b}
can be derived as:
Stage 8 [t_{7}, t_{8}]:
At
t
_{7}
,
S
_{3}
is turned on while its body diode has conducted. Hence,
S
_{3}
is turned on at ZVS.
i
_{L2}
increases continuously as (2), and
i
_{L1}
decreases linearly as follows:
Stage 9 [t_{8}, t_{9}]:
Similar to stage 4, the diodes
D
_{2}
,
D
_{3}
are turned off at ZCS. There is no reverserecovery problem for the diodes
D
_{2}
,
D
_{3}
. The antiparallel diode of the switch
S
_{3}
begins to conduct. The output current
I_{o}
is:
By combining (18) and (20),
I_{s,peak}
is obtained as:
Stage 10 [t_{9}, t_{10}]:
At
t
_{9}
, switch
S
_{3}
is turned off at ZVS. Similar operation stages work in the rest of the stages in a switching period.
In the operation analysis discussed above, the duty cycle
D
is more than 0.5. When
D
is less than 0.5, the operation analysis is similar but the switching sequence is different. The switching sequences of two cases are summarized in
Table II
.
SWITCHING SEQUENCE AT DIFFERENT DUTY CYCLE
SWITCHING SEQUENCE AT DIFFERENT DUTY CYCLE
It should be pointed out that the bottom switches
S
_{2}
,
S
_{4}
cannot achieve ZVS turnon in this topology. However, this issue can be solved by adding an auxiliary circuit. The boundary condition will be derived and discussed in future works due to page limitations.
An operation analysis of the switchedcapacitor doubler is discussed in Appendix A.
III. THE CONTROL SCHEME OF THE PROPOSED CONVERTER
Pulsewidth modulation plus phase angle shift (PPAS) is used as the control scheme in the proposed converter. The current doubler port is plotted in
Fig. 4
(a). An interleaved boost converter is employed in the current doubler port shown in
Fig. 4
(a), which is the front part of the proposed converter shown in the left dashed block in
Fig. 1
(a). Where,
V_{bus}
is equal to
V_{Cc}
,
ν_{p}
is the phase voltage difference between the leg
BB
_{1}
and the leg
BB
_{2}
. Steadystate waveforms of the control scheme are described in
Fig. 4
(b). Where,
D
is duty cycle of the switches
S
_{2}
and
S
_{4}
, and
Ts
is the switching period. It is noted that the phase angle between
BB
_{1}
and
BB
_{2}
is kept at a constant 180° to reduce the current ripple.
D
is employed as the only control freedom to achieve output voltage regulation. Once
D
is adjusted during a selected range, the phase voltage difference
ν_{p}
will vary correspondingly, as shown in
Fig. 4
(b). Hence, the transformer can be inserted into the primary side (point A and point B) and the switchedcapacitor circuit (point C and point D), as shown in
Fig. 1
, to realize output voltage regulation. The relationship between the duty cycle, the transformer turns ratio
N
and the voltage conversion is derived in the next section.
Control scheme of the proposed converter. (a) Current doubler port. (b) Key steadystate waveforms.
IV. PERFORMANCE ANALYSIS AND DESIGN CONSIDERATIONS OF THE CONVERTER
 A. Voltage Gain Ratio
The voltsecond balance law of L
_{1}
during one switching period determines the relation between
V_{in}
and
V_{Cc}
as follows:
Then, formula (22) can be derived as:
The voltsecond balance law of
L
_{lk}
during one switching period provides the following relationship between the resonant capacitor average voltage
V
_{c1a}
and
V_{o}
:
Where,
T_{o}
is the resonant period. Hence, the average voltage of the resonant capacitor
V
_{c1a}
is obtained as:
Due to symmetry,
V
_{c1b}
is equal to
V
_{c1a}
.
The average value
V
_{c1a}
is equal to the amplitude of
ν_{s}
, and the amplitude of
ν_{p}
is equal to
V_{Cc}
. Therefore, the relationship between the clamp capacitor voltage and the output voltage can be written as:
By combining (22) and (26), the relationship between the input voltage
V_{in}
and the output voltage
V_{o}
can be derived as:
 B. Resonant Capacitor
The existence of stage 3 and stage 8 ensures the ZCS turnoff for the rectifier diodes
D
_{1}
,
D
_{2}
,
D
_{3}
,
D
_{4}
. The interval of stage 3 and stage 8 changes with variations of resonant frequency and duty ratio. To achieve ZCS turnoff for all of the rectifier diodes
D
_{1}
,
D
_{4}
,
D
_{2}
, and
D
_{3}
, the following critical conditions must be satisfied:
Where,
ω_{r}
is the critical angular resonant frequency. Therefore, the resonant capacitor
C
_{1a}
must meet the following relationship:
The leak inductance is an inductive reactance by nature. If the leak inductance is too large, the output capability of the system will be influenced. Of course, this also influences the switching frequency, current and voltage stress of the resonant elements since it participants the resonance process. In practical transformer design, it is difficult for the real value of the leakage inductance to meet the theoretical value well and there is some deviation. Therefore, the switching frequency and the resonant capacitor are determined based on the leak inductance, which means that the switching frequency and resonant capacitor values will be adjusted with deviations of the leak inductance.
 C. Input Current Ripple
Assuming that the boost inductors
L
_{1}
and
L
_{2}
have the same value
L
, the inputcurrent ripple Δ
I_{in}
of the photovoltaic cell is:
The maximum input current ripple Δ
I
_{in,max}
occurs at the duty ratio D= 2/3. The maximum input current ripple Δ
I
_{in,max}
is:
The current ripple of
L
_{1}
and
L
_{2}
is:
The maximum current ripple at the duty ratio
D
=0.5 is:
From (31) and (33), the maximum input current ripple is much less than that of
i
_{L1}
and
i
_{L2}
.
 D. Topology Extension of the Proposed Converter
The proposed converter, composed of a current doubler and a quasiresonant switchedcapacitor circuit, can be extended to other converters. The first one is the extension on the primary port as shown in the left dashed block of
Fig. 5
(a)
5
(c), and the second one is the extension on the secondary port as show in the right dashed block of
Fig. 5
(a)
5
(c).
Extension of the proposed converter (a) Type I(b) Type II(c) Type III
The current doubler is extended into the three types shown in
Fig. 5
(a)(c). The primary port of type I is an interleaved buckboost converter. Unlike the proposed converter, the clamp capacitor is connected to the positive of the power source so that it can endure the lower voltage stresses of the clamp capacitor. However, a larger capacitance is required. Similarly, the primary port of type II is an interleaved buckboost converter. However, the upper switches
S
_{1}
,
S
_{3}
are employed as main switches and
V_{in}
is float. On the other hand, the primary port of type III is a currentfed half bridge converter. The currentfed DCDC isolated converters, use fewer switches without an active clamp circuit.
The switchedcapacitor circuit can be extended to attain a different voltage gain by adding or removing switchedcapacitor cells as shown in the green block of
Fig. 5
(a)(c). In
Fig. 5
(a)(c), there are two switchedcapacitor cells and 8 times the voltage of the transformer secondary winding can be reached in the output port. A general principle is that M switchedcapacitor cells are employed and 4M times the voltage is obtained through the switchedcapacitor circuit.
 E. Performance Comparison
For conventional currentfed fullbridge converters
[28]
, to provide a current path for the input inductor, the duty cycle of the primary main switches should be greater than 0.5 under any load condition. Consequently, an additional startup circuit should be designed to minimize the inrush current during the startup process. Meanwhile, the primary current should flow through two primary switches in most of the operation states, which results in large switch conduction losses. In addition, the current stress of the input inductor is high due to its whole input current maintenance. Last, the magnetizing currents of the two inductors cannot be limited since this leads to a minimum output power level. However, the mainswitch duty cycle of the proposed converter can vary from 0 to 1. When the duty cycle is lower than 0.5, the present converter may work in the discontinuous current mode with a light load. As a result, the ZVS performance is lost because the leakage energy is not sufficient to discharge the energy stored in the parallel capacitor when the corresponding clamp switch turns off. In addition, a wide dutycycle operation range is achieved in the proposed converter to remove the additional startup circuit. Moreover, the current stress of the magnetizing inductors is decreased because of the large input current distribution in the two interleaved phases. Finally, the primary switch conduction loss is reduced. This is because the primary current only flows through one switch and the average current stress on the activeclamp switches is relatively low. In other words, the proposed converter is more suitable for highefficiency, high stepup, and highpowerdensity dc/dc conversions when compared with the conventional currentfed fullbridge converters.
The authors of
[29]
presented a topology that is similar to the proposed converter except for the reduced clampedcapacitor utilized in primaryside of the proposed converter. The main difference is the control strategy. This results in different operation principles for the two converters. They have some similar merits, such as soft switching realization for primaryside MOSFET switches and secondaryside diodes, few turn ration of the transformer, and a low outputvoltage ripple. Due to the sawtoothwave current through the switches and diodes for the converter in
[29]
, there is higher peak current when compared with the sinewave current operation of the proposed converter at the same average output current. This means higher conduction losses in primaryside switches and in the secondaryside diodes for the converter in
[29]
.
A more detailed comparison between the conventional currentfed full bridge converter, the converter in
[29]
and the proposed converter is summarized in
Table III
. Assume that the three converters have the same power rating and voltage gain. Define
V_{in}
,
I_{in}
,
U_{o}
,
I_{o}
, and
D
as the input voltage, input current, output voltage, output current and duty cycle, respectively. Introduce the concept of DPTR (device power total rating, which is equal to the current rating times the voltage rating) to descript the device cost.
PERFORMANCE COMPARISON
 F. Design Consideration
The 400W design procedure of the proposed converter is shown here as an example. Some of the specifications of the prototype converter are set first:
V_{in}
=25V,
V_{o}
= 200 V,
P_{o}
= 400 W,
N
_{1}
/
N
_{2}
=18:18,
L_{k}
=1uH, and
f_{s}
=50 kHz.
1) Resonant Frequency
: In order to provide ZCS turnoff for the rectifier diodes
D
_{1}
,
D
_{2}
,
D
_{3}
,
D
_{4}
, in addition to making sure the switching frequency is lower than the resonant frequency, other relations need to be satisfied:
Where,
T_{o}
is resonant period. Here, set
f_{o}
=80KHz.
2) Resonant Capacitor
: The resonant capacitance value should meet (29), and it should be chosen according to the voltage ripple
[26]
[27]
. A detailed derivation is discussed in Appendix A:
Where,
C
_{1}
is resonant capacitor value. The value of the voltage ripple is determined by the output current, the resonant capacitance value and the switching frequency. The capacitor voltage ripple should be smaller than the average voltage (equal to
v_{s}
) to prevent voltage across the resonant capacitor from the positive to negative region and losing ZCS. This means that the resonant capacitor should have a positive dc voltage offset.
3) Output Capacitor
: Another consideration is that the maximum voltage ripple should be less than one third of the dc component. Here, a 20% voltage ripple is considered for the resonant capacitor. Then the resonant capacitance value can be derived as:
Here, a 2uF resonant capacitor is selected.
C
_{2}
is large enough to maintain a constant voltage for each stage.
Where,
θ
=sin
^{1}
(
fs
)/(
πf_{o}
) and
I_{o}
= (
P_{o}
)/(
V_{o}
) .
For a 0.1 V ripple voltage, this gives
C
_{2}
=59.2uF and 47uF is selected.
4) Duty Cycle
: According to (34), the duty cycle range is selected to be 0.3375<
D
<0.6625. In the experiments,
D
is selected to be 0.5.
5) Other Considerations
: The boost inductor is selected according to formula (33). Here, two 60uH inductors are used.
Since the peak voltage stresses on the diodes
D
_{1}
,
D
_{2}
,
D
_{3}
,
D
_{4}
are equal to half of the output voltage
V_{o}
, the block voltage of the diodes are chosen to be
V_{o}
for twice the voltage stress concern.
V. SIMULATION AND EXPERIMENTAL RESULTS
The specifications for the simulation are shown in
Table IV
. A prototype of the proposed converter plotted in
Fig. 1
is implemented. The prototype is operated with the parameters shown in
Table V
.
SIMULATION SPECIFICATION OF THE PROPOSED CONVERTER
SIMULATION SPECIFICATION OF THE PROPOSED CONVERTER
PARAMETERS OF THE PROTOTYPE
PARAMETERS OF THE PROTOTYPE
The saber simulation waveforms of the proposed converter are shown in
Fig. 6
.
Simulation waveforms.
The simulation waveforms verify the principle of the proposed converter and the feasibility of the operation is validated.
Fig. 7
shows the ZCS realization of the rectifier diodes. In
Fig. 7
(a),
i
_{D1}
and
i
_{D2}
decrease to zero before the diodes
D
_{1}
,
D
_{2}
are reverse biased, and
D
_{1}
,
D
_{2}
achieve ZCS turnoff. Analogously,
D
_{3}
,
D
_{4}
achieve ZCS turnoff as shown in
Fig. 7
(b). From the waveforms, it is noted that the reverserecovery problem has been removed.
Voltage/current waveforms of the rectifier diodes. (a) Waveforms of D_{1}, D_{2}. (b) Waveforms of D_{3}, D_{4}.
Fig. 8
shows the voltage and current waveforms across the primary/secondary windings of the transformer. The primary/secondary winding currents agree with the theoretical analysis and the primary voltage spike is suppressed partly due to the clamp capacitor. A high frequency resonance occurs as shown in
Fig. 8
(a) because of the parasitic capacitor of the transformer. This will kill the system efficiency.
Voltage/current of transformer windings. (a) Primary winding. (b) Secondary winding.
Fig. 9
shows the input/output characteristic of the proposed converter. The ripple of the input current is reduced greatly as shown in
Fig. 9
(a). Due to the symmetrical duty cycle of the switches
S
_{2}
,
S
_{4}
, the two boost inductors work in an interleaved way to be charged or discharged, and the input current is almost ripple free.
Fig. 9
(b) shows the input/output voltage and the current waveforms together. The output voltage drops to 188V from the theoretical 200V under the open loop control due to the output impedance. The voltage drop includes the device (MOSFETs and rectifier diodes) drop voltage and the transformer voltage drop. It is noted that the output voltage is almost ripple free due to the alternate charging and discharging of the output capacitors.
Input/output characteristic of the proposed converter. (a) Current waveforms of i_{L1},i_{L2}, I_{in}. (b)Input/output voltage and current.
Fig. 10
shows the voltage of the switchedcapacitors.
V
_{c1a}
and
V
_{c1b}
are the dc voltages with a sinusoidal ripple determined by the resonant parameters and load as calculated in (34)(35),
V
_{c2a}
and
V
_{c2b}
have relatively large capacitances. As a result, the voltage is basically constant. In theoretical calculation,
V
_{c2a}
=
V
_{c2b}
=100V.
Switchedcapacitors voltage.
In
Fig.11
, the voltage spike of the main switches is reduced by the activeclamp circuit. The clampcapacitor voltage calculated from (22) is 25V for a duty cycle that is close to 0.5. Hence,
S
_{3}
(the drainsource voltage of the auxiliary switch) along with
V
_{ds3}
and
V
_{ds4}
(the drainsource voltage of the main switch
S
_{4}
) are clamped to be about 50V, which agrees with the theoretical waveforms. It should be mentioned that ZVS turnon/off is realized for the switch
S
_{3}
.
Drainsource voltage waveforms of switches S_{3}&S_{4} and current waveforms of switches S_{3}&S_{4}.
With the selected parameters, the estimated power loss distribution is calculated and summarized in
Fig.12
. The loss includes the main switches conduction loss P
_{Input_MC}
, the main switches switching loss P
_{Input_MS}
, the clamp switches conduction loss P
_{Input_C}
, the inputside boost inductors conduction loss P
_{Input_L}
, the outputside diodes conduction loss P
_{Output_D}
, the magnetic core loss of the transformer P
_{Mag_Core}
, the primary copper loss of the transformer P
_{MagPri_Co}
, and the secondary copper loss of the transformer P
_{MagSec_Co}
. It can be found that the main switches loss and the primary copper loss are dominant for the loss distribution. The estimated efficiency at a 400w load with a 25V input and a 200V output is about 94.86%.
Loss breakdown distribution at 400W load.
The main switches conduction loss and the primary copper loss of the transformer are dominant due to a high primary current. In addition, the output diodes conduction loss covers a relative breakdown because of the relative high forward voltage of the diodes. Since the diodes are turned off at ZCS, it is better to utilize diodes with a lower forward voltage to promote system efficiency.
The measured efficiency of the proposed converter under all load conditions is presented in
Fig.13
. The maximum efficiency is over 94.79% at a 300W load. Due to ZCS realization for all of the rectifier diodes and ZVS turnoff/turnon realization for the auxiliary switches
S
_{1}
,
S
_{3}
. The efficiency of the proposed converter is high but relatively low at a light load since the basic loss weight increases in the whole power range.
Measured efficiency.
VI. CONCLUSION
This paper presents a high stepup DCDC converter for photovoltaic power systems. The characteristic of the proposed converter can be summarized as follows:

1) The diodes are turned off at ZCS to solve the reverserecovery problem and the maximum voltage stress of the rectifier diodes is reduced to one half of the output voltage.

2) The symmetrical structure of the switchedcapacitor circuit results in an output voltage ripple reduction because the ripples on the charging capacitor and discharging capacitor cancelled each other out.

3) The double boost inductors are operated in an interleaved way to minimize the input current ripple.

4) The voltage spike of the MOSFETs is suppressed by an active clamp circuit.

5) The leakage of the twowinding transformer is shared by two resonant loops to reduce the complexity of the transformer.

6) The PPAS control strategy is employed in the proposed converter to control the output voltage.
Acknowledgements
The research work was supported by the National Nature Science Foundations of China (No.61403320), the Natural Science Foundation of Fujian Province (No. 2015J201274) and the Fundamental Research Funds For Central University (No.2013121017, No. 20720150088). The support from Collaborative Innovation Center of HighEnd Equipment Manufacturing in FuJian is also acknowledged.
BIO
Liangzong He was born in Hunan, China, in 1984. In September 2012, he joined Xiamen University, Xiamen, China, as an Assistant Professor. His current research interests include DCDC converters, switchedcapacitor converters, Zsource converters, and renewable energy generation.
Tao Zeng was born in Hunan, China, in 1983. He is presently an Assistant Professor in Department of Mechanical and Electrical Engineering, Xiamen University, Xiamen, China. His current research interests include the design of switching power supplies, and the design of haptic devices for shape and texture rendering.
Tong Li was born in Hubei, China, in 1989. He is presently working toward the master degree in Department of Mechanical and Electrical Engineering, Xiamen University, Xiamen, China. His current research interests include acac switchedcapacitor converters, and renewable energy generation.
Yuxian Liao was born in Fujian, China, in 1989. He is presently working toward the master degree in Department of Mechanical and Electrical Engineering, Xiamen University, Xiamen, China. His current research interests include renewable energy generation and wireless power transmission.
Wei Zhou received his Ph.D. degree in Mechanical Engineering from the South China University of Technology, Guangzhou, China. From 2010 to 2012, he was a Postdoctoral Researcher at Sun Yatsen University, Guangdong, China. He is presently an Associate Professor at Xiamen University Xiamen, China. His current research interests include the design, fabrication and performance evaluation of energy and biomedical devices.
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