This paper presents a 1.92 kW resonant converter for medium voltage applications that uses low voltage stress MOSFETs (500V) to achieve zero voltage switching (ZVS) turnon. In the proposed converter, four MOSFETs are connected in series to limit the voltage stress of the power switches at half of the input voltage. In addition, three resonant circuits are adopted to share the load current and to reduce the current stress of the passive components. Furthermore, the transformer primary and secondary windings are connected in series to balance the output diode currents for medium power applications. Split capacitors are adopted in each resonant circuit to reduce the current stress of the resonant capacitors. Two balance capacitors are also used to automatically balance the input capacitor voltage in every switching cycle. Based on the circuit characteristics of the resonant converter, the MOSFETs are turned on under ZVS. If the switching frequency is less than the series resonant frequency, the rectifier diodes can be turned off under zero current switching (ZCS). Experimental results from a prototype with a 750800 V input and a 48V/40A output are provided to verify the theoretical analysis and the effectiveness of the proposed converter.
I. I NTRODUCTION
Fullbridge converters with a simple structure, constant frequency pulsewidth modulation and soft switching turnon
[1]

[4]
have been adopted in medium power applications. However, power switches should suffer the input voltage due to the fullbridge structure. High input DC/DC converters have been developed for ship electric power distribution systems
[5]
, threephase AC/DC converters and the traction systems for light trains
[6]

[7]
. Threelevel DC/DC converters
[8]

[10]
with low voltage and current stresses were presented to reduce the voltage stress on active switches. However, the power switches are operated at hard switching. High switching losses on the power switches reduce the circuit efficiency. In order to achieve soft switching and reduce switching losses, threelevel zero voltage switching (ZVS) converters for high input voltage applications were proposed in
[11]

[14]
. In
[13]
, four power switches with
V_{in}
/2 voltage stress and two power switches with
V_{in}
voltage stress are used in the threelevel ZVS hybrid full bridge converter. The drawback of this circuit is that two power switches with high voltage stress are used in this converter. Resonant converters
[15]

[18]
have been proposed for the advantages of high conversion efficiency and high power density. Power switches are turned on under ZVS from low load to full load. If the switching frequency is less than the series resonant frequency, the rectifier diodes at output side are turned off under zero current switching (ZCS). The seriesparallel connection techniques have been discussed in
[19]

[21]
. In
[19]
, two transformers are adopted in threelevel converter with current double rectifier for medium voltage application. However, the high current rating of rectifier diodes and large size of filter inductors are needed in this circuit topology for high load current application. The circuit efficiency will be drop at light load due to the high circulating current in conventional threelevel PWM converter. The input split capacitor voltages cannot be automatically balanced. An active clamp forward converter with parallel connection in primary side was presented in
[20]
to achieve soft switching. However, this circuit topology cannot be used for medium voltage applications due to its high voltage stress on the power switches. A threelevel resonant converter with duty cycle control has been presented in
[21]
to have ZVS turnon for all of the power switches and ZCS turnoff for all of the rectifier diodes. The output currents of the two secondary sides are automatically balanced due to the series connection of the transformers. However, the input split capacitor voltages cannot be balanced automatically and the duty cycle is decreased under a light load case. Thus, the circuit efficiency under a light load is decreased.
A ZVS DC/DC converter for high input voltage and load current applications is studied in this paper. Two halfbridge legs with split capacitors are connected in series at the high voltage side to clamp the voltage stress of the power switches at half of the input voltage. Two balance capacitors are used between the AC sides of the two halfbridge legs to automatically balance the input split capacitor voltages. Three resonant circuits are used at the high voltage side in order to reduce the current stress of the resonant components. The secondary windings of the transformers are connected in series to automatically balance the output diode currents. Since the input impedance of the resonant tank is an inductive load at the switching frequency, the power switches are turned on under ZVS. As a result, the switching losses on the power switches are reduced. Finally, experiments from a 750800
V_{in}
put and 48V/40A output prototype were provided to verify the performance of the proposed converter.
II. PROPOSED CONVERTER AND OPERATION PRINCIPLE
For threephase power factor corrector converters with a 380V or 480V utility voltage or a DC traction system, the input voltage of the DC/DC converter is equal to or higher than 750V.
Fig. 1
gives the circuit topology of the proposed converter for medium voltage applications. The circuit components at the high voltage side include the input voltage
V_{in}
, power MOSFETs
S
_{1}

S
_{4}
with their body diodes and parallel capacitors
C
_{oss}
_{1}

C
_{oss}
_{4}
, resonant capacitors
C
_{r}
_{1}

C
_{r}
_{6}
, resonant inductors
L
_{r}
_{1}

L
_{r}
_{3}
, and transformers
T
_{1}

T
_{4}
. Two centertapped rectifiers are used at the low voltage side to share the load current and to reduce the current stress of the passive components. The secondary windings of
T
_{1}
and
T
_{3}
are connected in series so that the primary currents
i
_{Lr}
_{1}
and
i
_{Lr}
_{3}
are balanced. Similarly, the primary currents
i
_{Lr}
_{2}
and
i
_{Lr}
_{3}
are balanced since the secondary windings of
T
_{2}
and
T
_{4}
are connected in series. Thus, the primary and secondary winding currents of
T
_{1}

T
_{4}
are balanced. (
S
_{1}
and
S
_{3}
) and (
S
_{2}
and
S
_{4}
) have the same PWM waveforms with a 0.5 duty cycle. However, the driving signals of
S
_{2}
and
S
_{4}
are complementary with the driving signals of
S
_{1}
and
S
_{3}
with a short dead time. The components
S
_{1}

S
_{4}
and
C
_{r}
_{1}

C
_{r}
_{6}
establish a switched capacitor circuit
[22]
. Therefore, the input capacitor voltages are balanced,
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
=
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
V_{in}
/2. The proposed converter includes three resonant circuits at the high voltage side. A variable frequency scheme is adopted to regulate the output voltage.
Circuit configuration of the proposed converter.
The following assumptions are presumed to simplify the system analysis of the three resonant circuits. The transformers
T
_{1}

T
_{4}
have the magnetizing inductances
L_{m}
_{1}
=
L_{m}
_{2}
=2
L_{m}
_{3}
=2
L_{m}
_{4}
=
L_{m}
and the turns ratios
n
_{1}
=
n
_{2}
=2
n
_{3}
=2
n
_{4}
=
n
. The resonant capacitances are
C
_{r}
_{1}
=
C
_{r}
_{2}
=
C
_{r}
_{3}
=
C
_{r}
_{4}
=
C
_{r}
_{5}
=
C
_{r}
_{6}
=
C_{r}
. The resonant inductances are identical
L
_{r}
_{1}
=
L_{r}
2 =
L
_{r}
_{3}
=
L_{r}
. The power MOSFETs
S
_{1}

S
_{4}
have the same output capacitances
C
_{oss}
_{1}
=
C
_{oss}
_{2}
=
C
_{oss}
_{3}
=
C
_{oss}
_{4}
=
C_{oss}
. The capacitor voltages
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
=
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
V_{in}
/2. If the switching frequency
f_{sw}
is less than the series resonant frequency
f_{r}
, there are six operating modes in a switching cycle. The main PWM waveforms of the proposed converter under
f_{sw}
<
f_{r}
are shown in
Fig. 2
and
Fig. 3
. They give the corresponding equivalent circuit for each operation mode. If the switching frequency
f_{sw}
>
f_{r}
, then the resonant circuit has only four operation modes (modes 1, 3, 4 and 6) in a switching cycle. In the following statements, the six modes of operation are discussed in each switching cycle. Before time
t_{0}
,
S
_{1}

S
_{4}
,
D
_{2}
and
D
_{4}
are in the offstate.
C
_{oss}
_{1}
and
C
_{oss}
_{3}
are discharged, and
C
_{oss}
_{2}
and
C
_{oss}
_{4}
are charged.
Key waveforms of the proposed converter.
Operation modes of the proposed converter in a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6.
Mode 1 [t_{0}  t_{1}]:
Mode 1 starts at time
t
_{0}
when
C
_{oss}
_{1}
and
C
_{oss}
_{3}
are discharged to zero voltage. Since
i
_{Lr}
_{1}
(
t
_{0}
)<0,
i
_{Lr}
_{2}
(
t
_{0}
)<0 and
i
_{Lr}
_{3}
(
t
_{0}
)<0, the antiparallel diodes of
S
_{1}
and
S
_{3}
are conducting. Thus,
S
_{1}
and
S
_{3}
are turned on at this moment under ZVS. The voltage stresses of
S
_{2}
and
S
_{4}
are equal to
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
and
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
, respectively. In this mode, the capacitor voltage
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
. On the other hand, the capacitor voltage
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
in mode 3. Thus, it can be obtained that
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
=
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
V_{in}
/2 in steady state. Since
i
_{Lr}
_{1}
>
i
_{Lm}
_{1}
,
i
_{Lr}
_{2}
>
i
_{Lm}
_{2}
and
i
_{Lr}
_{3}
>
i
_{Lm}
_{3}
, diodes
D
_{1}
and
D
_{3}
are conducting. In this mode,
v
_{Lm}
_{1}

v
_{Lm}
_{4}
are positive and
i
_{Lm}
_{1}

i
_{Lm}
_{5}
increase. In addition,
L
_{r}
_{1}
,
C
_{r}
_{1}
and
C
_{r}
_{2}
are resonant in circuit 1;
L
_{r}
_{2}
,
C
_{r}
_{3}
and
C
_{r}
_{4}
are resonant in circuit 2;
L
_{r}
_{3}
,
C
_{r}
_{5}
and
C
_{r}
_{6}
are resonant in circuit 3; and power is transferred from the input voltage
V_{in}
to the output load
R_{o}
. The resonant frequency is
Mode 2 [t_{1}  t_{2}]:
At time
t
_{1}
,
i
_{Lr}
_{1}
(
t
_{1}
)=
i
_{Lm}
_{1}
(
t
_{1}
),
i
_{Lr}
_{2}
(
t
_{1}
)=
i
_{Lm}
_{2}
(
t
_{1}
) and
i
_{Lr}
_{3}
(
t
_{1}
)=
i
_{Lm}
_{3}
(
t
_{1}
)=
i
_{Lm}
_{4}
(
t
_{1}
). Thus, diodes
D
_{1}

D
_{4}
are all in the offstate. In this mode,
L
_{r}
_{1}
,
L_{m}
_{1}
,
C
_{r}
_{1}
and
C
_{r}
_{2}
are resonant in circuit 1;
L_{r}
_{2}
,
L_{m}
_{2}
,
C
_{r}
_{3}
and
C
_{r}
_{4}
are resonant in circuit 2; and
L
_{r}
_{3}
,
L_{m}
_{3}
,
L_{m}
_{4}
,
C
_{r}
_{5}
and
C
_{r}
_{6}
are resonant in circuit 3. The resonant frequency is
Mode 3 [t_{2}  t_{3}]:
At time
t
_{2}
,
S
_{1}
and
S
_{3}
are turned off. Diodes
D
_{2}
and
D
_{4}
are conducting,
v
_{Lm}
_{1}

v
_{Lm}
_{4}
are negative, and
i
_{Lm}
_{1}

i
_{Lm}
_{4}
decrease. Since
i
_{Lr}
_{1}
(
t
_{2}
)>0,
i
_{Lr}
_{2}
(
t
_{2}
)>0 and
i
_{Lr}
_{3}
(
t
_{2}
)>0,
C
_{oss}
_{1}
and
C
_{oss}
_{3}
are charged and
C
_{oss}
_{2}
and
C
_{oss}
_{4}
are discharged.
C
_{oss}
_{2}
and
C
_{oss}
_{4}
can be discharged to zero voltage if the energy stored in
L
_{r}
_{1}

L
_{r}
_{3}
at
t
_{2}
is greater than the energy stored in
C
_{oss}
_{1}

C
_{oss}
_{4}
.
Mode 4 [t_{3}  t_{4}]:
At time
t
_{3}
,
v
_{Coss}
_{2}
=
v
_{Coss}
_{4}
=0. Since
i
_{Lr}
_{1}
(
t
_{3}
)>0,
i
_{Lr}
_{2}
(
t
_{3}
)>0 and
i
_{Lr}
_{3}
(
t
_{3}
)>0, the antiparallel diodes of
S
_{2}
and
S
_{4}
are conducting.
S
_{2}
and
S
_{4}
can be turned on at this moment under ZVS. In mode 4,
D
_{2}
and
D
_{4}
are conducting,
i
_{Lm}
_{1}

i
_{Lm}
_{4}
decrease. In addition,
v
_{Coss}
_{1}
=
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
,
v
_{Coss}
_{3}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
, and
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
=
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
.
L
_{r}
_{1}
,
C
_{r}
_{1}
and
C
_{r}
_{2}
are resonant in circuit 1;
L_{r}
2 ,
C
_{r}
_{3}
and
C
_{r}
_{4}
are resonant in circuit 2;
L
_{r}
_{3}
,
C
_{r}
_{5}
and
C
_{r}
_{6}
are resonant in circuit 3; and power is transferred from the input voltage
V_{in}
to the output load
R_{o}
. The resonant frequency is
Mode 5 [t_{4}  t_{5}]:
At time
t
_{4}
,
i
_{Lr}
_{1}
(
t
_{4}
)=
i
_{Lm}
_{1}
(
t
_{4}
),
i
_{Lr}
_{2}
(
t
_{4}
)=
i
_{Lm}
_{2}
(
t
_{4}
) and
i
_{Lr}
_{3}
(
t
_{4}
)=
i
_{Lm}
_{3}
(
t
_{4}
)=
i
_{Lm}
_{4}
(
t
_{4}
). Diodes
D
_{1}

D
_{4}
are all in the offstate.
L
_{r}
_{1}
,
L_{m}
_{1}
,
C
_{r}
_{1}
and
C
_{r}
_{2}
are resonant in circuit 1;
L_{r}
_{2}
,
L_{m}
_{2}
,
C
_{r}
_{3}
and
C
_{r}
_{4}
are resonant in circuit 2;
L
_{r}
_{3}
,
L_{m}
_{3}
,
L_{m}
_{4}
,
C
_{r}
_{5}
and
C
_{r}
_{6}
are resonant in circuit 3; and the resonant frequency is
Mode 6 [t_{5}  T+t_{0}]:
At time
t
_{5}
,
S
_{2}
and
S
_{4}
are turned off. Diodes
D
_{1}
and
D
_{3}
are conducting. The magnetizing voltages
v
_{Lm}
_{1}

v
_{Lm}
_{4}
are positive and the magnetizing currents
i
_{Lm}
_{1}

i
_{Lm}
_{4}
increase. Since
i
_{Lr}
_{1}
(
t
_{5}
)<0,
i
_{Lr}
_{2}
(
t
_{5}
)<0 and
i
_{Lr}
_{3}
(
t
_{5}
)<0,
C
_{oss}
_{1}
and
C
_{oss}
_{3}
are discharged and
C
_{oss}
_{2}
and
C
_{oss}
_{4}
are charged.
C
_{oss}
_{1}
and
C
_{oss}
_{3}
can be discharged to zero voltage if the energy stored in
L
_{r}
_{1}

L
_{r}
_{3}
at
t
_{5}
is greater than the energy stored in
C
_{oss}
_{1}

C
_{oss}
_{4}
. Then, the operating modes of the proposed converter in a switching period are completed.
III. CONVERTER PERFORMANCE ANALYSIS AND DESIGN EXAMPLE
Three resonant circuits are included in the proposed converter to share the load power. The power transferred through the three resonant circuits is a function of the switching frequency. The input terminal of the resonant circuit is a square wave voltage. If the bandwidth of the resonant circuit is less than the switching frequency, the harmonics of the input square wave voltage can be neglected at the output terminal. The secondary side currents
i
_{D}
_{1}
+
i
_{D}
_{2}
and
i
_{D}
_{3}
+
i
_{D}
_{4}
are quasisinusoidal currents. If the primary inductor currents are greater than the magnetizing currents, then diodes
D
_{1}
and
D
_{3}
are conducting and
v
_{Lm}
_{1}
=
v
_{Lm}
_{2}
=
nV_{o}
/2 and
v
_{Lm}
_{3}
=
v
_{Lm}
_{4}
=
nV_{o}
/4. On the other hand,
v
_{Lm}
_{1}
=
v
_{Lm}
_{2}
=
nV_{o}
/2,
v
_{Lm}
_{3}
=
v
_{Lm}
_{4}
=
nV_{o}
/4 and rectifier diodes
D
_{2}
and
D
_{4}
are conducting when the primary inductor currents are less than the magnetizing currents. Since the charge/discharge time of output capacitors
C
_{oss}
_{1}

C
_{oss}
_{4}
in modes 3 and 6 and the time intervals in modes 2 and 5 are much less than the time intervals in modes 1 and 4, the magnetizing inductor voltages
v
_{Lm}
_{1}

v
_{Lm}
_{4}
approximate quasisquare waveforms.
where
θ_{m}
is the phase angle of the
m
th harmonic frequency. The peak secondary winding currents are given as:
Thus, the load resistance
R_{o}
reflected to the transformer primary sides is shown as:
Fig. 4
shows the AC resonant circuits excited by the effective sinusoidal input voltage and the effective resistive loads
R
_{ac,}
_{1}

R
_{ac,}
_{4}
. The input impedances
Z
_{in,}
_{1}

Z
_{in,}
_{3}
of the resonant circuits are expressed as:
Equivalent circuit of the proposed converter for the derivation of steady state model.
The frequency modulation (FM) approach is adopted to regulate the AC voltage gain of the resonant circuit. The AC voltage gain of the resonant circuit is approximately expressed as:
where
k
=
L_{r}/L_{m}
and
f_{s}
is the switching frequency. The DC voltage gain
G_{dc}
of the proposed converter is given as
G_{dc}
= 2
nV_{o}/V_{in}
. The AC voltage gain at the noload condition (
Q
=0) and
f_{s}
=∞ is given as
G_{ac}(f)_{NLfs}
_{=∞}
=1/(1+
k
). In order to regulate the output voltage from noload to full load, the minimum DC voltage gain must be greater than the AC voltage gain at the noload condition. Thus, the minimum turns ratio of transformers T
_{1}
and
T
_{2}
is given in (9).
A design example of the prototype circuit is provided in order to verify the system analysis of the proposed converter. A laboratory prototype was constructed to verify the effectiveness of the proposed converter. The electric specifications are
V_{in}
=750800 V,
V_{o}
=48 V, and
I_{o,rated}
=40 A. The selected series resonant frequency
f_{r}
is 120 kHz. The selected inductance ratio
L_{m}
/
L_{r}
=1/
k
=7.
 A. Turns Ratio ofT1T4
In the prototype circuit, the DC voltage gain is equal to
G_{dc}
=2
nV_{o}
/
V_{in}
. Thus, the minimum turns ratio is given as
n
=
G_{dc,min}V_{in,micdc}
/(2
V_{o}
) If the minimum DC voltage gain is selected as unity at the series resonant frequency, then the turns ratio of
T
_{1}

T
_{4}
is given as:
The actual primary and secondary turns used in
T
_{1}

T
_{4}
are
n
_{p,T}
_{1}
=
n
_{p,T}
_{2}
=66 turns,
n
_{s,T}
_{1}
=
n
_{s,T}
_{1}
=8 turns,
n
_{p,T}
_{3}
=
n
_{s,T}
_{4}
=33 turns and
n
_{s,T}
_{3}
=
n
_{s,T}
_{4}
=8 turns. The actual turns ratios of
T
_{1}
and
T
_{2}
are 8.25, and the turns ratios of
T
_{3}
and
T
_{4}
are 4.125.
 B. DC Voltage Gain of the Proposed Converter
Based on the selected turns ratio of
T
_{1}

T
_{4}
, the minimum and maximum DC voltage gains of the proposed converter are derived as:
 C. Q Value at Full Load and AC Equivalent Resistance
Fig. 5
gives the AC voltage gain versus the frequency ratio
f_{s}
/
f_{r}
with
k
=1/7. Since the minimum and maximum DC gains are 0.99 and 1.056, respectively, the maximum
Q
at a full load should be less than 0.4 in order to effectively regulate the output voltage. In this prototype, the
Q
value at a full load is selected as 0.4. Based on (4) and (5), the AC equivalent resistances
R
_{ac,}
_{1}

R
_{ac,}
_{4}
at a full load are derived as:
AC voltage gain and DC voltage gain at different frequency ratio f_{s}/f_{r}.
 D. Resonant Capacitances and Inductances
Since
the resonant capacitances
C_{r}
_{1}

C_{r}
_{6}
and inductances
L_{r}
_{1}

L_{r}
_{3}
are obtained as:
The magnetizing inductances of
T
_{1}

T
_{4}
are expressed as:
 E. Power Semiconductors
The input maximum voltage is 800 V and the voltage stresses of
S
_{1}

S
_{4}
are equal to
V_{in}
/2=400 V. Power MOSFETs (IRFP460) with a 500 V voltage rating and a 13 A current rating at
100℃
are used for power switches
S
_{1}

S
_{4}
. The output voltage is 48 V and the load current is 40 A. The average currents of
D
_{1}

D
_{4}
are equal to 40 A/4=10 A. The voltage stresses of
D
_{1}

D
_{4}
are equal to 2
V_{o}
=96 V. Fast recovery diodes (KCU30A20) with a 200 V voltage rating and a 30 A current rating are adopted for
D
_{1}

D
_{4}
in the prototype circuit.
IV. EXPERIMENTAL RESULTS
Based on the derived circuit parameters in the previous section, experimental verification is provided to demonstrate the performance of the proposed circuit. The measured PWM waveforms of
S
_{1}

S
_{4}
at different input voltages and load conditions are given in
Fig. 6
.
S
_{1}
and
S
_{3}
have the same PWM waveforms, and
S
_{2}
and
S
_{4}
have identical PWM signals. However, the PWM signals of
S
_{1}
and
S
_{2}
are complementary each other to avoid short circuits at each halfbridge leg. At the same load power, the switching frequency at a low input voltage
V_{in}
=750 V is less than the switching frequency at a high input voltage
V_{in}
=800 V. At the same input voltage,
V_{in}
=800 V, the switching frequency at a full load is less than the switching frequency at a light load.
Fig. 7
gives the measured switching frequency of the proposed converter at different input voltages and load conditions. The measured waveforms of the gate voltage and drain voltage of
S
_{1}
and
S
_{2}
at different input voltages and load conditions are illustrated in
Fig. 8
. In the same manner,
Fig. 9
gives the test results of the gate voltage and drain voltage of
S
_{3}
and
S
_{4}
at different input voltages and load conditions. Before
S
_{1}

S
_{4}
are turned on, the drain voltages are decreased to zero voltage. Therefore, the ZVS turnon of
S
_{1}

S
_{4}
is achieved.
Fig. 10
shows the test waveforms of
i
_{Lr}
_{1}

i
_{Lr}
_{3}
at a full load and different input voltages. It is clear that inductor currents
i
_{Lr}
_{1}
and
i
_{Lr}
_{2}
are balanced.
Fig. 11
(a) shows the test waveforms of
v
_{Cr}
_{1}

v
_{Cr}
_{6}
at a full load and
V_{in}
=750 V. It is clear that
v
_{Cr}
_{1}
,
v
_{Cr}
_{3}
and
v
_{Cr}
_{6}
have the same voltage waveforms and that the voltage waveforms of
v
_{Cr}
_{2}
,
v
_{Cr}
_{4}
and
v
_{Cr}
_{5}
are balanced.
Fig. 11
(b) shows the test results of
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
,
v
_{Cr}
_{3}
+
v
_{C}
_{4}
and
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
. From the test results in
Fig. 11
(b), it can be seen that the three voltages
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
,
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
and
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
are balanced. In the same manner, the measured voltages
v
_{Cr}
_{1}

v
_{Cr}
_{6}
,
v
_{Cr}
_{1}
+
v
_{Cr}
_{2}
,
v
_{Cr}
_{3}
+
v
_{Cr}
_{4}
and
v
_{Cr}
_{5}
+
v
_{Cr}
_{6}
at
V_{in}
=800 V are shown in
Fig. 12
.
Fig. 13
shows the measured gate voltage
v
_{S}
_{1,}
_{gs}
and the output diode currents
i
_{D}
_{1}

i
_{D}
_{4}
at a full load and different input voltages. The diode currents
i
_{D}
_{1}
and
i
_{D}
_{3}
are balanced, and
i
_{D}
_{2}
and
i
_{D}
_{4}
are also balanced. The measured circuit efficiencies at different loads are shown in
Fig. 14
. The measured efficiency is greater than 92% from a 25% load to a full load.
Measured PWM waveforms of S_{1}S_{4} at (a) V_{in}=750 V and 25% load. (b) V_{in}=750 V and 100% load. (c) V_{in}=800 V and 25% load. (d) V_{in}=800 V and 100% load.
Measured switching frequencies at different input voltages and load conditions.
Measured results of gate voltage and drain voltage of active switches. (a) S_{1} and S_{2} at 25% load with V_{in}=750 V. (b) S_{1} and S_{2} at 100% load with V_{in}=750 V. (c) S_{1} and S_{2} at 25% load with V_{in}=800 V. (d) S_{1} and S_{2} at 100% load with V_{in}=800 V.
Measured results of gate voltage and drain voltage of active switches. (a) S_{3} and S_{4} at 25% load with V_{in}=750 V. (b) S_{3} and S_{4} at 100% load with V_{in}=750 V. (c) S_{3} and S_{4} at 25% load with V_{in}=800 V. (d) S_{3} and S_{4} at 100% load with V_{in}=800 V.
Measured results of the resonant inductor currents i_{Lr}_{1}i_{Lr}_{3} at full load and (a) V_{in}=750 V. (b) V_{in}=800 V.
Measured capacitor voltage waveforms of C_{r}_{1}C_{r}_{6} at V_{in}=750 V and full load. (a) v_{Cr}_{1}v_{Cr}_{6}. (b) v_{Cr}_{1}+v_{Cr}_{2}, v_{Cr}_{3}+v_{Cr}_{4} and v_{Cr}_{5}+v_{Cr}_{6}.
Measured capacitor voltage waveforms of C_{r}_{1}C_{r}_{6} at V_{in}=800 V and full load. (a) v_{Cr}_{1}v_{Cr}_{6}. (b) v_{Cr}_{1}+v_{Cr}_{2}, v_{Cr}_{3}+v_{Cr}_{4} and v_{Cr}_{5}+v_{Cr}_{6}.
Measured output diode currents at full load under (a) V_{in}=750 V (b) V_{in}=800 V.
Measured efficiencies at different input voltages and load conditions.
V. CONCLUSION
A new soft switching DC/DC converter with balanced diode currents at the output side and low voltage stress of the power MOSFETs is presented for medium voltage applications. Three resonant circuits are adopted at the primary side and a seriesconnection of isolation transformers at the secondary side in order to balance the output diode currents of the proposed converter. The power rating of each resonant circuit is equal to half of the load power so that the current stresses of the passive components and transformer windings are reduced. Two halfbridge circuits with four spilt capacitors are adopted so that the voltage stress of the power MOSFETs are clamped at half of the input voltage. Two resonant capacitors
C
_{r}
_{5}
and
C
_{r}
_{6}
are also adopted to balance the input split capacitor voltages. When compared to conventional parallel threelevel converters, the proposed converter has a lower power switch count. Finally, experiments with a 1.92
k
W prototype are provided to demonstrate the performance of the converter.
Acknowledgements
This project is supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022 MY3.
BIO
BorRen Lin received his B.S. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988, and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri, Columbia, MO, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings—Power Electronics and the Journal of Power Electronics. His current research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was a recipient of Research Excellence Awards in 2004, 2005, 2007 and 2011 from the College of Engineering and the National Yunlin University of Science and Technology. He received Best Paper Awards from the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, 2007 Taiwan Power Electronics Conference, 2009 IEEE–Power Electronics and Drive Systems Conference, the 2012 Taiwan Electric Power Engineering Conference, and the 2014 IEEEInternational Conference on Industrial Technology.
YanKang Du is currently working toward his M.S. degree in Electrical Engineering at the National Yunlin University of Science and Technology, Yunlin, Taiwan (ROC). His current research interests include the design and analysis of power factor correction techniques, switching mode power supplies and soft switching converters.
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