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Design of Parallel-Operated SEPIC Converters Using Coupled Inductor for Load-Sharing
Design of Parallel-Operated SEPIC Converters Using Coupled Inductor for Load-Sharing
Journal of Power Electronics. 2015. Mar, 15(2): 327-337
Copyright © 2015, The Korean Institute Of Power Electronics
  • Received : July 02, 2014
  • Accepted : October 28, 2014
  • Published : March 20, 2015
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About the Authors
Venkatanarayanan Subramanian
Department of Electrical and Electronics Engineering, K.L.N. College of Engineering, Sivagangai, India
venjeyeee@gmail.com
Saravanan Manimaran
Department of Electrical and Electronics Engineering, Thiagarajar College of Engineering, Madurai, India

Abstract
This study discusses the design of a parallel-operated DC-DC single-ended primary-inductor converter (SEPIC) for low-voltage application and current sharing with a constant output voltage. A coupled inductor is used for parallel-connected SEPIC topology. Generally, two separate inductors require different ripple currents, but a coupled inductor has the advantage of using the same ripple current. Furthermore, tightly coupled inductors require only half of the ripple current that separate inductors use. In this proposed work, tightly coupled inductors are used. These produce an output that is more efficient than that from separate inductors. Two SEPICs are also connected in parallel using the coupled inductors with a single common controller. An analog control circuit is designed to generate pulse width modulation (PWM) signals and to fulfill the closed-loop control function. A stable output current-sharing strategy is proposed in this system. An experimental setup is developed for a 18.5 V, 60 W parallel SEPIC (PSEPIC) converter, and the results are verified. Results indicate that the PSEPIC provides good response for the variation of input voltage and sudden change in load.
Keywords
I. I NTRODUCTION
The DC-DC converters that operate in parallel have several advantages, such as low component stress, good thermal management, more reliability, and less maintenance than single DC-DC converters. The single-ended primary-inductor Converter (SEPIC) is a DC-DC converter that possesses reduced output ripple, high efficiency, and high-voltage transfer gain. The minimum values of the equivalent inductance and capacitance are calculated. The Minimum Value of the Output Voltage Ripple and the switch peak current are calculated in Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode. The stress of the switching current and the design method were discussed to determine the equivalent inductance and capacitance of the SEPIC in [1] .
A stability property of the closed- loop control procedure was developed to design a globally asymptotical stabilizing linear proportional plus integral controllers for SEPIC in [2] . The optimization technique for a Proportional -IntegralDerivative (PID) controller to achieve Maximum-Power-Point Tracking of SEPIC was discussed. A weight function based on gradient descent method was developed to optimize the PID parameters by adding a low-pass filter term [3] . The operational analysis of an isolated time-sharing dual-input, single-ended primary-inductor was analyzed. A study demonstrated that active-clamping technique and zero-voltage switching can be achieved on the first-turned-on input leg, and the active-clamping leg with a proper driving strategy reduces component stress [4] .
The investigation of coupled-inductor SEPIC design issues focused on the correlation that exists among the sizes of the coupling capacitor and the magnetic coupling factor of coupled inductors. The voltage conversion ratio and amplitude of the peak-to-peak ripple current in the input and output ports of the coupled inductors were demonstrated [5] .Voltage multiplier and active-clamp techniques were applied to the conventional SEPIC converter to increase the voltage gain and reduce the voltage stresses of the power switches and diode [7] . The proposed converter utilizes a single controlled power switch and two inductors; it can provide high-voltage gain without an extreme switch duty cycle. The two inductors can be coupled into one core to reduce the input current ripple without affecting the basic DC characteristic of the converter. Moreover, voltage stresses across all the semiconductors are less than half of the output voltage [8] .
A Proportional Integral (PI) controller was designed to reduce the output current ripple for SEPIC, which demonstrates the possibility of eliminating the Electro Magnetic Interference (EMI) filter [9] . Non-isolated bidirectional soft-switching SEPIC/ZETA converter with reduced ripple currents was discussed. The SEPIC/ZETA explains that can be operated in the forward SEPIC and reverse ZETA modes with reduced ripple currents, and have increased voltage gains that are attributed to the optimized selection of duty ratios [10] .
The tightly coupled inductor structure only requires a single core for mutual inductance to force the ripple current into splitting equally between two coupled inductors [11] .
A high step-up DC-DC converter with a coupled-inductor and voltage-doubler circuits was discussed, and the converter achieved high step-up voltage gain with an appropriate duty ratio and low-voltage stress on the power switches. The energy stored in the leakage inductor of the coupled inductor can also be recycled to the output with the operating principles and the steady-state analyses of the converter in [12]
Considering all these facts, a coupled inductor is used in the present study, and a parallel operation of SEPIC with current sharing method is proposed. The PSEPIC is operating with CCM using a PI controller. First, a state-space model for a PSEPIC is derived, and then a PI controller is designed for control. The performance of the PI controller and the coupled inductor topology are assessed in terms of load-current sharing and stability, which are implemented in analog platform. This parallel-operated SEPIC with the coupled inductor design has numerous advantages, such as improved stability, robustness, and good dynamic response.
This paper is organized as follows: The basic operation of a SEPIC converter is presented in Section II. The design of the proposed PSEPIC converter is given in Section III. The simulation results of the proposed PSEPIC converter using a PI controller under a step-load change and step-input voltage-change conditions are discussed in Section IV. The experimental results of PSEPIC with the coupled inductor are revealed in Section V. The conclusion is discussed in Section VI.
II. SEPIC CONVERTER
SEPIC is a type of DC-DC converter that allows its output to be greater than, less than, or equal to the input voltage. The duty cycle of the control transistor controls the SEPIC output. The SEPIC circuit is presented in Fig. 1 . It consists of input supply, inductors L 1a , L 1b , switch S 1 , diode D 1 , capacitor C 1 , output capacitors C 2 , and resistor R. The SEPIC exchanges energy between the capacitors and inductors to convert from one voltage to another. Switch S 1 controls the amount of energy exchanged.
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Schematic of a SEPIC Converter.
Figs. 2 (a) and 2 (b) show the operational modes of the SEPIC. In Fig. 2 (a), the diode D 1 is reverse-biased and open, and the source voltage v i occupies the Inductor L 1a when the switch S 1 is closed. When switch S 1 is off, the current that passes through capacitor C 1 becomes the same as the current i L1a . Furthermore, we can conclude that power is delivered to the load from both L 2a and L 1a while S 1 is off. L 1 changes C 1 during this off mode, and will, in turn, recharge L 2 during the on mode, as shown in Fig. 2 (b).
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(a) SEPIC during Switch-On Mode. (b) SEPIC during Switch-Off Mode.
Fig. 3 . shows the circuit diagram of a SEPIC with a coupled inductor.
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SEPIC with a coupled inductor.
III. DESIGNING OF PROPOSED PSEPIC CONVERTER
A parallel connection of a SEPIC converter is a reliable and efficient way to increase the power rating of the SEPIC module, which removes the limit of the current ceiling of power semiconductor switches. PSEPIC is a viable alternative method to satisfy the power requirement, which can be more than the capacity of the large single SEPIC module.
PSEPIC requires a current-sharing mechanism to ensure proper operation. Various methods can be used to obtain load-current sharing, such as average current sharing, master– slave scheme, democratic current sharing, and autonomous master–slave scheme. In this study, a simple PI controller is used to force the output voltage of the PSEPIC into following the voltage reference. The main benefits of this PSEPIC are robustness, stability of output voltage, lower component count, and lower inductor value compared with operating two SEPIC converters with separate inductors.
Conventional SEPIC possesses two inductors, L 1a and L 2a . Therefore, this tool requires a large space in the printed circuit board. The tightly coupled inductors are inside a single package when used in the proposed PSEPIC, which provides not only compactness, but also uses the same ripple current. Half of the inductor value that the separate inductors have can be used because the proposed PSEPIC is a coupled inductor. Fig. 4 . shows the block diagram of the proposed PSEPIC.
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Block diagram of the proposed PSEPIC.
The designed PSEPIC works in a cycle with a small off-mode to avoid EMI. Only one SEPIC operates for a low load. If the load exceeds more than 50% of the load current, then the other SEPIC shares the load current. Hence, less circuit losses occur and the components experience no stress. Identical components are used for both SEPIC converters. A switch control circuit drives PSEPIC. Initially, SEPIC-I is switched on to receive the load current when the load is exceeded. SEPIC-II is then switched on to share the load, with a 10% delay of the switching period to avoid EMI and overloading.
- A. Selection of Component Ratings
The design of various components in the circuit is shown in Fig. 1 and is explained in this section. A coupled inductor involves a simultaneous parallel energy pathway and works as an energy storage element for ripple-current steering. Fig. 5 . shows the coupled inductor. The voltage across the inductor L 1 is considered as V 1 , and the voltage across L 2 is considered as V 2 . The current that passes through the inductors L 1 and L 2 are considered as i 1 and i 2 respectively. Mutual inductance also has a relationship with the coupling coefficient, which is between 1 and 0, as given in Eq. (1).
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Coupled inductor.
where M is the mutual inductance, k is the coupling coefficient, and L 1 and L 2 are self-inductance.
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The proposed PSEPIC works similarly with separate inductors and coupled inductors. For the circuit to operate properly, a volt-microsecond balance must be maintained across each magnetic core. In other words, the products of each inductor voltage and time must be equal in magnitude and opposite in polarity during the MOSFET ON and OFF times for the two separate inductors. However, the coupled inductor can manage without such problems. The capacitor voltage for separate inductors is also charged to the input voltage, which can be algebraically shown. A coupled inductor is preferred for the proposed PSEPIC because of its reduced component count, better integration, and less inductance requirement compared with using two single inductors. A coupled inductor PSEPIC can benefit from leakage inductance, which reduces current losses. The selected coupled inductors have a 1:1 turn ratio for volt-microsecond balance.
The developed PSEPIC converter with a coupled inductor has many advantages compared with a separate single inductor, as seen in Table I .
COMPARISON OF COUPLEDAND SINGLE INDUCTOR-BASED PSEPIC
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COMPARISON OF COUPLEDAND SINGLE INDUCTOR-BASED PSEPIC
- B. Duty Cycle Consideration
The duty cycle of the proposed PSEPIC is shown in Fig. 6 . In the figure, Is 1 and Is 2 represent the current that passes through the switches SEPIC-I and SEPIC-II respectively. The efficiency of the SEPIC should be maximized. The proposed PSEPIC operates on CCM, and the duty cycle of switch D is given in Eq. (4).
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Duty cycle.
where VD is the forward voltage drop of the Schottky diode. In PSEPIC, the ratio between input current ii and output current io is given in Eq. (6):
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- C. Inductor Ripple Current
One of the first steps in designing any PWM-switching regulator is to determine the inductor ripple current ∆ iL , which can be obtained using Eq. (7). Normally, 20% to 40% of the input current is accepted as the ripple current. In this study, the ripple current is 30%.
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where η is the efficiency of the PSEPIC, which is 90%, and i1 is the accurate estimate of the input current. In ideal cases, a tightly coupled inductor that has single cores with the same number of windings for each conductor, and the mutual inductance forces the ripple current to split equally between two coupled inductors. The design of the inductor value is determined to be half of what will be required for two separate inductors, and is given as Eq. (8):
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where L 1a and L 1b are the inductance of the coupled inductors, Vi (min) is the minimum input voltage, D (max) is the maximum duty cycle, and fs is the switching frequency. When load changes are considered, the saturation current rating of the tightly coupled inductor must be 20% higher than the steady-state peak current in the input of inductor i L1a(peak) and is calculated as in Eq. (9):
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The capacitor C 2 must be able to provide the load current and have sufficient capacitance with a low Equivalent Series Resistance (ESR). C 2 is selected based on Eq. (10):
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where ∆ V(c)ripple is the ripple voltage of the capacitor C 2 . Furthermore, ESR can be ignored. Low ESR capacitors are used, and the value of capacitor C 2 can be calculated using Eq. (11).
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The output capacitor must have a Root Mean Square (RMS) current rating that is more than the output RMS current, which is given in Eq. (12).
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The coupling capacitor C 1 obtains a large RMS current that is related to the output power and is given in Eq. (13).
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The maximum voltage across coupling capacitor C 1 is given in Eq. (14):
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The ripple voltage across C 1 can be calculated using Eq. (15):
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- D. MOSFET Selection
MOSFET ( S 1 ) is the main active component and must be selected in such a way that it can handle the peak voltage and the current with low loss in the circuit. The peak current rating of switch S 1 is given in Eq. (16):
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Table II shows the parameters of the designed PSEPIC.
PARAMETERS OF PSEPIC
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PARAMETERS OF PSEPIC
IV. SIMULATION
The purpose of this section is to discuss the simulation of the PSEPIC with a PI controller. A PI controller with a Kp setting of 0.1205 and a Ti of 0.00016 s is obtained using the Ziegler–Nichols tuning technique. These results are used for the design of the PSEPIC feedback controller. The developed circuit performance is verified with different conditions, such as startup, line variation, load variation, and steady-state condition.
Simulations are performed using the listed parameters, as shown in Table II . The simulated results of the output voltage and the current without a PI controller for each module are listed in Tables III and IV respectively. The voltage regulation and current distribution have some equalities. Fig. 7 . shows the simulink diagram of PSEPIC with separate inductors, and Fig. 8 shows the coupled inductor-based PSEPIC.
SIMULATED RESULT OF OUTPUT VOLTAGE OF PSEPIC WITHOUT CONTROLLER
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SIMULATED RESULT OF OUTPUT VOLTAGE OF PSEPIC WITHOUT CONTROLLER
SIMULATED RESULT OF OUTPUT CURRENT OF PSEPIC WITHOUT CONTROLLER
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SIMULATED RESULT OF OUTPUT CURRENT OF PSEPIC WITHOUT CONTROLLER
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Simulink diagram with separate inductor PSEPIC.
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Simulink diagram of the Proposed PSEPIC.
The performance of the proposed PSEPIC with a PI controller that was obtained through simulation is analyzed and verified as follows.
- A. Startup Transient
Fig. 9 shows the startup behavior of the PSEPIC output voltage for different input voltages viz 15, 18.5, and 24 V, in which the reference value of the input voltage is set to 18.5 V and the load resistance is 6 Ω. The output voltage has no overshoot, and the settling time is 0.25 s. Fig. 10 . shows the output current of PSEPIC for the same set of reference output voltages and load resistance values.
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Response of the PSEPIC output voltage at various input voltages at startup.
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Response of the PSEPIC output current at various input voltages at startup.
Fig. 11 shows the startup response of the PSEPIC output voltage for the different load resistances of 4, 6, and 8 Ω, and the reference output voltage of 18.5 V. Irrespective of the variation of load resistance, the output voltages remain constant at 18.5 V. The input voltage is kept at 15 V during the above simulation. Fig. 12 shows the PSEPIC output current for the different load resistances of 4, 6, and 8 Ω using a PI controller. The output voltage is constant at 18.5 V for all three loads, and the currents are 4.625, 3.08, and 2.312 A, respectively.
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Response of the PSEPIC output voltage during startup for various load resistances.
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Response of the PSEPIC output voltage during startup for various load resistances.
- B. Step Change in Load
Fig. 13 shows the response of the PSEPIC output voltage when the load is forced to step change from 6 Ω to 4 Ω (-33% load variation) at time t = 0.4 s. The output voltage of PSEPIC has a small overshoot of 1.2 V with a settling time of 0.05 s. Fig. 14 shows that the response of the PSEPIC output voltage for a load step changes from 6 Ω to 8 Ω (+33% load variation) at time t = 0.4 s. The output voltage of the PSEPIC also has the maximum over shoot of 1.5 V with the settling time of 0.05 s. Figs. 13 and 14 show that the simulated output of the designed PSEPIC exhibits good performance on load disturbances.
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Response of output voltage when the load changes from 6 Ω to 4 Ω.
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Response of output voltage when load changes from 6 Ω to 8 Ω.
- C. Steady-State Condition
Figs. 15 and 16 show the steady-state output voltage and output current of the PSEPIC when Vi = 15 V and load resistance R = 6 Ω. Steady-state variation of the voltage is 0.015 V, which is a good constant voltage requirement. The output voltage ripple is low at approximately 0.015 V (0.083%), and the peak-to-peak ripple current is 0.002 A.
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Response of PSEPIC output voltage at the steady-state condition.
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Response of PSEPIC output voltage at the steady-state condition.
In summary, Figs. 9 16 show that the PSEPIC results have good performance.
V. EXPERIMENTAL RESULTS
The purpose of this section is to discuss the experimental results of the proposed PSEPIC with a PI controller. The validation is done with different conditions viz line variation, load variation, and steady-state operation.
The experimental setup of the PSEPIC with coupled inductors is developed with the same specifications as the simulation. This setup is shown in Fig. 17 . The parameters of the main circuit and components of the control circuits are given in Tables V and VI . A photograph of the PSEPIC experimental setup is shown in Fig. 18 .
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Experimental circuit of PSEPIC.
PARAMETERS OF MAIN CIRCUIT
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PARAMETERS OF MAIN CIRCUIT
LIST OF CONTROL CIRCUIT COMPONENTS
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LIST OF CONTROL CIRCUIT COMPONENTS
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Experimental setup of PSEPIC.
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Response of PSEPIC pulse.
- A. Operation of the Circuit
The purpose of PSEPIC is to share the load and consider the maximum duty cycle. Generally, duty cycle D with time Ts is accepted as t 1 and t 2 , as shown Fig. 6 . The proposed PSEPIC shares the 30% ON in SEPIC-I and 30% ON in SEPIC-II. Hence, the maximum tapping of energy from the supply is derived.
Only a simple PI controller is used in this work. The PSEPIC gate is given separate pulses with a small time delay using IC KA3525, which operates and controls the PSEPIC with the individual gate voltage from pin numbers 11 and 14. A reference voltage of 18.5 V is given to pin 1, and a fraction of the PSEPIC output voltage is given to KA3525. According to the error between the above two voltages, the gate pulse width will be adjusted to maintain the output voltage at a constant value. When the output voltage of PSEPIC either exceeds 24 V or goes below 15 V, the comparator LM324 sends a shutdown signal to pin 10 of KA3525. Thus, the gate pulses are cut off. Using this simple controller, the duty cycle of the gate pulse is varied to regulate the output voltages, which improves the dynamic performance of PSEPIC. The performance of the PSEPIC obtained from the experiment is analyzed in the following section.
- B. Line Variation
Fig. 20 shows the experimental response of the output voltage of the PSEPIC when there is an input voltage change from 15 V to 18.5 V at time t = 0.4 s. The reference value of the output voltage is set to 18.5 V. The load resistance value is kept at 6 Ω. The experimental response demonstrates that the average output voltage of the PSEPIC has a maximum undershoot of 1.96 V and a settling time of 0.05 s.
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Response of output voltage on line variation when the input voltage suddenly changes from 15 V to 18.5 V.
Fig. 21 shows the experimental response of the average PSEPIC output voltage when an input voltage step changes from 24 V to 18.5 V at time 0.4 s. The experimental response demonstrates that the output voltage of the PSEPIC has a maximum undershoot of 1.96 V and a settling time of 0.05 s.
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Response of output voltage on line variation when input voltage suddenly changes from 24 V to 18.5 V.
- C. Load Variation
Fig. 22 shows the response of PSEPIC output voltage when the load is forced to step change from 6 Ω to 4 Ω (-33% load variation) at time t = 0.4 s. The output voltage of PSEPIC has a small overshoot of 2 V with a settling time of 0.06 s. Fig. 23 shows the response of the PSEPIC output voltage for a load that step changes from 6 Ω to 8 Ω (+33% load variation) at time t = 0.4 s. Furthermore, the output voltage of the PSEPIC has a maximum overshoot of 3 V with a settling time of 0.06 s. Figs. 22 and 23 show that the experimental output of the designed PSEPIC exhibits good performance on load disturbances.
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Response of output voltage on load variation when the load suddenly changes from 6 Ω to 4 Ω.
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Response of output voltage on load variation when the load suddenly changes from 6 Ω to 8 Ω.
- D. Steady-State Region
Figs. 24 , 25 , and 26 show the experimental output voltage of the PSEPIC in the steady-state region for Vi = 15 V, 18.5 V, and 24 V, respectively. The reference value of Vo is kept at 18.5 V. The output voltage is kept constant for all three inputs.
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Response of PSEPIC on output voltage for the input voltage of 15 V.
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Response of PSEPIC on output voltage for the input voltage of 18.5 V.
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Response of PSEPIC on output voltage for the input voltage of 24 V.
Table VI shows the comparison of simulation and experimental results when the input voltage is at 15, 18.5, and 24 V. The PSEPIC circuit is stable and produces 18.5 V. In the simulation and the experimental setup, the output voltage is kept constant at 18.5 V. Thus, the results are close to the experimental and simulated values.
In cases of various loads, the PSEPIC response is to maintain its output voltage and share the load current. In Table VII , the output currents and voltages of the simulation and experimental setup have the nearest values.
EXPERIMENTAL AND SIMULATED VALUES OF CHANGE IN INPUT VOLTAGE AND CURRENT
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EXPERIMENTAL AND SIMULATED VALUES OF CHANGE IN INPUT VOLTAGE AND CURRENT
In summary, Figs. 19 - 26 indicate that the experimental results of the PSEPIC agree with the simulated results with a tolerance of ±2%. The proposed coupled inductor with simple PI controller also performs well in all operational situations of the PSEPIC. The novelty of the circuit is its use of a coupled inductor with a simple PI controller. The PI controller provides the gate pulse for both the switches in PSEPIC with time delay. Another advantage is the ON and OFF time. Therefore, the proposed PSEPIC is considered to share only when the load is exceeded by more than half; otherwise, one SEPIC will operate. This characteristic is the uniqueness of this novel technique.
VI. CONCLUSION
Considering its advantages of load sharing, maintaining constant voltage, reducing the footprint of components, component counts, and stress on components, the parallel-connected SEPIC converter for low-voltage applications is developed. A coupled inductor is used for this PSEPIC because single and separate inductors utilize considerable ripple currents. As a result, this coupled inductor utilizes only half of the ripple current that two separate inductors use. PSEPIC is verified under various conditions, such as startup transient, load variation, line variation, and steady-state condition to maintain a constant voltage and load sharing. An analog control circuit is designed to generate PWM signals to fulfill the closed-loop control function. A stable output voltage is kept constant at 18.5 V with a common input voltage. The proposed PSEPIC shares the load current according to the load conditions. The experimental setup is developed for an 18.5 V 60 W PSEPIC, and the results are verified. The results show evidence that the proposed PSEPIC provides good response for line variation and shares the load current. This PSEPIC also withstands sudden changes in load.
BIO
Venkatanarayanan Subramanian was born in Madurai, India. He received his BE in Madurai Kamaraj University in 1998, and his ME in Anna University in 2008. He is currently an Associate Professor in the Department of Electrical and Electronics Engineering, K.L.N. College of Engineering, Sivagangai, India where he is engaged in research on SEPIC. His current research interests are power electronics and control.
Saravanan Manimaran was born in Madurai, India. He received his BE in Madurai Kamaraj University in 1991 and his ME in the 1992 from Bharathiyar University. He received his PhD from Madurai Kamaraj University in 2007. Presently, he is working as a Professor of EEE at Thiagarajar College of Engineering, Madurai, India. His research interests are power electronics and control.
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