This study proposes a dualoutput singlestage bridgeless singleended primaryinductor converter (DOSSBS) that can completely remove the frontend fullbridge alternating current–direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multistage configurations in a single stage. Therefore, this proposed converter is costeffective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either highfrequency pulsewidth modulation pattern or lowfrequency rectifying mode for switching loss reduction. A prototype for dealing with an 85265 V
_{rms}
universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.
I. INTRODUCTION
The topologies of power factor corrector (PFC) generally contain buck, boost, buck–boost, Zeta, ‘Cuk, singleended primaryinductor converter (SEPIC), and flyback. Buck PFC can decrease the input voltage to obtain an output voltage less than the peak value of the line voltage
[1]
. However, zerocrossing distortion degrades power factor. On the contrary, boost PFC can achieve a unity power factor, but its output voltage is higher than its input. Boost PFC cannot deal with the applications of low output voltage, unless it embeds a stepdown direct current (dc)/dc stage. Another disadvantage of boost PFC is that power components withstand highvoltage stresses
[2]
,
[3]
. Buck–boost can obtain an output voltage whose magnitude is either larger or smaller than the input. Nevertheless, the polarity reversal on output and isolated driving requirement will become potential problems
[4]
. Similar to buck–boost, ‘Cuk and Zeta have the feature of stepping up or down input voltage. However, pulsating input current and highside driving are required for Zeta, while ‘Cuk still has the polarity reversal problem
[5]

[7]
. Flyback PFC can resolve the polarity reversal problem and possesses the characteristic of galvanic isolation, but it has the significant drawback of low efficiency
[8]

[13]
. Compared with the aforementioned stepup/stepdown PFCs, the SEPIC type performs better in total harmonic distortion (THD), efficiency, and power factor
[14]

[16]
.
To reduce component count and improve efficiency, a bridgeless structure attracts a great deal of interest in fulfilling power factor correction. Although high efficiency can be achieved in typical bridgeless PFC topologies derived from boost, buck, or buckboost
[17]

[20]
, the aforementioned drawbacks still exist. Some researchers have proposed a bridgeless PFC with respect to SEPIC configuration
[21]

[23]
; however, two diodes are needed to accomplish rectification. Given that the two diodes have to block a voltage higher than the mains, the problems of large cutin voltage and reverse recovery losses remain. In literature
[24]
, the frontend alternating currentdc bridge rectifier is completely done away with, but the stepdown property is lost.
To overcome all the mentioned drawbacks, a novel dualoutput singlestage bridgeless SEPIC (DOSSBS) with power factor correction is proposed (
Fig. 1
). Unlike the conventional PFC, the proposed DOSSBS can complete power factor correction without the need for a frontend bridge rectifier, which therefore simplifies converter structure, avoids the problem of power loss on rectifier diode, and decreases component count. DOSSBS is distinguished by the features of single stage, bridgeless, and high efficiency. It can also provide dual individual outputs in a single stage. A 100 W universal line input prototype is built and examined for verification. Experimental results validate the proposed DOSSBS.
Main power circuit of the proposed DOSSBS.
With respect to practical applications, the proposed DOSSBS can serve as a power supply with power factor correction to drive electric appliances, which need two different levels of source voltage. DOSSBS can power appliances in a single converter, instead of two separate converters, thereby yielding high energy conversion efficiency and low cost. For example, in an intelligent lighting system application, DOSSBS can simultaneously drive lightemitting diodes and provide power for the dimming circuits of the communication interface.
The remainder of this paper is organized as follows. Section II describes the operation principle of the proposed DOSSBS. Section III deals with the design considerations of the converter. Section IV provides practical measurements and a performance comparison with other PFCs. Finally, Section V concludes.
II. OPERATION PRINCIPLE
For the operation description of the proposed DOSSBS, the definitions of current direction and voltage polarity are given in
Fig. 2
. The two active switches alternately operate at a high frequency within an interval of line cycle. During the positive halfline cycle,
SW_{1}
is always closed, and
SW_{2}
operates at a high frequency. During the negative halfline cycle,
SW_{1}
switches in a high frequency, while
SW_{1}
is kept in onstate. As the highfrequency switching pattern is not in constant use, the switching loss of the proposed converter can be significantly reduced.
Representation of voltage polarity and current direction of the proposed converter.
The operation of the converter can be divided into four main modes over one switching period.
Figs. 3
and
4
show the corresponding equivalents and conceptual key waveforms when the converter is operated in the positive half cycle respectively. The corresponding modeequivalents and conceptual key waveforms in the negative cycle are illustrated in
Figs. 5
and
6
. The converter operation in the positive half cycle is discussed mode by mode below.
Equivalents during one switching period in the positive halfline cycle. (a) Mode 1, (b) Mode 2, (c) Mode 3, and (d) Mode 4.
Conceptual waveforms corresponding to the operation modes in the positive halfline cycle.
Equivalents during one switching period in the negative halfline cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4.
Conceptual waveforms corresponding to the operation modes in the negative half cycle.
Mode 1
[Fig. 3(a), t_{0}t_{1}]:
Over the entire positive halfline cycle,
SW_{1}
is always in onstate, while
SW_{2}
is operated in a high switching frequency to control input current.
SW_{2}
is turned on at the beginning of mode 1. In mode 1, input voltage is directly connected to the input inductor
L_{1}
. The current
i_{L1}
is linearly built, and the capacitor
C_{2}
dumps energy to the primary of the coupled inductor through
SW_{2}
and
D_{3}
. Meanwhile, the capacitor
C_{o2}
supplies energy for the load
R_{L2}
, and the capacitor
C_{o1}
for the load
R_{L1}
. The voltage across the inductor
L_{1}
is given by
where
v_{s}
(
t
) represents the line voltage, and
V_{DS1,on}
and
V_{DS2,on}
stand for the voltage drop on
SW_{1}
and
SW_{2}
respectively. Supposing that the line voltage is purely sinusoidal and equal to
V_{m}sin
(
2pf_{line}t
), the above equation becomes
where
V_{m}
is the amplitude of line voltage, and
f_{line}
denotes the line frequency. The onstate voltage
V_{DS1,on}
in Eq. (2) is less than the forward voltage of a rectifier diode. Compared with traditional fullbridge PFCs, the proposed DOSSBS replaces an active switch with two lowfrequency rectifier diodes, such that it can significantly decrease conduction loss. The inductor current
i_{L1}
can be determined as follows:
Under the boundary mode operation, given that the initial value of the inductor current
i_{L1}
(0) is zero, the converter can achieve zero current switching feature at
SW_{2}
.
In mode 1, the capacitor
C_{2}
discharges to the primary magnetizing inductance
L_{m,pri}
and the primary leakage inductance
L_{lk,pri}
of the coupled inductor. The current
i_{D3}
can be calculated by
where
v_{C2}
(
t
) stands for the voltage across the capacitor
C_{2}
,
V_{D3,f}
means the forward voltage of the diode
D_{3}
, and
L_{pri}
denotes the measured inductance with respect to the input terminals of the coupled inductor while the secondary is open.
L_{pri}
is the sum of
L_{m,pri}
and
L_{lk,pri}
.
Mode 2
[Fig. 3(b), t_{1}t_{2}]:
his mode begins as soon as
SW_{2}
is turned off. In mode 2, the energy stored in the inductors
L_{1}
,
L_{m,pri}
, and
L_{lk,pri}
continues to increase. The voltage across the parasitic capacitor of
SW_{2}
also increases, but the capacitors
C_{o1}
and
C_{o2}
still dump energy to the loads
R_{L1}
and
R_{L2}
respectively. The voltage across
SW_{2}
can be expressed as
The voltage
v_{DS2}
continuously increases during mode 2. At the moment that
v_{DS2}
reaches the magnitude of input voltage, this mode ends, and the polarities of the inductors
L_{1}
,
L_{m,pri}
, and
L_{lk,pri}
reverse. All the inductors start discharging.
Mode 3
[Fig. 3(c), t_{2}t_{3}]:
During this mode, the inductor
L_{1}
releases energy to the capacitors
C_{2}
and
C_{o2}
, and the energy stored in the leakage inductance
L_{lk,pri}
will be recycled to the output through
L_{m,pri}
,
D_{2}
, and
D_{3}
.
L_{m,pr}
dumps energy to
C_{o2}
and
C_{o1}
.
From the equivalent circuit of mode 3, the voltage across the parasitic capacitor of
SW_{2}
is clamped at
v_{c2}
+
V_{o2}
. Thus, the voltage stress of
SW_{2}
,
V_{stress}
, and
_{SW2}
, can be determined as follows:
The inductor current
i_{L1}
can be obtained by
where
i_{L1}
(
t_{2}
) is the initial value of
i_{L1}
at
t
=
t_{2}
, and
V_{D2,f}
is the voltage drop on the diode
D_{2}
. This mode ends when the current of the leakage inductance
L_{lk,pri}
drops to zero.
Mode 4
[Fig. 3(d), t_{3}t_{4}]:
In mode 4, the inductor
L_{1}
continues supplying energy to the capacitors
C_{2}
and
C_{o2}
, while the coupled inductor transmits energy to
C_{o1}
. The current flowing through
L_{m,pri}
linearly decreases, which can be estimated by
In the negative halfline cycle, the roles of
SW_{1}
and
SW_{2}
exchange.
SW_{1}
is operated in high frequency to control input current, while
SW_{2}
is kept in onstate over the entire half cycle. The operation of the proposed converter is symmetrical in two halfline cycles of input voltage. The description of operation in the negative halfline cycle is similar to that in the positive which also has four modes. The equivalent circuits and conceptual waveforms are illustrated in
Figs. 5
and
6
, respectively.
III. DESIGN CONSIDERATIONS
 A. Equivalent Iron Loss Resistance
1) V_{o1} = V_{o2} :
Minimum switching frequency
f_{sw,min}
is a key parameter for the design of the input inductor
L_{1}
. Switching frequency can be estimated by determining the ontime and offtime periods of the active switch. As power factor correction is performed under a constant ontime switching pattern,
f_{sw,min}
can be obtained after determining the maximum off time. However, a low line input voltage indicates a high ontime interval. Thus, maximum on time
T_{on,max}
and maximum off time
T_{off,max}
over the range of universal line input should be determined in advance for
f_{sw,min}
calculation.
Supposing that the range of universal line input is from
V_{rms,min}
to
V_{rms,max}
,
T_{on,max}
then occurs when the line voltage is
V_{rms,min}
. Given that output power is equal to the multiplication of input power and converter efficiency, the following equation holds:
where
η
denotes the converter efficiency, and
P_{o}
is the output power. Over a halfline cycle, the maximum off time
T_{off,max}
appears at the peak of the sinusoidal line voltage. Accordingly, if the two output voltages of the converter are equal,
V_{o1}
=
V_{o2}
=
V_{o}
, then
From Eqs. (9) and (10), solving
T_{on,max}
and
T_{off,max}
obtains
and
The minimum switching frequency is calculated by
Substituting Eqs. (11) and (12) into Eq. (13), we obtain
To determine the value of the input inductor
L_{1}
, Eq. (14) can be rewritten as
Supposing that
η
= 0.93, then two output voltages are equal, and the minimum line input voltage is 85 V
_{rms}
.
Fig. 7
shows the relationship among input inductance, power rating, and output voltage. High power rating requires low input inductance; under a certain power rating, a high output voltage needs large input inductance. Considering that a small input inductance will result in a high switching frequency, the minimum switching frequency should be larger than 20 kHz to avoid audio frequency.
Relationship between input inductance and output power under different output voltages.
2) V_{o1} ≠ V_{o2} :
The determination of input inductance in Eq. (15) is only suitable for the condition
V_{o1}
=
V_{o2}
. If
V_{o1}
≠
V_{o2}
, then the minimum switch frequencies of
SW_{1}
and
SW_{2}
will differ. Therefore, two values will be elected as input inductance and are expressed as
and
f_{sw1,min}
and
f_{sw2,min}
denote the minimum switching frequencies of
SW_{1}
and
SW_{2}
respectively. The smaller one between
L_{α}
and
L_{β}
is chosen as the input inductance, that is,
The converter power rating is 100 W, and the minimum line voltage is 85 V
_{rms}
.
Fig. 8
illustrates the relationship among two output voltages and the minimum switching frequencies of
SW_{1}
and
SW_{2}
.
f_{SW1,min}
will be larger than
f_{SW2,min}
when
V_{o1}
>
V_{o2}
. On the contrary,
f_{SW1,min}
is less than
f_{SW2,min}
when
V_{o1}
<
V_{o2}
. If
V_{o1}
=
V_{o2}
, both switching frequencies are identical.
Relationship among the minimum switching frequencies of SW_{1} and SW_{2} and dual output voltages.
f_{SW1,min}
and
f_{SW2,min}
vary with input line voltage and output power. For example,
η
= 0.93,
V_{o1}
= 30 V,
V_{o2}
= 60 V, and input inductance
L_{1}
= 670 μH.
Fig. 9
shows the relationship among the minimum switching frequencies of the two active switches, input voltage, and output power.
Relationship between minimum switching frequency and input voltage under different output powers.
 B. Design of the Coupled Inductance
The coupling coefficient of a coupled inductor can be evaluated as follows:
Rearranging Eq. (19) yields
When the inductance
L_{sec}
is in the output terminals while the primary is open,
where
L_{lk,sec}
is the leakage inductance of the secondary. The relationship between
L_{lk,pri}
and
L_{lk,sec}
is given by
The magnetizing inductance in the secondary
L_{m,sec}
also equals the primary magnetizing inductance
L_{m,pri}
times the square of turn ratio. The following relationship is then derived:
The terminal voltage of the secondary,
V_{Lsec}
, can be computed by
where
V_{Lm,pri}
is the voltage across the magnetizing inductance of the primary. Given that
k
is less than unity, the following inequality holds:
Thus, the design for the coupled inductor should meet the following inequality:
 C. Coupled Capacitance
The energytransferred capacitors
C_{1}
and
C_{2}
are also key components because their values significantly influence input line current. Both capacitors must be in a proper design for their steadystate voltage waveforms to be consistent with the rectified input line voltage, and the lowfrequency oscillating with input inductor or coupled inductor can be avoided. In practical consideration, resonant frequency should be larger than line frequency but less than minimum switching frequency, that is,
and
where
f_{r1}
and
f_{r2}
are the resonant frequencies of
L_{1}

C_{2}

L_{pri}
and
L_{1}

C_{1}

L_{sec}
respectively. They are calculated as
and
According to Eqs. (29) and (30), the capacitances of
C_{1}
and
C_{2}
can be calculated by
and
respectively.
 D. Output Capacitance
The frequency of output ripple is twice the line frequency. A low output voltage ripple is accompanied by a large output capacitance. Once the output voltage ripple △
V_{o}
is specified, the corresponding output capacitance
C_{o}
can be estimated by
 E. Switch Stress
In this converter, the voltage stress across active switch can be estimated by the peak value of the uppermost universal line voltage
V_{pk,max}
plus output voltage. Therefore,
and
IV. EXPERIMENTAL RESULTS
A prototype is built, simulated, and examined to verify the feasibility of the proposed DOSSBS. In the prototype, the universal line input voltage is over the range of 85265 V
_{rms}
, the line frequency is 60 Hz, the output voltage of ports 1 and 2 are 30 and 60 V respectively, that of port 2 is 60 V, and the converter power rating is 100 W. The key component values are summarized in
Table I
.
KEY COMPONENTS AND VALUES OF THE PROTOTYPE
KEY COMPONENTS AND VALUES OF THE PROTOTYPE
Fig. 10
shows the measured waveforms of the line voltage
v_{s}
and the input inductor current
i_{L1}
at full load when the line voltage is 110 V
_{rms}
. The envelope of
i_{L1}
in
Fig. 10
is sinusoidal and can be in phase with the line voltage. In the positive halfline cycle,
SW_{2}
is operated at a high frequency, but
SW_{1}
is always in onstate.
Fig. 11
shows the zoomedin waveforms in the positive halfline cycle. The control signal of
SW_{2}
is in a high frequency, and the input inductor current is controlled at a boundary conduction manner. The filtered source current
i_{in}
is shown in
Fig. 12
, which illustrates that
i_{in}
is sinusoidal and in phase with the line voltage.
Fig. 13
shows the two output voltages at ports 1 and 2 to demonstrate that both ports can be kept constant at 30 and 60 V under full load.
Figs. 14
and
15
present the corresponding waveforms of the stepchange transient response of DOSSBS, while the output power at port 1 changes from light to heavy load and from heavy to light load respectively. Both figures indicate that even under stepchange loading, DOSSBS still can still feature rapid transient response and sustain stable output voltages. The waveforms of
v_{C1}
and
v_{C2}
are presented in
Fig. 16
, which depicts that the positive voltages of
v_{C1}
and
v_{C2}
are sinusoidal, and the maximum negative voltages equal the output voltages of ports 1 and 2.
Fig. 17
presents the voltages across the diodes
D_{1}
and
D_{2}
when the line voltage
v_{s}
increases to 90 V. The blocking voltage of
D_{2}
is equal to
v_{C2}
plus output voltage at port 2, at approximately 150 V. Under the same input voltage of 90 V, the measured waveforms of
v_{D3}
and
v_{D4}
are shown in
Fig. 18
. The reversed voltage across
D_{4}
is approximately 75 V. The result of harmonic measurement is shown in
Fig. 19
, which expresses that DOSSBS can meet the standard of IEC 6100032 Class C. The measured THD is 14.8%.
Fig. 20
shows the measured power factor over the range of universal line input at full load, in which the maximum power factor approaches unity.
Figs. 21
and
22
illustrate the prototype efficiency.
Fig. 21
shows the efficiency curve from 4 W to 100 W, while line voltage is 110 V
_{rms}
. The figure also demonstrates that DOSSBS can achieve the highest efficiency among the converters of conventional fullbridge SEPIC PFC, bridgeless SEPIC PFC, and bridgeless nonSEPIC PFC. The maximum efficiency of the prototype is up to 95% at approximately 60 W. Efficiency measurement over the entire range of universal line input under full load is presented in
Fig. 22
, in which the efficiencies at 110 and 220 V
_{rms}
are 93.5% and 95.7% respectively. A comparison with other types of singlestage PFC is summarized in
Table II
. The proposed converter does not require lowspeed diode and dualoutput topology.
Measured waveforms of the line voltage v_{s} and the input inductor current i_{L1} at full load.
Zoomedin waveforms of input inductor current and associated control signal in the positive halfline cycle.
Measured waveforms of line voltage and filtered source current.
Measured waveforms of output voltages at ports 1 and 2.
Related waveforms while the output power of port 1 changes from light to heavy load.
Related waveforms while the output power of port 1 changes from heavy to light load.
Measured waveforms of v_{C1} and v_{C2}.
Measured waveforms of v_{D1} and v_{D2}.
Measured waveforms of v_{D3} and v_{D4}.
Measured result of current harmonics.
Measured power factor over the range of universal line input at full load.
Efficiency measurement from light to full load while line voltage is 110 V_{rms}.
Efficiency measurement over the range of universal line input from 85 V_{rms} to 265 V_{rms}.
COMPARISON AMONG THE PROPOSED CONVERTER AND OTHER TYPES OF SINGLE STAGE PFC
COMPARISON AMONG THE PROPOSED CONVERTER AND OTHER TYPES OF SINGLE STAGE PFC
V. CONCLUSION
This study proposes DOSSBS PFC, which can deal with a wide range of input of 85265 V
_{rms}
of universal line and provide dual outputs. In the proposed converter, the frontend rectifier is completely removed, thereby simplifying configuration, decreasing component count, and reducing conduction losses. A coupled inductor is incorporated to replace two separate inductors and thus reduce converter volume, as well as recycle the energy stored in leakage inductance. Practical measurements validate the proposed DOSSBS, whose configuration can be expanded for multipleoutput applications.
Fig. 23
shows the main power schematics, in which the inductors of all the additional output ports can be coupled with
L_{pri}
and
L_{sec}
.
Main circuit schematic of the expanded configuration of the proposed converter.
BIO
ChihLung Shen was born in Tainan, Taiwan, R.O.C. in 1962. He received his B.S. degree from National Taiwan University of Science and Technology, Taipei, Taiwan in 1988; his M.S. degree from National TsingHua University, Hsinchu, Taiwan in 1991; and his Ph.D. degree from National Chung Cheng University, ChiaYi, Taiwan, R.O.C. in 2003, all in electrical engineering. He is currently with the Department of Electronic Engineering, National Kaohsiung First University of Science and Technology (NKFUST), Kaohsiung, Taiwan, where he is a full professor, the department director of Electronic Engineering, and the director of the Photovoltaics Technology Research Center. His research interests include electric ignition system, photovoltaicpowered systems, active power filters, and power converter design.
ShihHsueh Yang was born in Kaohsiung, Taiwan in February 1989. He received his B.S. degree in Undergraduate Honors Program of Engineering in 2011 and his M.S. degree in Industrial Technology Master Program on Green Energy and IC Design in 2013 from NKFUST. His research interests include power conversion dc/dc, ac/dc PFC converters, dc/ac inverters, and analog IC design.
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