This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current–direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an 85-265 V _rms universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter. The topologies of power factor corrector (PFC) generally contain buck, boost, buck–boost, Zeta, ‘Cuk, single-ended primary-inductor converter (SEPIC), and flyback. Buck PFC can decrease the input voltage to obtain an output voltage less than the peak value of the line voltage [1] . However, zero-crossing distortion degrades power factor. On the contrary, boost PFC can achieve a unity power factor, but its output voltage is higher than its input. Boost PFC cannot deal with the applications of low output voltage, unless it embeds a step-down direct current (dc)/dc stage. Another disadvantage of boost PFC is that power components withstand high-voltage stresses [2] , [3] . Buck–boost can obtain an output voltage whose magnitude is either larger or smaller than the input. Nevertheless, the polarity reversal on output and isolated driving requirement will become potential problems [4] . Similar to buck–boost, ‘Cuk and Zeta have the feature of stepping up or down input voltage. However, pulsating input current and high-side driving are required for Zeta, while ‘Cuk still has the polarity reversal problem [5] - [7] . Flyback PFC can resolve the polarity reversal problem and possesses the characteristic of galvanic isolation, but it has the significant drawback of low efficiency [8] - [13] . Compared with the aforementioned step-up/step-down PFCs, the SEPIC type performs better in total harmonic distortion (THD), efficiency, and power factor [14] - [16] . To reduce component count and improve efficiency, a bridgeless structure attracts a great deal of interest in fulfilling power factor correction. Although high efficiency can be achieved in typical bridgeless PFC topologies derived from boost, buck, or buck-boost [17] - [20] , the aforementioned drawbacks still exist. Some researchers have proposed a bridgeless PFC with respect to SEPIC configuration [21] - [23] ; however, two diodes are needed to accomplish rectification. Given that the two diodes have to block a voltage higher than the mains, the problems of large cut-in voltage and reverse recovery losses remain. In literature [24] , the front-end alternating current-dc bridge rectifier is completely done away with, but the step-down property is lost. To overcome all the mentioned drawbacks, a novel dual-output single-stage bridgeless SEPIC (DOSSBS) with power factor correction is proposed ( Fig. 1 ). Unlike the conventional PFC, the proposed DOSSBS can complete power factor correction without the need for a front-end bridge rectifier, which therefore simplifies converter structure, avoids the problem of power loss on rectifier diode, and decreases component count. DOSSBS is distinguished by the features of single stage, bridgeless, and high efficiency. It can also provide dual individual outputs in a single stage. A 100 W universal line input prototype is built and examined for verification. Experimental results validate the proposed DOSSBS. With respect to practical applications, the proposed DOSSBS can serve as a power supply with power factor correction to drive electric appliances, which need two different levels of source voltage. DOSSBS can power appliances in a single converter, instead of two separate converters, thereby yielding high energy conversion efficiency and low cost. For example, in an intelligent lighting system application, DOSSBS can simultaneously drive light-emitting diodes and provide power for the dimming circuits of the communication interface. The remainder of this paper is organized as follows. Section II describes the operation principle of the proposed DOSSBS. Section III deals with the design considerations of the converter. Section IV provides practical measurements and a performance comparison with other PFCs. Finally, Section V concludes. For the operation description of the proposed DOSSBS, the definitions of current direction and voltage polarity are given in Fig. 2 . The two active switches alternately operate at a high frequency within an interval of line cycle. During the positive half-line cycle, SW₁ is always closed, and SW₂ operates at a high frequency. During the negative half-line cycle, SW₁ switches in a high frequency, while SW₁ is kept in on-state. As the high-frequency switching pattern is not in constant use, the switching loss of the proposed converter can be significantly reduced. The operation of the converter can be divided into four main modes over one switching period. Figs. 3 and 4 show the corresponding equivalents and conceptual key waveforms when the converter is operated in the positive half cycle respectively. The corresponding mode-equivalents and conceptual key waveforms in the negative cycle are illustrated in Figs. 5 and 6 . The converter operation in the positive half cycle is discussed mode by mode below. Mode 1 [Fig. 3(a), t₀-t₁]: Over the entire positive half-line cycle, SW₁ is always in on-state, while SW₂ is operated in a high switching frequency to control input current. SW₂ is turned on at the beginning of mode 1. In mode 1, input voltage is directly connected to the input inductor L₁ . The current i_L1 is linearly built, and the capacitor C₂ dumps energy to the primary of the coupled inductor through SW₂ and D₃ . Meanwhile, the capacitor C_o2 supplies energy for the load R_L2 , and the capacitor C_o1 for the load R_L1 . The voltage across the inductor L₁ is given by where v_s ( t ) represents the line voltage, and V_DS1,on and V_DS2,on stand for the voltage drop on SW₁ and SW₂ respectively. Supposing that the line voltage is purely sinusoidal and equal to V_msin ( 2pf_linet ), the above equation becomes where V_m is the amplitude of line voltage, and f_line denotes the line frequency. The on-state voltage V_DS1,on in Eq. (2) is less than the forward voltage of a rectifier diode. Compared with traditional full-bridge PFCs, the proposed DOSSBS replaces an active switch with two low-frequency rectifier diodes, such that it can significantly decrease conduction loss. The inductor current i_L1 can be determined as follows: Under the boundary mode operation, given that the initial value of the inductor current i_L1 (0) is zero, the converter can achieve zero current switching feature at SW₂ . In mode 1, the capacitor C₂ discharges to the primary magnetizing inductance L_m,pri and the primary leakage inductance L_lk,pri of the coupled inductor. The current i_D3 can be calculated by where v_C2 ( t ) stands for the voltage across the capacitor C₂ , V_D3,f means the forward voltage of the diode D₃ , and L_pri denotes the measured inductance with respect to the input terminals of the coupled inductor while the secondary is open. L_pri is the sum of L_m,pri and L_lk,pri . Mode 2 [Fig. 3(b), t₁-t₂]: his mode begins as soon as SW₂ is turned off. In mode 2, the energy stored in the inductors L₁ , L_m,pri , and L_lk,pri continues to increase. The voltage across the parasitic capacitor of SW₂ also increases, but the capacitors C_o1 and C_o2 still dump energy to the loads R_L1 and R_L2 respectively. The voltage across SW₂ can be expressed as The voltage v_DS2 continuously increases during mode 2. At the moment that v_DS2 reaches the magnitude of input voltage, this mode ends, and the polarities of the inductors L₁ , L_m,pri , and L_lk,pri reverse. All the inductors start discharging. Mode 3 [Fig. 3(c), t₂-t₃]: During this mode, the inductor L₁ releases energy to the capacitors C₂ and C_o2 , and the energy stored in the leakage inductance L_lk,pri will be recycled to the output through L_m,pri , D₂ , and D₃ . L_m,pr dumps energy to C_o2 and C_o1 . From the equivalent circuit of mode 3, the voltage across the parasitic capacitor of SW₂ is clamped at v_c2 + V_o2 . Thus, the voltage stress of SW₂ , V_stress , and _SW2 , can be determined as follows: The inductor current i_L1 can be obtained by where i_L1 ( t₂ ) is the initial value of i_L1 at t = t₂ , and V_D2,f is the voltage drop on the diode D₂ . This mode ends when the current of the leakage inductance L_lk,pri drops to zero. Mode 4 [Fig. 3(d), t₃-t₄]: In mode 4, the inductor L₁ continues supplying energy to the capacitors C₂ and C_o2 , while the coupled inductor transmits energy to C_o1 . The current flowing through L_m,pri linearly decreases, which can be estimated by In the negative half-line cycle, the roles of SW₁ and SW₂ exchange. SW₁ is operated in high frequency to control input current, while SW₂ is kept in on-state over the entire half cycle. The operation of the proposed converter is symmetrical in two half-line cycles of input voltage. The description of operation in the negative half-line cycle is similar to that in the positive which also has four modes. The equivalent circuits and conceptual waveforms are illustrated in Figs. 5 and 6 , respectively. 1) V_o1 = V_o2 : Minimum switching frequency f_sw,min is a key parameter for the design of the input inductor L₁ . Switching frequency can be estimated by determining the on-time and off-time periods of the active switch. As power factor correction is performed under a constant on-time switching pattern, f_sw,min can be obtained after determining the maximum off time. However, a low line input voltage indicates a high on-time interval. Thus, maximum on time T_on,max and maximum off time T_off,max over the range of universal line input should be determined in advance for f_sw,min calculation. Supposing that the range of universal line input is from V_rms,min to V_rms,max , T_on,max then occurs when the line voltage is V_rms,min . Given that output power is equal to the multiplication of input power and converter efficiency, the following equation holds: where η denotes the converter efficiency, and P_o is the output power. Over a half-line cycle, the maximum off time T_off,max appears at the peak of the sinusoidal line voltage. Accordingly, if the two output voltages of the converter are equal, V_o1 = V_o2 = V_o , then From Eqs. (9) and (10), solving T_on,max and T_off,max obtains and The minimum switching frequency is calculated by Substituting Eqs. (11) and (12) into Eq. (13), we obtain To determine the value of the input inductor L₁ , Eq. (14) can be rewritten as Supposing that η = 0.93, then two output voltages are equal, and the minimum line input voltage is 85 V _rms . Fig. 7 shows the relationship among input inductance, power rating, and output voltage. High power rating requires low input inductance; under a certain power rating, a high output voltage needs large input inductance. Considering that a small input inductance will result in a high switching frequency, the minimum switching frequency should be larger than 20 kHz to avoid audio frequency. 2) V_o1 ≠ V_o2 : The determination of input inductance in Eq. (15) is only suitable for the condition V_o1 = V_o2 . If V_o1 ≠ V_o2 , then the minimum switch frequencies of SW₁ and SW₂ will differ. Therefore, two values will be elected as input inductance and are expressed as and f_sw1,min and f_sw2,min denote the minimum switching frequencies of SW₁ and SW₂ respectively. The smaller one between L_α and L_β is chosen as the input inductance, that is, The converter power rating is 100 W, and the minimum line voltage is 85 V _rms . Fig. 8 illustrates the relationship among two output voltages and the minimum switching frequencies of SW₁ and SW₂ . f_SW1,min will be larger than f_SW2,min when V_o1 > V_o2 . On the contrary, f_SW1,min is less than f_SW2,min when V_o1 < V_o2 . If V_o1 = V_o2 , both switching frequencies are identical. f_SW1,min and f_SW2,min vary with input line voltage and output power. For example, η = 0.93, V_o1 = 30 V, V_o2 = 60 V, and input inductance L₁ = 670 μH. Fig. 9 shows the relationship among the minimum switching frequencies of the two active switches, input voltage, and output power. The coupling coefficient of a coupled inductor can be evaluated as follows: Rearranging Eq. (19) yields When the inductance L_sec is in the output terminals while the primary is open, where L_lk,sec is the leakage inductance of the secondary. The relationship between L_lk,pri and L_lk,sec is given by The magnetizing inductance in the secondary L_m,sec also equals the primary magnetizing inductance L_m,pri times the square of turn ratio. The following relationship is then derived: The terminal voltage of the secondary, V_Lsec , can be computed by where V_Lm,pri is the voltage across the magnetizing inductance of the primary. Given that k is less than unity, the following inequality holds: Thus, the design for the coupled inductor should meet the following inequality: The energy-transferred capacitors C₁ and C₂ are also key components because their values significantly influence input line current. Both capacitors must be in a proper design for their steady-state voltage waveforms to be consistent with the rectified input line voltage, and the low-frequency oscillating with input inductor or coupled inductor can be avoided. In practical consideration, resonant frequency should be larger than line frequency but less than minimum switching frequency, that is, and where f_r1 and f_r2 are the resonant frequencies of L₁ - C₂ - L_pri and L₁ - C₁ - L_sec respectively. They are calculated as and According to Eqs. (29) and (30), the capacitances of C₁ and C₂ can be calculated by and respectively. The frequency of output ripple is twice the line frequency. A low output voltage ripple is accompanied by a large output capacitance. Once the output voltage ripple △ V_o is specified, the corresponding output capacitance C_o can be estimated by In this converter, the voltage stress across active switch can be estimated by the peak value of the uppermost universal line voltage V_pk,max plus output voltage. Therefore, and A prototype is built, simulated, and examined to verify the feasibility of the proposed DOSSBS. In the prototype, the universal line input voltage is over the range of 85-265 V _rms , the line frequency is 60 Hz, the output voltage of ports 1 and 2 are 30 and 60 V respectively, that of port 2 is 60 V, and the converter power rating is 100 W. The key component values are summarized in Table I . Fig. 10 shows the measured waveforms of the line voltage v_s and the input inductor current i_L1 at full load when the line voltage is 110 V _rms . The envelope of i_L1 in Fig. 10 is sinusoidal and can be in phase with the line voltage. In the positive half-line cycle, SW₂ is operated at a high frequency, but SW₁ is always in on-state. Fig. 11 shows the zoomed-in waveforms in the positive half-line cycle. The control signal of SW₂ is in a high frequency, and the input inductor current is controlled at a boundary conduction manner. The filtered source current i_in is shown in Fig. 12 , which illustrates that i_in is sinusoidal and in phase with the line voltage. Fig. 13 shows the two output voltages at ports 1 and 2 to demonstrate that both ports can be kept constant at 30 and 60 V under full load. Figs. 14 and 15 present the corresponding waveforms of the step-change transient response of DOSSBS, while the output power at port 1 changes from light to heavy load and from heavy to light load respectively. Both figures indicate that even under step-change loading, DOSSBS still can still feature rapid transient response and sustain stable output voltages. The waveforms of v_C1 and v_C2 are presented in Fig. 16 , which depicts that the positive voltages of v_C1 and v_C2 are sinusoidal, and the maximum negative voltages equal the output voltages of ports 1 and 2. Fig. 17 presents the voltages across the diodes D₁ and D₂ when the line voltage v_s increases to 90 V. The blocking voltage of D₂ is equal to v_C2 plus output voltage at port 2, at approximately 150 V. Under the same input voltage of 90 V, the measured waveforms of v_D3 and v_D4 are shown in Fig. 18 . The reversed voltage across D₄ is approximately 75 V. The result of harmonic measurement is shown in Fig. 19 , which expresses that DOSSBS can meet the standard of IEC 61000-3-2 Class C. The measured THD is 14.8%. Fig. 20 shows the measured power factor over the range of universal line input at full load, in which the maximum power factor approaches unity. Figs. 21 and 22 illustrate the prototype efficiency. Fig. 21 shows the efficiency curve from 4 W to 100 W, while line voltage is 110 V _rms . The figure also demonstrates that DOSSBS can achieve the highest efficiency among the converters of conventional full-bridge SEPIC PFC, bridgeless SEPIC PFC, and bridgeless non-SEPIC PFC. The maximum efficiency of the prototype is up to 95% at approximately 60 W. Efficiency measurement over the entire range of universal line input under full load is presented in Fig. 22 , in which the efficiencies at 110 and 220 V _rms are 93.5% and 95.7% respectively. A comparison with other types of single-stage PFC is summarized in Table II . The proposed converter does not require low-speed diode and dual-output topology. This study proposes DOSSBS PFC, which can deal with a wide range of input of 85-265 V _rms of universal line and provide dual outputs. In the proposed converter, the front-end rectifier is completely removed, thereby simplifying configuration, decreasing component count, and reducing conduction losses. A coupled inductor is incorporated to replace two separate inductors and thus reduce converter volume, as well as recycle the energy stored in leakage inductance. Practical measurements validate the proposed DOSSBS, whose configuration can be expanded for multiple-output applications. Fig. 23 shows the main power schematics, in which the inductors of all the additional output ports can be coupled with L_pri and L_sec . Chih-Lung Shen was born in Tainan, Taiwan, R.O.C. in 1962. He received his B.S. degree from National Taiwan University of Science and Technology, Taipei, Taiwan in 1988; his M.S. degree from National Tsing-Hua University, Hsinchu, Taiwan in 1991; and his Ph.D. degree from National Chung Cheng University, Chia-Yi, Taiwan, R.O.C. in 2003, all in electrical engineering. He is currently with the Department of Electronic Engineering, National Kaohsiung First University of Science and Technology (NKFUST), Kaohsiung, Taiwan, where he is a full professor, the department director of Electronic Engineering, and the director of the Photovoltaics Technology Research Center. His research interests include electric ignition system, photovoltaic-powered systems, active power filters, and power converter design. Shih-Hsueh Yang was born in Kaohsiung, Taiwan in February 1989. He received his B.S. degree in Undergraduate Honors Program of Engineering in 2011 and his M.S. degree in Industrial Technology Master Program on Green Energy and IC Design in 2013 from NKFUST. His research interests include power conversion dc/dc, ac/dc PFC converters, dc/ac inverters, and analog IC design.