This study proposes a dual-output single-stage bridgeless single-ended primary-inductor converter (DOSSBS) that can completely remove the front-end full-bridge alternating current–direct current rectifier to accomplish power factor correction for universal line input. Without the need for bridge diodes, the proposed converter has the advantages of low component count and simple structure, and can thus significantly reduce power loss. DOSSBS has two uncommon output ports to provide different voltage levels to loads, instead of using two separate power factor correctors or multi-stage configurations in a single stage. Therefore, this proposed converter is cost-effective and compact. A magnetically coupled inductor is introduced in DOSSBS to replace two separate inductors to decrease volume and cost. Energy stored in the leakage inductance of the coupled inductor can be completely recycled. In each line cycle, the two active switches in DOSSBS are operated in either high-frequency pulse-width modulation pattern or low-frequency rectifying mode for switching loss reduction. A prototype for dealing with an 85-265 V
rms
universal line is designed, analyzed, and built. Practical measurements demonstrate the feasibility and functionality of the proposed converter.
I. INTRODUCTION
The topologies of power factor corrector (PFC) generally contain buck, boost, buck–boost, Zeta, ‘Cuk, single-ended primary-inductor converter (SEPIC), and flyback. Buck PFC can decrease the input voltage to obtain an output voltage less than the peak value of the line voltage
[1]
. However, zero-crossing distortion degrades power factor. On the contrary, boost PFC can achieve a unity power factor, but its output voltage is higher than its input. Boost PFC cannot deal with the applications of low output voltage, unless it embeds a step-down direct current (dc)/dc stage. Another disadvantage of boost PFC is that power components withstand high-voltage stresses
[2]
,
[3]
. Buck–boost can obtain an output voltage whose magnitude is either larger or smaller than the input. Nevertheless, the polarity reversal on output and isolated driving requirement will become potential problems
[4]
. Similar to buck–boost, ‘Cuk and Zeta have the feature of stepping up or down input voltage. However, pulsating input current and high-side driving are required for Zeta, while ‘Cuk still has the polarity reversal problem
[5]
-
[7]
. Flyback PFC can resolve the polarity reversal problem and possesses the characteristic of galvanic isolation, but it has the significant drawback of low efficiency
[8]
-
[13]
. Compared with the aforementioned step-up/step-down PFCs, the SEPIC type performs better in total harmonic distortion (THD), efficiency, and power factor
[14]
-
[16]
.
To reduce component count and improve efficiency, a bridgeless structure attracts a great deal of interest in fulfilling power factor correction. Although high efficiency can be achieved in typical bridgeless PFC topologies derived from boost, buck, or buck-boost
[17]
-
[20]
, the aforementioned drawbacks still exist. Some researchers have proposed a bridgeless PFC with respect to SEPIC configuration
[21]
-
[23]
; however, two diodes are needed to accomplish rectification. Given that the two diodes have to block a voltage higher than the mains, the problems of large cut-in voltage and reverse recovery losses remain. In literature
[24]
, the front-end alternating current-dc bridge rectifier is completely done away with, but the step-down property is lost.
To overcome all the mentioned drawbacks, a novel dual-output single-stage bridgeless SEPIC (DOSSBS) with power factor correction is proposed (
Fig. 1
). Unlike the conventional PFC, the proposed DOSSBS can complete power factor correction without the need for a front-end bridge rectifier, which therefore simplifies converter structure, avoids the problem of power loss on rectifier diode, and decreases component count. DOSSBS is distinguished by the features of single stage, bridgeless, and high efficiency. It can also provide dual individual outputs in a single stage. A 100 W universal line input prototype is built and examined for verification. Experimental results validate the proposed DOSSBS.
Main power circuit of the proposed DOSSBS.
With respect to practical applications, the proposed DOSSBS can serve as a power supply with power factor correction to drive electric appliances, which need two different levels of source voltage. DOSSBS can power appliances in a single converter, instead of two separate converters, thereby yielding high energy conversion efficiency and low cost. For example, in an intelligent lighting system application, DOSSBS can simultaneously drive light-emitting diodes and provide power for the dimming circuits of the communication interface.
The remainder of this paper is organized as follows. Section II describes the operation principle of the proposed DOSSBS. Section III deals with the design considerations of the converter. Section IV provides practical measurements and a performance comparison with other PFCs. Finally, Section V concludes.
II. OPERATION PRINCIPLE
For the operation description of the proposed DOSSBS, the definitions of current direction and voltage polarity are given in
Fig. 2
. The two active switches alternately operate at a high frequency within an interval of line cycle. During the positive half-line cycle,
SW1
is always closed, and
SW2
operates at a high frequency. During the negative half-line cycle,
SW1
switches in a high frequency, while
SW1
is kept in on-state. As the high-frequency switching pattern is not in constant use, the switching loss of the proposed converter can be significantly reduced.
Representation of voltage polarity and current direction of the proposed converter.
The operation of the converter can be divided into four main modes over one switching period.
Figs. 3
and
4
show the corresponding equivalents and conceptual key waveforms when the converter is operated in the positive half cycle respectively. The corresponding mode-equivalents and conceptual key waveforms in the negative cycle are illustrated in
Figs. 5
and
6
. The converter operation in the positive half cycle is discussed mode by mode below.
Equivalents during one switching period in the positive half-line cycle. (a) Mode 1, (b) Mode 2, (c) Mode 3, and (d) Mode 4.
Conceptual waveforms corresponding to the operation modes in the positive half-line cycle.
Equivalents during one switching period in the negative half-line cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4.
Conceptual waveforms corresponding to the operation modes in the negative half cycle.
Mode 1
[Fig. 3(a), t0-t1]:
Over the entire positive half-line cycle,
SW1
is always in on-state, while
SW2
is operated in a high switching frequency to control input current.
SW2
is turned on at the beginning of mode 1. In mode 1, input voltage is directly connected to the input inductor
L1
. The current
iL1
is linearly built, and the capacitor
C2
dumps energy to the primary of the coupled inductor through
SW2
and
D3
. Meanwhile, the capacitor
Co2
supplies energy for the load
RL2
, and the capacitor
Co1
for the load
RL1
. The voltage across the inductor
L1
is given by
where
vs
(
t
) represents the line voltage, and
VDS1,on
and
VDS2,on
stand for the voltage drop on
SW1
and
SW2
respectively. Supposing that the line voltage is purely sinusoidal and equal to
Vmsin
(
2pflinet
), the above equation becomes
where
Vm
is the amplitude of line voltage, and
fline
denotes the line frequency. The on-state voltage
VDS1,on
in Eq. (2) is less than the forward voltage of a rectifier diode. Compared with traditional full-bridge PFCs, the proposed DOSSBS replaces an active switch with two low-frequency rectifier diodes, such that it can significantly decrease conduction loss. The inductor current
iL1
can be determined as follows:
Under the boundary mode operation, given that the initial value of the inductor current
iL1
(0) is zero, the converter can achieve zero current switching feature at
SW2
.
In mode 1, the capacitor
C2
discharges to the primary magnetizing inductance
Lm,pri
and the primary leakage inductance
Llk,pri
of the coupled inductor. The current
iD3
can be calculated by
where
vC2
(
t
) stands for the voltage across the capacitor
C2
,
VD3,f
means the forward voltage of the diode
D3
, and
Lpri
denotes the measured inductance with respect to the input terminals of the coupled inductor while the secondary is open.
Lpri
is the sum of
Lm,pri
and
Llk,pri
.
Mode 2
[Fig. 3(b), t1-t2]:
his mode begins as soon as
SW2
is turned off. In mode 2, the energy stored in the inductors
L1
,
Lm,pri
, and
Llk,pri
continues to increase. The voltage across the parasitic capacitor of
SW2
also increases, but the capacitors
Co1
and
Co2
still dump energy to the loads
RL1
and
RL2
respectively. The voltage across
SW2
can be expressed as
The voltage
vDS2
continuously increases during mode 2. At the moment that
vDS2
reaches the magnitude of input voltage, this mode ends, and the polarities of the inductors
L1
,
Lm,pri
, and
Llk,pri
reverse. All the inductors start discharging.
Mode 3
[Fig. 3(c), t2-t3]:
During this mode, the inductor
L1
releases energy to the capacitors
C2
and
Co2
, and the energy stored in the leakage inductance
Llk,pri
will be recycled to the output through
Lm,pri
,
D2
, and
D3
.
Lm,pr
dumps energy to
Co2
and
Co1
.
From the equivalent circuit of mode 3, the voltage across the parasitic capacitor of
SW2
is clamped at
vc2
+
Vo2
. Thus, the voltage stress of
SW2
,
Vstress
, and
SW2
, can be determined as follows:
The inductor current
iL1
can be obtained by
where
iL1
(
t2
) is the initial value of
iL1
at
t
=
t2
, and
VD2,f
is the voltage drop on the diode
D2
. This mode ends when the current of the leakage inductance
Llk,pri
drops to zero.
Mode 4
[Fig. 3(d), t3-t4]:
In mode 4, the inductor
L1
continues supplying energy to the capacitors
C2
and
Co2
, while the coupled inductor transmits energy to
Co1
. The current flowing through
Lm,pri
linearly decreases, which can be estimated by
In the negative half-line cycle, the roles of
SW1
and
SW2
exchange.
SW1
is operated in high frequency to control input current, while
SW2
is kept in on-state over the entire half cycle. The operation of the proposed converter is symmetrical in two half-line cycles of input voltage. The description of operation in the negative half-line cycle is similar to that in the positive which also has four modes. The equivalent circuits and conceptual waveforms are illustrated in
Figs. 5
and
6
, respectively.
III. DESIGN CONSIDERATIONS
- A. Equivalent Iron Loss Resistance
1) Vo1 = Vo2 :
Minimum switching frequency
fsw,min
is a key parameter for the design of the input inductor
L1
. Switching frequency can be estimated by determining the on-time and off-time periods of the active switch. As power factor correction is performed under a constant on-time switching pattern,
fsw,min
can be obtained after determining the maximum off time. However, a low line input voltage indicates a high on-time interval. Thus, maximum on time
Ton,max
and maximum off time
Toff,max
over the range of universal line input should be determined in advance for
fsw,min
calculation.
Supposing that the range of universal line input is from
Vrms,min
to
Vrms,max
,
Ton,max
then occurs when the line voltage is
Vrms,min
. Given that output power is equal to the multiplication of input power and converter efficiency, the following equation holds:
where
η
denotes the converter efficiency, and
Po
is the output power. Over a half-line cycle, the maximum off time
Toff,max
appears at the peak of the sinusoidal line voltage. Accordingly, if the two output voltages of the converter are equal,
Vo1
=
Vo2
=
Vo
, then
From Eqs. (9) and (10), solving
Ton,max
and
Toff,max
obtains
and
The minimum switching frequency is calculated by
Substituting Eqs. (11) and (12) into Eq. (13), we obtain
To determine the value of the input inductor
L1
, Eq. (14) can be rewritten as
Supposing that
η
= 0.93, then two output voltages are equal, and the minimum line input voltage is 85 V
rms
.
Fig. 7
shows the relationship among input inductance, power rating, and output voltage. High power rating requires low input inductance; under a certain power rating, a high output voltage needs large input inductance. Considering that a small input inductance will result in a high switching frequency, the minimum switching frequency should be larger than 20 kHz to avoid audio frequency.
Relationship between input inductance and output power under different output voltages.
2) Vo1 ≠ Vo2 :
The determination of input inductance in Eq. (15) is only suitable for the condition
Vo1
=
Vo2
. If
Vo1
≠
Vo2
, then the minimum switch frequencies of
SW1
and
SW2
will differ. Therefore, two values will be elected as input inductance and are expressed as
and
fsw1,min
and
fsw2,min
denote the minimum switching frequencies of
SW1
and
SW2
respectively. The smaller one between
Lα
and
Lβ
is chosen as the input inductance, that is,
The converter power rating is 100 W, and the minimum line voltage is 85 V
rms
.
Fig. 8
illustrates the relationship among two output voltages and the minimum switching frequencies of
SW1
and
SW2
.
fSW1,min
will be larger than
fSW2,min
when
Vo1
>
Vo2
. On the contrary,
fSW1,min
is less than
fSW2,min
when
Vo1
<
Vo2
. If
Vo1
=
Vo2
, both switching frequencies are identical.
Relationship among the minimum switching frequencies of SW1 and SW2 and dual output voltages.
fSW1,min
and
fSW2,min
vary with input line voltage and output power. For example,
η
= 0.93,
Vo1
= 30 V,
Vo2
= 60 V, and input inductance
L1
= 670 μH.
Fig. 9
shows the relationship among the minimum switching frequencies of the two active switches, input voltage, and output power.
Relationship between minimum switching frequency and input voltage under different output powers.
- B. Design of the Coupled Inductance
The coupling coefficient of a coupled inductor can be evaluated as follows:
Rearranging Eq. (19) yields
When the inductance
Lsec
is in the output terminals while the primary is open,
where
Llk,sec
is the leakage inductance of the secondary. The relationship between
Llk,pri
and
Llk,sec
is given by
The magnetizing inductance in the secondary
Lm,sec
also equals the primary magnetizing inductance
Lm,pri
times the square of turn ratio. The following relationship is then derived:
The terminal voltage of the secondary,
VLsec
, can be computed by
where
VLm,pri
is the voltage across the magnetizing inductance of the primary. Given that
k
is less than unity, the following inequality holds:
Thus, the design for the coupled inductor should meet the following inequality:
- C. Coupled Capacitance
The energy-transferred capacitors
C1
and
C2
are also key components because their values significantly influence input line current. Both capacitors must be in a proper design for their steady-state voltage waveforms to be consistent with the rectified input line voltage, and the low-frequency oscillating with input inductor or coupled inductor can be avoided. In practical consideration, resonant frequency should be larger than line frequency but less than minimum switching frequency, that is,
and
where
fr1
and
fr2
are the resonant frequencies of
L1
-
C2
-
Lpri
and
L1
-
C1
-
Lsec
respectively. They are calculated as
and
According to Eqs. (29) and (30), the capacitances of
C1
and
C2
can be calculated by
and
respectively.
- D. Output Capacitance
The frequency of output ripple is twice the line frequency. A low output voltage ripple is accompanied by a large output capacitance. Once the output voltage ripple △
Vo
is specified, the corresponding output capacitance
Co
can be estimated by
- E. Switch Stress
In this converter, the voltage stress across active switch can be estimated by the peak value of the uppermost universal line voltage
Vpk,max
plus output voltage. Therefore,
and
IV. EXPERIMENTAL RESULTS
A prototype is built, simulated, and examined to verify the feasibility of the proposed DOSSBS. In the prototype, the universal line input voltage is over the range of 85-265 V
rms
, the line frequency is 60 Hz, the output voltage of ports 1 and 2 are 30 and 60 V respectively, that of port 2 is 60 V, and the converter power rating is 100 W. The key component values are summarized in
Table I
.
KEY COMPONENTS AND VALUES OF THE PROTOTYPE
KEY COMPONENTS AND VALUES OF THE PROTOTYPE
Fig. 10
shows the measured waveforms of the line voltage
vs
and the input inductor current
iL1
at full load when the line voltage is 110 V
rms
. The envelope of
iL1
in
Fig. 10
is sinusoidal and can be in phase with the line voltage. In the positive half-line cycle,
SW2
is operated at a high frequency, but
SW1
is always in on-state.
Fig. 11
shows the zoomed-in waveforms in the positive half-line cycle. The control signal of
SW2
is in a high frequency, and the input inductor current is controlled at a boundary conduction manner. The filtered source current
iin
is shown in
Fig. 12
, which illustrates that
iin
is sinusoidal and in phase with the line voltage.
Fig. 13
shows the two output voltages at ports 1 and 2 to demonstrate that both ports can be kept constant at 30 and 60 V under full load.
Figs. 14
and
15
present the corresponding waveforms of the step-change transient response of DOSSBS, while the output power at port 1 changes from light to heavy load and from heavy to light load respectively. Both figures indicate that even under step-change loading, DOSSBS still can still feature rapid transient response and sustain stable output voltages. The waveforms of
vC1
and
vC2
are presented in
Fig. 16
, which depicts that the positive voltages of
vC1
and
vC2
are sinusoidal, and the maximum negative voltages equal the output voltages of ports 1 and 2.
Fig. 17
presents the voltages across the diodes
D1
and
D2
when the line voltage
vs
increases to 90 V. The blocking voltage of
D2
is equal to
vC2
plus output voltage at port 2, at approximately 150 V. Under the same input voltage of 90 V, the measured waveforms of
vD3
and
vD4
are shown in
Fig. 18
. The reversed voltage across
D4
is approximately 75 V. The result of harmonic measurement is shown in
Fig. 19
, which expresses that DOSSBS can meet the standard of IEC 61000-3-2 Class C. The measured THD is 14.8%.
Fig. 20
shows the measured power factor over the range of universal line input at full load, in which the maximum power factor approaches unity.
Figs. 21
and
22
illustrate the prototype efficiency.
Fig. 21
shows the efficiency curve from 4 W to 100 W, while line voltage is 110 V
rms
. The figure also demonstrates that DOSSBS can achieve the highest efficiency among the converters of conventional full-bridge SEPIC PFC, bridgeless SEPIC PFC, and bridgeless non-SEPIC PFC. The maximum efficiency of the prototype is up to 95% at approximately 60 W. Efficiency measurement over the entire range of universal line input under full load is presented in
Fig. 22
, in which the efficiencies at 110 and 220 V
rms
are 93.5% and 95.7% respectively. A comparison with other types of single-stage PFC is summarized in
Table II
. The proposed converter does not require low-speed diode and dual-output topology.
Measured waveforms of the line voltage vs and the input inductor current iL1 at full load.
Zoomed-in waveforms of input inductor current and associated control signal in the positive half-line cycle.
Measured waveforms of line voltage and filtered source current.
Measured waveforms of output voltages at ports 1 and 2.
Related waveforms while the output power of port 1 changes from light to heavy load.
Related waveforms while the output power of port 1 changes from heavy to light load.
Measured waveforms of vC1 and vC2.
Measured waveforms of vD1 and vD2.
Measured waveforms of vD3 and vD4.
Measured result of current harmonics.
Measured power factor over the range of universal line input at full load.
Efficiency measurement from light to full load while line voltage is 110 Vrms.
Efficiency measurement over the range of universal line input from 85 Vrms to 265 Vrms.
COMPARISON AMONG THE PROPOSED CONVERTER AND OTHER TYPES OF SINGLE -STAGE PFC
COMPARISON AMONG THE PROPOSED CONVERTER AND OTHER TYPES OF SINGLE -STAGE PFC
V. CONCLUSION
This study proposes DOSSBS PFC, which can deal with a wide range of input of 85-265 V
rms
of universal line and provide dual outputs. In the proposed converter, the front-end rectifier is completely removed, thereby simplifying configuration, decreasing component count, and reducing conduction losses. A coupled inductor is incorporated to replace two separate inductors and thus reduce converter volume, as well as recycle the energy stored in leakage inductance. Practical measurements validate the proposed DOSSBS, whose configuration can be expanded for multiple-output applications.
Fig. 23
shows the main power schematics, in which the inductors of all the additional output ports can be coupled with
Lpri
and
Lsec
.
Main circuit schematic of the expanded configuration of the proposed converter.
BIO
Chih-Lung Shen was born in Tainan, Taiwan, R.O.C. in 1962. He received his B.S. degree from National Taiwan University of Science and Technology, Taipei, Taiwan in 1988; his M.S. degree from National Tsing-Hua University, Hsinchu, Taiwan in 1991; and his Ph.D. degree from National Chung Cheng University, Chia-Yi, Taiwan, R.O.C. in 2003, all in electrical engineering. He is currently with the Department of Electronic Engineering, National Kaohsiung First University of Science and Technology (NKFUST), Kaohsiung, Taiwan, where he is a full professor, the department director of Electronic Engineering, and the director of the Photovoltaics Technology Research Center. His research interests include electric ignition system, photovoltaic-powered systems, active power filters, and power converter design.
Shih-Hsueh Yang was born in Kaohsiung, Taiwan in February 1989. He received his B.S. degree in Undergraduate Honors Program of Engineering in 2011 and his M.S. degree in Industrial Technology Master Program on Green Energy and IC Design in 2013 from NKFUST. His research interests include power conversion dc/dc, ac/dc PFC converters, dc/ac inverters, and analog IC design.
Qu X.
,
Wong S.C.
,
Tse C. K.
2011
“Resonance-assisted buck converter for offline driving of power LED replacement lamps,”
IEEE Trans. Power Electron.
26
(2)
532 -
540
DOI : 10.1109/TPEL.2010.2065242
Mather B. A.
,
Maksimović D.
2011
“A simple digital power-factor correction rectifier controller,”
IEEE Trans. Power Electron.
26
(1)
9 -
19
DOI : 10.1109/TPEL.2010.2051458
Chen H.C.
2014
“Interleaved current sensorless control for multiphase boost-type switch-mode rectifier with phase-shedding operation,”
IEEE Trans. Ind. Electron.
61
(2)
766 -
775
DOI : 10.1109/TIE.2013.2257137
Chen J.
,
Maksimovic D.
,
Erickson R. W.
2006
“Analysis and design of a low-stress buck-boost converter in universal-input PFC applications,”
IEEE Trans. Power Electron.
21
(2)
320 -
329
DOI : 10.1109/TPEL.2005.869744
Kavitha A.
,
Uma G.
,
Reesha M. Beni
2012
“Analysis of fast-scale instability in a power factor correction Ćuk converter,”
IET Power Electron.
5
(8)
1333 -
1340
DOI : 10.1049/iet-pel.2011.0175
Zhang H.
,
Zhang Y.
,
Ma X.
2012
“Distortion behavior analysis of general pulse-width modulated Zeta PFC converter operating in continuous conduction mode,”
IEEE Trans. Power Electron.
27
(10)
4212 -
4223
DOI : 10.1109/TPEL.2012.2191161
Singh S.
,
Singh B.
“Voltage controlled PFC Zeta converter based PMBLDCM drive for an air-conditioner,”
Industrial and Information Systems (ICIIS), 2010 International Conference on
Aug. 2010
550 -
555
Lee J. J.
,
Kwon J. M.
,
Kim E. H.
,
Choi W. Y.
,
Kwon B. H.
2008
“Single-stage single-switch PFC flyback converter using a synchronous rectifier,”
IEEE Trans. Ind. Electron.
55
(3)
1352 -
1365
DOI : 10.1109/TIE.2007.911908
Garcia J.
,
Dalla-Costa M.
,
Kirsten A.
,
Gacio D.
,
Calleja A.
2013
“A novel flyback-based input PFC stage for electronic ballasts in lighting applications,”
IEEE Trans. Ind. Appl.
49
(2)
769 -
777
DOI : 10.1109/TIA.2013.2244545
Athab H.
,
Lu D.
,
Ramar K.
2012
“A single-switch AC/DC flyback converter using a CCM/DCM quasi-active power factor correction front-end,”
IEEE Trans. Ind. Electron.
59
(3)
1517 -
1526
DOI : 10.1109/TIE.2011.2158771
Chiu H. J.
,
Lo Y. K.
,
Lee H. C.
,
Cheng S. J.
,
Yan Y. C.
,
Lin C. Y.
,
Wang T. H.
,
Mou S. C.
2010
“A single-stage soft-switching flyback converter for power-factorcorrection applications,”
IEEE Trans. Ind. Electron.
57
(6)
2187 -
2190
DOI : 10.1109/TIE.2009.2033622
Xie X.
,
Wang J.
,
Zhao C.
,
Lu Q.
,
Liu S.
2012
“A novel output current estimation and regulation circuit for primary side controlled high power factor single-stage flyback LED driver,”
IEEE Trans. Power Electron.
27
(11)
4602 -
4612
DOI : 10.1109/TPEL.2012.2190523
Choi W.-Y.
,
Choi J.-Y.
2011
“A novel single-stage AC-DC converter to supply sustain power for plasma display panels,”
J. Display Technol.
7
(9)
494 -
502
DOI : 10.1109/JDT.2011.2141113
Kwon J.-M.
,
Choi W.-Y.
,
Lee J.-J.
,
Kim E.-H.
,
Kwon B.-H.
2006
“Continuous conduction mode SEPIC converter with low reverse-recovery loss for power factor correction,”
IEE Proc. Elect. Power Appl.
153
(5)
673 -
681
DOI : 10.1049/ip-epa:20060486
Melo P. F.
,
Gules R.
,
Romaneli E. F. R.
,
Annunziato R. C.
2010
“A modified SEPIC converter for high power factor rectifier and universal-input voltage applications,”
IEEE Trans. Power Electron.
25
(2)
310 -
321
DOI : 10.1109/TPEL.2009.2027323
Ma H.
,
Lai J. S.
,
Feng Q.
,
Yu W.
,
Zheng C.
,
Zhao Z.
2012
“A novel valley-fill SEPIC-derived power supply without electrolytic capacitors for LED lighting application,”
IEEE Trans. Power Electron.
27
(6)
3057 -
3071
DOI : 10.1109/TPEL.2011.2174446
Jang Y.
,
Jovanovi´c M. M.
2011
“Bridgeless high-power-factor Buck converter,”
IEEE Trans. Power Electron.
26
(2)
602 -
611
DOI : 10.1109/TPEL.2010.2068060
Huber L.
,
Jang Y.
,
Jovanovic M. M.
2008
“Performance evaluation of bridgeless PFC Boost rectifiers,”
IEEE Trans. Power Electron.
23
(3)
1381 -
1390
DOI : 10.1109/TPEL.2008.921107
Wei W.
,
Hongpeng L.
,
Shigong J.
,
Dianguo X.
“A novel bridgeless buck-boost PFC converter,”
in Proc. IEEE Power Electron. Spec. Conf.
Jun. 2008
1304 -
1308
Shu-Kong K.
,
Lu D. D. C.
2013
“A high step-down transformerless single-stage single-switch AC/DC converter,”
IEEE Trans. Power Electron.
28
(4)
36 -
45
Sabzali A. J.
,
Ismail E. H.
,
Al-Saffar M. A.
,
Fardoun A. A.
2011
“New bridgeless DCM SEPIC and Ćuk PFC rectifiers with low conduction and switching losses,”
IEEE Trans. Ind. Appl.
47
(2)
873 -
881
DOI : 10.1109/TIA.2010.2102996
Mahdavi M.
,
Farzanehfard H.
2011
“Bridgeless SEPIC PFC rectifier with reduced components and conduction losses,”
IEEE Trans. Ind. Electron.
58
(9)
4153 -
4160
DOI : 10.1109/TIE.2010.2095393
Yang J.-W.
,
Do H.-L.
2013
“Bridgeless SEPIC converter with a ripple-free input current,”
IEEE Trans. Powerw Electron.
28
(7)
3388 -
3394
DOI : 10.1109/TPEL.2012.2226607
Ismail E. H.
2009
“Bridgeless SEPIC rectifier with unity power factor and reduced conduction losses,”
IEEE Trans. Ind. Electron.
56
(4)
1147 -
1157
DOI : 10.1109/TIE.2008.2007552