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An Active Clamp High Step-Up Boost Converter with a Coupled Inductor
An Active Clamp High Step-Up Boost Converter with a Coupled Inductor
Journal of Power Electronics. 2015. Jan, 15(1): 86-95
Copyright © 2015, The Korean Institute Of Power Electronics
  • Received : June 10, 2014
  • Accepted : September 18, 2014
  • Published : January 20, 2015
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About the Authors
Quanming Luo
State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing, China
lqm394@126.com
Yang Zhang
State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing, China
Pengju Sun
State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing, China
Luowei Zhou
State Key Laboratory of Power Transmission Equipment & System Security and New Technology, Chongqing University, Chongqing, China

Abstract
An active clamp high step-up boost converter with a coupled inductor is proposed in this paper. In the proposed strategy, a coupled inductor is adopted to achieve a high voltage gain. The clamp circuit is included to achieve the zero-voltage-switching (ZVS) condition for both the main and clamp switches. A rectifier composed of a capacitor and a diode is added to reduce the voltage stress of the output rectifier diode. As a result, diodes with a low reverse-recovery time and forward voltage-drop can be utilized. Since the voltage stresses of the main and clamp switches are far below the output voltage, low-voltage-rated MOSFETs can be adopted to reduce conduction losses. Moreover, the reverse-recovery losses of the diodes are reduced due to the inherent leakage inductance of the coupled inductor. Therefore, high efficiency can be expected. Firstly, the derivation of the proposed converter is given and the operation analysis is described. Then, a steady-state performance analysis of the proposed converter is analyzed in detail. Finally, a 250 W prototype is built to verify the analysis. The measured maximum efficiency of the prototype is 95%.
Keywords
I. INTRODUCTION
Non-isolated high step-up DC/DC converters are widely employed in many industrial applications, such as uninterruptable power systems, photovoltaic systems, fuel cell systems, electric vehicles, high-intensity discharge lamps, etc. [1] - [4] . Theoretically, under the ideal continuous current mode operation, the conventional boost converter can achieve a very high voltage gain with an extremely high duty cycle. However, in practice, it is difficult to design a boost converter with a very high voltage gain due to the equivalent series resistance (ESR) elements, which cause poor efficiency and a degraded voltage gain. The optimized voltage gain of the conventional boost converter is limited to approximately four times with a relative high efficiency [5] , [6] . Therefore, it is not preferable for high step-up and high voltage applications.
Many isolated current-fed converters, such as current-fed push-pull converters [7] , current-fed full-bridge converters [8] , and dual boost converters are applied in high step-up applications [9] , [10] . When compared with the voltage-fed converters, the voltage stresses of the rectifier diodes and the turns ratio of the transformer are reduced in the current-fed converters due to their boost-type configuration, which make them more suitable for obtaining a high voltage gain [11] , [12] . However, at least one inductor and one transformer are required in these converters, which increases the circuit volume and reduces the power density.
When compared with an isolation transformer, a coupled inductor or tapped inductor has a simpler winding structure and lower conduction loss. Thus, a coupled-inductor-based high step-up boost converter seems to be more attractive in these high step-up applications. By introducing a coupled inductor to the conventional boost converter, the turns ratio of the coupled inductor becomes another design freedom for extending the voltage gain except for the switch duty cycle, which shows a flexibility for optimizing the efficiency and improving the utilization of the components [13] . However, the leakage inductance of the coupled inductor may cause a high voltage spike on the switch when it turns OFF. It may also induce large energy losses. In order to solve the aforementioned problems, a resistor-capacitor-diode (RCD) snubber can be employed, but the leakage energy is dissipated [14] . Passive lossless clamp circuits composed of diodes and capacitors are adopted to clamp the turn-off voltage spikes on the switch and to recycle the leakage inductance energy [15] - [18] . Thus, low-voltage rated switches can be employed to improve the efficiency. Meanwhile, the reverse-recovery problem of the output diode is partly solved by a reasonable design of the leakage inductance. However, the switches in these converters work under the hard switching condition. The active clamp circuit can be used to replace the role of the passive lossless clamp circuit. In addition, the main and clamp switches turn ON under the zero-voltage-switching (ZVS) condition, and the turn OFF losses can be greatly reduced with the help of parallel capacitors [19] . Unfortunately, the output rectifier diode suffers from very high voltage stress. Thus, high-voltage-rated diodes must be adopted, which may degrade the efficiency.
In this paper, an active clamp high step-up boost converter with a coupled inductor is proposed. Like the converter proposed in [19] , the coupled inductor is included to extend the voltage ratio, while a boost type or buck-boost type clamp circuit can be employed to recycle the leakage inductance energy and achieve the zero voltage switching condition for the main and clamp switches. Moreover, a rectifier composed of a diode and a capacitor is adopted to reduce the voltage stress of the output rectifier diode. Since the voltage stresses of the switches and diodes are lower than the output voltage, low-voltage-rated metal-oxide-semiconductor field-effect transistors (MOSFETs) and diodes can be adopted for reductions of conduction losses and cost.
This paper is organized as follows. In Section II, the derivation of the proposed converter is presented and the operation analysis is described. The steady state performance analysis is carried out in Section III. Experimental results are given in Section IV, and Section V presents some conclusions drawn from the investigation.
II. DERIVATION AND OPERATION ANALYSIS OF THE CONVERTER
- A. Topology Derivation
The coupled-inductor boost converter presented in [14] is shown in Fig. 1 (a), and the voltage gain is given by:
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Where D is the duty cycle of the main switch S and N ( N = n 2 / n 1 ) is the turns ratio of the coupled-inductor.
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The derivation of the proposed converter. (a) The coupled-inductor based boost converter presented in [14]. (b) A capacitor and a diode are added as a rectifier. (c) Active clamp circuit is included.
From (1), it is clear that a higher voltage gain than that of the conventional boost converter is achieved by introducing the coupled inductor. However, the voltage stress of the output diode D o is much higher than its output voltage when switch S is in the on state. A rectifier composed of a diode D r and a capacitor C r is included to reduce the voltage stress of the output diode D o as shown in Fig. 1 (b). Therefore, low-voltage-rated diodes can be adopted for a reduction of the conduction losses, and a higher efficiency can be achieved than the circuit shown in Fig. 1 (a). Finally, in order to make the main switch S work under the soft switching condition, a boost type active clamp circuit composed of a clamp switch S c and a capacitor C c is adopted, as shown in Fig. 1 (c).
- B. Operation Analysis
In order to perform a mode analysis of the proposed converter, several assumptions are made as follows. The coupled inductor is modeled as a magnetizing inductor L m , a leakage inductor L lk , and an ideal transformer with a turn ratio N . C s is the extra parallel capacitor, and the parasitic capacitors of the main and clamp switches can be included in it. D s and D c are the body diodes of S and S c , respectively. The capacitors C c , C r and C o are large enough to assume that the voltages across them is constant. Finally, the switches and diodes are assumed to be ideal. The equivalent circuit of the converter is shown in Fig.2 .
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The equivalent circuit of the proposed converter.
There are nine operation stages during one switching cycle. The key waveforms are shown in Fig.3 and the equivalent circuits for each stage are shown in Fig.4 .
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Key waveforms of the proposed converter.
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Operational stages of the proposed converter. (a) Stage 1 [t0t1]. (b) Stage 2 [t1t2]. (c) Stage 3 [t2t3]. (d) Stage 4 [t3t4]. (e) Stage 5 [t4t5]. (f) Stage 6 [t5t6]. (g) Stage 7 [t6t7]. (h) Stage 8 [t7t8]. (i)Stage 9 [t8t0′].
Stage 1 [t 0 t 1 ] : Before t 1 , the main switch S is in the ON state while the clamp switch S c is in the OFF state. The output diode D o and rectifier diode D r are reversed-biased. The magnetizing inductor L m and leakage inductor L lk are connected in series and charged by the input voltage V in . Therefore, the currents through them are equal and increase gradually in a linear way. The clamp capacitor voltage V Cc and rectifier capacitor voltage V Cr are unchanged. The load current is provided solely by the output capacitor C o . In this stage, the increasing rate of the magnetizing inductor current i Lm and that of the leakage inductor current i Lk are given by:
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Stage 2 [t 1 t 2 ] : At t 1 , the main switch S turns off. Then, the parallel capacitor C s is charged by the magnetizing current. Since C s is small and L m is relatively large, the drain-source voltage of the switch S increases and that of the clamp switch S c decreases at a constant slope. The turn-off losses of the main switch S are reduced due to the existence of the parallel capacitor C s . The increasing rate of the drain-source voltage v s can be derived by:
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The transition interval of this stage is deduced by:
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Stage 3 [t 2 t 3 ] : At t 2 , the drain-source voltage of the main switch S reaches the clamp voltage, and the antiparallel diode of the clamp switch D c is forced to conduct. Therefore, v s is clamped to V Cc by the antiparallel diode D c . Since the clamp capacitor C c is much larger than C s , C s can be neglected and almost all of the current flows through C c . In this stage, the magnetizing inductor and leakage inductor are discharged by the voltage of V in - V Cc , and the currents through them decrease approximately linearly with a decreasing rate given by:
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Stage 4 [t 3 t 4 ] : The turn-on signal is applied to the clamp switch S c at t 3 . S c is turned ON when its antiparallel diode D c is conducting. Thus, the ZVS turn-on condition is achieved. The equivalent circuit in this stage is similar to that of stage 3.
Stage 5 [t 4 t 5 ] : At t 4 , the rectifier diode D r and output diode D o are forced to conduct. The magnetizing inductor L m and leakage inductor L lk are discharged by the voltages of – V Cr / N and V in + V Cr / N V Cc , respectively. Since L lk is much smaller than L m , the decreasing rate of i lk is much greater than that of i Lm . Since the output capacitor C o is relatively large when compared with the clamp capacitor C c , the current through the output rectifier diode i Do is approximately equal to i lk . The current through the rectifier diode i Dr increases linearly from zero, and the increasing rate is given by (8).
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Stage 6 [t 5 t 6 ] : At t 5 , the current through the output diode D o decreases linearly to zero and D o turns off. The leakage inductor current i Lk begins to change its direction and it increases linearly in the reverse direction. The magnetizing inductor current i Lm continues to decrease linearly and the current through the rectifier diode i Dr continues to increase linearly. The change rates of i Lk , i Lm and i Dr are the same as the ones in the previous stage.
Stage 7 [t 6 t 7 ] : At t 6 , the clamp switch S c turns off. The parallel capacitor C s and the leakage inductor L lk begin to resonate. Since the resonant period is relatively large and the transition interval of this stage is relatively small too, it is reasonable to assume that the leakage inductor current i Lk keeps constant and that v s decrease approximately linearly. The magnetizing inductor current i Lm continues to decrease with the change rate shown in (6). The transition interval of this stage can be derived by:
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Stage 8 [t 7 t 8 ] : At t 7 , the drain-source voltage of the main switch v s decreases to zero and the parallel diode D s is forced to conduct. The voltage across the leakage inductor is equal to V in + V Cr / N , and the change rate is derived by (10). The magnetizing inductor current i Lm continues to decrease in this stage.
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Stage 9 [t 8 t 0 ′] : At t 8 , the turn-on signal is applied to the main switch S when its antiparallel diode is in the ON state. Therefore, the main switch S turns ON with ZVS. The equivalent circuit of this stage is similar to that of the previous stage. At t 0 ′, the leakage inductor current i Lk increases to be equal to the magnetizing inductor current i Lm , the current through the rectifier diode i Dr drops to zero, and D r turns off. After that, the magnetizing inductor L m and leakage inductor L lk are connected in series and charged by the input voltage V in again. Then, a new switching period begins.
III. STEADY STATE PERFORMANCE ANALYSIS
- A. Voltage Gain
When the leakage inductor L Lk is equal to zero, one switching cycle can be separated into two stages. When the main switch S is in the ON state and the clamp switch S c is in the OFF state, the voltage across the magnetizing inductor L m , V Lm-charge can be derived by:
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When the main switch S is in the OFF state and the clamp switch S c is in the ON state, the magnetizing inductor is discharged by V Lm-discharge , and V Lm-discharge is deduced by:
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By applying the inductor volt-second balance principle to the magnetizing inductor, the voltage across the clamp capacitor V Cc can be derived by:
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Since the magnetizing inductor current i Lm is continuous, the capacitor voltage V Cr can de deduced by:
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Apparently, the output voltage V o is the sum of V Cc and V Cr . Therefore, the ideal voltage gain M ideal when the leakage inductor is omitted can be obtain by:
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From the operation analysis in Section II, it can be seen that the leakage inductor L lk causes little duty cycle loss. The voltage gain when considering the influence of leakage inductor L lk is deduced as follows.
Since the time intervals from t 1 to t 4 and from t 6 to t 8 are relatively short when compared with the switching cycle, they are excluded in the following voltage gain analysis, and there are only four stages during one switching cycle. The ideal current waveform of the leakage inductance is taken as a straight line during each subinterval due to the relatively large resonant period. Simplified waveforms are shown in Fig. 5 .
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The simplified waveforms.
During the time interval from t 0 to t 4 , the main switch S is in the ON state and the clamp switch S c is in the OFF state. Moreover, the rectifier diode D r is reverse biased. The magnetizing inductor L m and leakage inductor L lk are series connected and charged by V Lm-charge and V Llk-charge , respectively. V Lm-charge and V Llk-charge are derived by:
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During the time interval from t 4 to t 6 , the main switch S is in the OFF state and the clamp switch S c is in the ON state. At the same time, the rectifier diode D r is forced to conduct. The magnetizing inductor L m and leakage inductor L lk are discharged by V Lm-discharge and V Llk-discharge , respectively, and can be obtained by:
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During the last time interval in one switching cycle from t 6 to t 0 ′, the main switch S is in the ON state and the clamp switch S c is in the OFF state. In addition, the rectifier diode D r is forward biased in this time interval. The magnetizing inductor is discharged by V Lm-discharge which can be obtained by (18), while the leakage inductor is charged by V Llk-charge which can be derived by:
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By applying the volt-second balance principle to the magnetizing inductor L m and leakage inductor L lk , the following equations can be derived:
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At t 6 , the current through the diode D f , i Dr reaches its peak value I Dr-peak which can be deduced by (23), and the average value of i Dr , I Df can be obtained by (24):
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When operating at the steady state, the average currents through the capacitors C r and C o are zero. Therefore, I Dr should be equal to the output current I o and the following equation is obtained:
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Apparently, the output voltage V o is the sum of V Cc and V Cr , that is:
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From (21), (22) and (24) to (26), the voltage gain of the proposed converter, when considering the leakage inductor, can be expressed by:
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Where k L = L lk / L m and k m = L lk f s / R o . f s is the switching frequency.
The relationship between the voltage gain, the duty cycle, the leakage inductor, and the turns ratio with L m =120 μH, f s =100 kHz, R o =578 Ω is shown in Fig. 6 . It is concluded that the voltage gain ratio increases significantly as the turns ratio of the coupled inductor increases, which is a desirable feature in high step-up high efficiency applications because a very narrow turn-OFF period is avoided. When the turns ratio is zero, the voltage gain of the proposed converter is the same as that of the conventional boost converter. The leakage inductor has little effect on the voltage gain of the converter. As the leakage inductor increases, the voltage gain decreases.
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The voltage gain of the proposed converter.
- B. Voltage and Current Stresses
Neglecting the voltage ripples on the capacitors C c , C r and C o , and assuming the leakage inductor to be zero, the voltage stress of the main switch S, V S-stress is equal to the voltage stress of the clamp switch S c , V Sc-stress , which can be derived by:
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The voltage stress of the rectifier diode D r , V Dr-stress is given by:
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From (14) and (29), V Dr-stress is obtained by:
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The voltage stress of the output diode D o , V Do-stress is given by:
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From (14), (15) and (31), V Do-stress is obtained by:
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From (15), (28) and (32), V S-stress , V Sc-stress , and V Do-stress are equivalent and they are lower than the output voltage V o . Fig. 7 (a) shows the voltage stress normalized by V o . When the duty cycle D and the turns ratio N increase, the voltage stress decreases. Since V S-stress and V Sc-stress are much lower than the output voltage V o , low-voltage-rated switches can be used to improve the efficiency. From (15) and (30), the voltage stress of the rectifier diode D r V Dr-stress normalized by the output voltage V o is shown in Fig. 7 (b). It can be seen that the voltage stress on D r decreases as the duty cycle D increases or as the turns ratio N decreases. Moreover, it is lower than the output voltage V o if the following condition is satisfied:
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The voltage stresses according to the variation of duty cycle D and turns ratio N. (a) VS-stress, VSc-stress, VDo-stress normalized by Vo. (b) VDr-stress normalized by Vo.
According to the operation analysis of the proposed converter in Section II, the current stresses of the main switch S, the clamp switch S c , and the output diode D o , which are expressed by I S-stress , I Sc-stress , and I Do-stress , respectively, are similarly equal to the peak value of the current through the output rectifier diode D o , I Do-peak . From Fig.5 , I Do-peak can be deduced by:
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Since the average value of the current through the output rectifier diode D o , I Do should be equal to the output current I o when operating at the steady state, the following equation is obtained:
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Additionally, the clamp capacitor voltage V Cc is given by:
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From (26), (27) and (34) to (36), D 1 can be derived by:
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Therefore, I S-stress , I Sc-stress and I Do-stress can be deduced by:
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I S-stress , I Sc-stress and I Do-stress normalized by I o according to variations of the duty cycle D , the turns ratio N and the leakage inductor L lk are shown in Fig. 8 (a). It is shown that the current stress increases with an increasing duty cycle D . Additionally, as the turns ratio N decreases and the leakage inductor L lk increases, the current stress decreases.
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The current stress of the main switch S, clamp switch Sc, output diode Do, and rectifier diode Dr normalized by Io. (a) IS-stress, ISc-stress, IDo-stress normalized by Io. (b) IDr-stress normalized by Io with N=4. (c) IDr-stress normalized by Io with N=2. (d) IDr-stress normalized by Io with N=1.
From (23), (26), (27) and (32), the current stress of the rectifier diode D r , I Dr-stress can be derived by:
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I Dr-stress normalized by I o according to variations of the duty cycle D , the turns ratio N and the leakage inductor L lk is shown in Fig. 8 (b) to Fig. 8 (d) with N =4, N =2, and N =1 respectively for clear. It is show that the current stress of the rectifier diode D r increases with an increasing duty cycle. However, it decreases with an increasing leakage inductor. Moreover, from Fig. 8 (b) to Fig. 8 (d), the current stress I Dr-stress increases with a decreasing turns ratio N .
- C. Soft Switching Condition
The turn-off losses of the main and clamp switches are reduced because of the parallel capacitor. The reverse-recovery losses of the diodes are negligible since the leakage inductor provides a current snubbing effect. The ZVS turn-on condition of the clamp switch can be realized by applying a turn-on signal when its antiparallel diode is in the ON state and the drain-source voltage is clamped to zero. To realize to the ZVS turn-on condition of the main switch, the energy stored in the leakage inductor should be greater than that stored in the parallel capacitor when the clamp switch turns off. Therefore, the ZVS turn-on condition of the main switch can be derived by:
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IV. EXPERIMENTAL RESULTS AND ANALYSIS
In order to verify the performance of the proposed converter, a 250W prototype is built and tested. Due to the resonance between the leakage inductor of the coupled inductor and the junction capacitor of the rectifier diode D r , it is necessary to add a proper resistor-capacitor-diode (RCD) snubber to reduce the voltage spike across D r , as shown in Fig. 9 . Since the current level at the high-voltage side of the coupled inductor is relatively low, even though an RCD snubber is adopted, the conversion efficiency will not drop significantly. The parameters of the converter are described in Table I and the experimental results of the proposed converter are shown in Fig. 10 .
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The proposed converter with RCD snubber.
PARAMETER OF THE PROTOTYPE
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PARAMETER OF THE PROTOTYPE
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The experimental results of the proposed converter. (a) The measured waveforms of QS, Vin and Vo. (b) Leakage current iLk and magnetizing inductance voltage vLm (c) ZVS-on performance of main switch S. (d) ZVS-on performance of clamp switch Sc. (e) Voltage and current waveforms of rectifier diode Dr and output diode Do.
Fig. 10 (a) shows the gate-source voltage of the main switch QS, the input voltage V in and the output voltage V o . The measured duty cycle is about 0.68 as predicted by (15), and high step-up capacity is verified. The current of the leakage inductance i Lk and the voltage of the magnetizing inductance v Lm are shown in Fig. 10 (b). It can be seen that the experimental results are consistent with the theoretical analysis. The gate-source voltage, drain-source voltage and current experimental waveforms of the main switch S and the clamp switch S c are shown in Fig. 10 (c) and Fig. 10 (d) respectively. It is shown that both the main switch and the clamp switch are turned ON and OFF under the ZVS condition. This reduces the switching losses greatly. Moreover, the voltage stresses of the main switch and clamp switch is about 160V. Thus, low-voltage-rated MOSFETs can be adopted and the conduction losses can be reduced. Fig. 10 (e) shows voltage and current waveforms of the rectifier diode D r and the output rectifier diode D o . Clearly, the reverse-recovery current of the rectifier diode D r and output rectifier diode D o is small because the reverse-recovery problem is alleviated by the leakage inductance of the coupled inductor. As a result, the reverse-recovery losses are minimized. The voltage waveform of the output diode in the converter proposed in [19] is illustrated in Fig. 11 . It shows that the voltage stress of the diode is 550V, which is much higher than the 380V of the rectifier diode D r and the 160V of the output rectifier diode D o in the proposed converter. Therefore, a low forward voltage drop diode can be used to improve the efficiency of the proposed converter. An efficiency comparison between the proposed converter and the converter proposed in reference [19] is plotted in Fig. 12 . It can be seen that the maximum efficiency of the proposed converter is 95% with a 48V input and a 380V output conversion when operating at 100kHz. When compared with the converter proposed in reference [19] , there is about a 1% efficiency improvement under full load and about a 3% efficiency improvement under light load.
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Voltage waveforms of output diode in the converter proposed in [19].
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The efficiency comparison between proposed converter and converter proposed in reference [19].
V. CONCLUSIONS
An active clamp high step-up boost converter with a coupled inductor has been proposed in this paper. A coupled inductor is included to extent the voltage gain. By applying an active clamp circuit, the main and clamp switches operate under the ZVS condition and the switching losses are minimized. The reverse-recovery problems of the diodes are solved due to the inherent leakage inductor of the coupled inductor. Additionally, the voltage stress of the output diode is reduced by adopting a rectifier composed of a diode and a capacitor. The derivation of the proposed converter is presented. A steady-state operational analysis and the main circuit performance are discussed to explore the advantages of the proposed converter. Finally, a 250W prototype has been built and experimental results have been presented to verify the analysis.
Acknowledgements
This project is supported by The National High Technology Research and Development of China 863 Program (2011AA05A110),the National Natural Science Foundation of China (51207172), and the Scientific Research Foundation of the SKL of Power Transmission Equipment & System Security and New Technology (2007DA10512713204).
BIO
Quanming Luo was born in Chongqing, China, in 1976. He received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Chongqing University, Chongqing, China, in 1999, 2002, and 2008, respectively. He was with the Emerson Network Power Co. Ltd., Shenzhen, China, as a Research and Development Engineer, from 2002 to 2005. Since 2005, he has been with the College of Electrical Engineering, Chongqing University, where he is presently an Associate Professor. He is the author or coauthor of more than 30 papers in journal or conference proceedings. His current research interests include LED driving systems, communication power systems, power harmonic suppression, and power conversion systems in electrical vehicles.
Yang Zhang was born in Hubei, China, in 1989. He received his B.S. degree in Electrical Engineering from the Wuhan Polytechnic University, Wuhan, China, in 2012. He is presently working toward his M.S. degree in Electrical Engineering at Chongqing University, Chongqing, China. His current research interests include high-efficiency power converters and photovoltaic power systems.
Pengju Sun was born in Henan, China. She received her B.S. and Ph.D. degrees in Electrical Engineering from Chongqing University, Chongqing, China, in 2005 and 2011, respectively. Since 2011, she has been with the College of Electrical Engineering, Chongqing University. She was a Visiting Student with the University of California, Irvine, CA, USA, from September 2009 to August 2010. Her current research interests include wide output range DC/DC converters, digital control techniques, high power high performance power converters and power factor correction.
Luowei Zhou was born in Dujiangyan, China. He received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Chongqing University, Chongqing, China, in 1982, 1988, and 2000, respectively. Since 1982, he has been with the College of Electrical Engineering, Chongqing University, where he is presently a Full Professor. He was a Visiting Professor with the University of California, Irvine, CA, USA, from September 1998 to August 1999. He is the Vice Director of the China Society of Power Supply. His current research interests include the analysis and control of power electronics circuits, the realization of active power filters, power factor correction techniques, and high frequency power conversion.
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