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Dead Angle Reduction of Single-Stage PFC Using Controllable Coupled Inductors
Dead Angle Reduction of Single-Stage PFC Using Controllable Coupled Inductors
Journal of Power Electronics. 2015. Jan, 15(1): 78-85
Copyright © 2015, The Korean Institute Of Power Electronics
  • Received : May 24, 2014
  • Accepted : August 26, 2014
  • Published : January 20, 2015
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About the Authors
Mohammad Mehdi Tavassol
Dept. of Electrical & Computer Engineering, Isfahan University Of Technology, Isfahan, Iran
mm.tavassol@ec.iut.ac.ir
Hosein Farzanehfard
Dept. of Electrical & Computer Engineering, Isfahan University Of Technology, Isfahan, Iran
Ehsan Adib
Dept. of Electrical & Computer Engineering, Isfahan University Of Technology, Isfahan, Iran

Abstract
This paper presents a new structure of single-stage flyback power factor correction (PFC) converter with a controllable coupled negative magnetic feedback (NMF) winding. NMF winding is used to reduce the bulk capacitor voltage at high line voltages and light loads. However, it would cause line current distortion at zero crossing condition. In the proposed circuit, a series winding is used with NMF inductor to eliminate the NMF inductor at low line voltages. As a result, the dead angle of the input current, near zero voltage crossing, is eliminated and the power factor is increased. The presented experimental results of the proposed PFC converter confirm the integrity of the new idea and the theoretical analysis.
Keywords
I. INTRODUCTION
Active power factor correction (PFC) methods have been widely used since harmonic regulations, such as IEC61000-3-2, have been approved. Conventional two-stage PFC converters can provide desirable characteristics, such as high-power factor and low-voltage stress. The disadvantages of this type of PFC converter are complexity and high number of elements. Therefore, this type is usually applied for high-power applications. Single-stage PFC (S 2 PFC) converters are introduced for cost-effective conditions. In these converters, output voltage regulation and current shaping are achieved by using only one control circuit. An internal bulk capacitor ( Cb ) is used to compensate the instantaneous difference between the varying input power and a constant output power. Therefore, the voltage across the bulk capacitor is not controlled. This condition occurs particularly when the input current shaping part operates under discontinuous conduction mode (DCM), whereas the DC/DC part operates under continuous conduction mode (CCM). At light load condition, the voltage across the bulk capacitor increases. At light load conditions, with 220 V ac to 240 V ac input voltage, the capacitor voltage can be above the desirable voltage, 450 V DC , which makes the single-stage design impractical for applications with a universal input voltage range. Different methods are presented to reduce high bulk capacitor voltage stress [1] - [4] . Variable frequency control (VFC) reduces the bulk capacitor voltage stress [5] . However, VFC cannot effectively reduce the bulk capacitor voltage below 450 V DC , even with wide frequency variation range, which is not desirable for the magnetic component and EMI filter design. Another solution is to operate both the input current shaping and the DC/DC stage in DCM, in which the independence of the bulk capacitor voltage from the load is achieved [6] . However, compared with the efficiency in CCM operation of the DC/DC stage, the efficiency in DCM is reduced because of high conduction losses. When operating the DC/DC stage in the CCM/DCM boundary mode, the switching losses is reduced but the switching frequency increases at light load condition [7] , [8] . Fig. 1 shows a conventional single-stage boost-flyback PFC converter with the addition of a second primary winding NNMF in series with diode D2 [9] .
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Conventional single-stage flyback PFC with NMF inductor.
By using NNMF winding, when the switch is turned on, the induced voltage across NNMF would reduce the effective voltage across Lb . Thus, a large duty cycle is necessary to keep the same volt-second product across Lb . Since the output voltage is constant, the voltage Vb is reduced with a large duty cycle. In addition, part of the input energy is directly transferred to the output through the coupled windings NNMF and Ns . Since the extra primary winding voltage has opposite polarity with respect to the rectified input voltage during the switch switch-on interval, this winding is called negative magnetic feedback (NMF). Because the input voltage is a sinusoid waveform, a dead angle exists in the input current when the input voltage becomes lower than the feedback voltage on LNMF , which decreases the power factor. An auxiliary switch can be used to eliminate the dead angle problem. This solution improves the power factor, but increases the cost of the components at the same time [10] , [11] . In such a circuit, the auxiliary switch current is high and equal to the main switch. However, in the proposed PFC presented in the current paper, an auxiliary switch is in series with the control winding circuit. Thus, the peak current and average current of the auxiliary switch are very low because of the turn ratio between the control and NMF winding and the low-duty cycle of the auxiliary switch.
A new structure based on NMF winding without dead angle of input current is proposed in this paper. As explained, using NMF inductor results in line current distortion near the zero crossing voltage because the line current cannot flow when the instantaneous line voltage is lower than the voltage induced across LNMF . If NMF is eliminated at low line voltages, line current can flow even at very low line voltages. Although it should be noted that at high line voltages, NMF inductor is necessary to limit Vb particularly at light load condition [10] - [12] .
In the proposed PFC, a series winding is used with NMF winding to eliminate NMF winding effect at low line voltages. The series winding is coupled in the opposite direction with NMF winding. Thus, the effect of NMF winding induced voltage during zero crossing distortion is eliminated. At high line voltages, the coupling between series winding and NMF winding is eliminated by disconnecting the control winding, which is the interface of the coupling. Therefore, NMF winding would reduce the boost inductor charging current when the main switch is on, and series winding acts as a series inductor with NMF winding. Using this method reduces the dead angle of input current near zero voltage crossing caused by the NMF winding and increases the power factor.
II. CONTROLLABLE COUPLED INDUCTORS
In this paper, a new structure of controllable coupled inductors is proposed, as shown in Fig. 2 . The coupled inductors are implemented by using two U cores and three windings, namely, NMF winding ( NNMF ), control winding ( NC ), and compensation winding ( NCMP ). NC is wound commonly on both legs of the inner part of the cores in the opposite direction. According to the fact that total ampere-turn products for each core is 0,
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Controllable coupled windings, NMF, and CMP with the control winding on the center leg (a) with cross winding and (b) with separate winding.
Thus,
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and
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If
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then
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The following relation is obtained because of the coupling between windings, NNMF and NC (right leg):
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Short circuiting the control winding obtains 0 as the voltage across the NC (left leg);
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Thus,
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Moreover, given that the coupling between windings, NCMP , and NC (left leg),
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According to (9), opposite voltages are produced in both legs of control winding because of the short circuit condition of control winding. Thus, the polarity of the voltage induced in CMP winding is opposite the voltage of NMF winding. As a result, the total voltage across both windings, NNMF and NCMP , is 0, and these two series windings act as short circuit.
The block diagram of the proposed single-stage PFC with controllable coupled inductors is shown in Fig. 3 . The coupling of the two windings, NNMF and NCMP , is controlled by the control winding connection. The control circuit includes the switch Saux , the input voltage sensing circuit, and NC winding connection control circuit.
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Block diagram of the proposed single-stage PFC with controllable coupled inductors, LNMF, and NCMP.
At high line voltages, switch Saux is turned off, thereby opening the control winding, NC . Therefore, no current exists through winding NC . Thus, the windings NNMF and NCMP do not have any coupling with each other, and NCMP acts as a series inductor with NNMF winding as shown in Fig. 4 (a). Consequently, NMF winding compensates the variation of bulk capacitor voltage caused by load variation.
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Equivalent circuit of the proposed single stage PFC. (a) At high line, NCMP acts as serried inductor with LNMF. (b) At low line, NCMP acts as oppositely coupled inductor with LNMF.
At low line voltages, switch Saux is turned on, and the NMF winding flux flows through the control winding NC , thereby inducing a magnetic flux φc in two U cores in the same direction. According to the winding structure of NNMF and NCMP , the control winding NC is coupled with them, and the voltage induced on the windings NNMF and NCMP is the same in amplitude but with opposite polarity. Consequently, VCMP = − VNMF , as shown in Fig. 4 (b). Thus, the combination of these two series inductors acts as a short circuit. Therefore, NMF inductor is eliminated by series combination with NCMP . Consequently, the charge current branch of the boost inductor does not include NMF inductor. Thus, the dead angle of input current is reduced to 0, which is the same as the state where no NMF winding exists in the charging path of the boost inductor. With the dead angle elimination, the input peak current reduces and decreased THD is achieved.
The turn-on signal for switch Saux is generated with a comparator, which compares the scaled rectified line voltage K . Vin(rect) with the reference voltage Vref . Voltage Vref is equal to the induced voltage on the NMF winding, when the main switch is closed. Saux is turned on to bypass NMF winding when the instantaneous scaled rectified line voltage is lower than the reference voltage, which occurs near the 0 crossing of the line voltage.
This technique has no significant effect on the main switch voltage stress, because the maximum voltage stress of the switch is affected from output voltage in both cases. This is due to the fact that the main switch voltage stress bases on the flyback part of the converter, not on the boost part of the converter. However, the main switch current waveform is affected only at low line voltages, because the current of the auxiliary circuit passes through the main switch. Thus, the main switch current increases at low line voltages, wherein the current is not high. At any rate, the peak of switch current is not affected. The switch peak current is equal to
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where d is the converter duty cycle, TS is the switching cycle time, and VCb is the bulk capacitor voltage.
III. DESIGN CONSIDERATIONS
- A. NMF Inductance (NNMF) Design
The single-stage flyback PFC converter operates like a conventional flyback converter when NNMF / NPrimary is greater than or equal to 1, because according to Fig. 1 , diode D2 is off when the switch is on in this condition.
However, in the single-stage flyback PFC converter, diode D2 should conduct and diode D1 should be reverse biased when the main switch Qm is on. Thus,
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Therefore, for proper operation of single-stage flyback PFC converter, the turn ratio of NNMF / NPrimary must be chosen less than 1. Changing the NNMF / NPrimary turn ratio changes the dead angle of the input current. A smaller NNMF / NPrimary would provide better power factor and smaller input current dead angle. However, the bulk capacitor voltage and switch voltage stress increase. Thus, NNMF / NPrimary turn ratio should not be chosen too small. In general, an NNMF / NPrimary turn ratio of approximately 0.5 is sufficient. With this value, a good trade-off among the bulk capacitor voltage, switch voltage stress, input current dead angle, and current harmonic distortion can be achieved. The proposed converter is in Class D harmonic current limit category. With turn ratio NNMF / NPrimary of 14/29, the converter not only complies with EN61000-3-2 Class D harmonic current limits but also controls the bulk capacitor voltage, such that the capacitor voltage would be below the desirable voltage, 450 V DC . According to (4), NCMP is equal to NNMF .
The dead angle of the input current should be calculated near 0 voltage crossing. The auxiliary switch ( Saux ) is closed at zero crossing. Thus, according to Fig. 4 (b), the input current flows if
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Thus, the input current dead angle is equal to
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Thus, with increasing the NMF inductance, the ratio of LNMF / Lpri = NNMF / Npri is increased, and the input current dead angle would increase. Fig. 5 shows the plot of power factor versus the dead angle ( Θdead ).
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Plot of power factor, versus the dead angle Θdead).
- B. Magnetizing Inductance (LM) Design
The average output power of a flyback DCM converter is derived by using the following [10] :
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where LM is the magnetizing inductance of the flyback transformer, fS is the switching frequency, d is the converter duty cycle, and VCb is the bulk capacitor voltage.
According to the PFC parameters in Table I , Pout = 120 W, η = 90%, fS = 50 KHz, VCb = 120 V, and d = 60%. The magnetizing inductance of the flyback transformer ( LM ) is obtained from (14) 388 μH and is chosen to be 400 μH.
PFC PARAMETERS
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PFC PARAMETERS
According to the power of the converter, the power of flyback transformer is approximately 120 W. NC winding operates for a short period (approximately 10% of whole period). Thus, NC winding does not considerably affect the flyback transformer power, and EE2525 ferrite core (with 0.5 mm air gap to achieve increased saturation point) is used for this power [13] . All transformer windings are wound in four layers to reduce leakage inductances.
- C. Controllable Inductance (NC) Design
One of the advantages of this technique is the controll of the current of the auxiliary switches. The turn ratio of NC / NNMF should be reduced to reduce current stress of auxiliary switches. The turn ratio of NC / NNMF of approximately 0.5 provides a good trade-off between the auxiliary switch current and voltage stress.
According to Equation (9), VNMF and VCMP would not become exactly equal by decreasing the coupling coefficient of NCMP and NC . Thus, the total harmonic distortion increases. The simulation demonstrates that the total harmonic distortion increases by decreasing the coupling coefficient of NCMP and NC . However, this increase is not high and is approximately 5% of the full range of practical coupling coefficient variation (0.90 to 0.99). Fig. 6 shows the plot of THD versus coupling coefficient of NCMP and NC .
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Plot of THD versus coupling coefficient of NCMP and NC.
The power processed with auxiliary transformer ( Paux ) is equal to
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where NC1 is the right leg of control winding, which is coupled by NMF winding, whereas NC2 is the left leg of control winding, which is coupled by CMP winding.
According to PFC parameters in Table I , the power processed with auxiliary transformer ( Paux ) is approximately 20 W, and EE1515 ferrite core is used for this power given that the auxiliary transformer acts in a short period (approximately 10% of the entire period) [13] .
- D. Bulk capacitor design
The bulk capacitor is used to compensate the instantaneous difference between the varying input power and the constant output power. Thus, its capacity should be large enough to compensate this large power difference. With smaller capacitor, the voltage of bulk capacitor changes rapidly and would increase to balance the difference between the input and the output power. Decreasing the bulk capacitor capacity to 470 μF would double the bulk capacitor ripple. Thus, the harmonic distortion of input current would increase.
The bulk capacitor voltage (DC bus voltage) is a function of the input voltage, the ratio of inductances Lb / LM , the turn ratio of NNMF / Npri , and the output voltage [14] . DC bus voltage increases with increasing input voltage from low line to high line voltage. However, the NMF inductance controls its voltage, such that the DC bus voltage is kept below the desired voltage, 450 V DC , at the full range of the input voltage from low line to high line voltage. This finding can be observed from the simulation results, which are presented in Fig. 7 .
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Plot of DC bus voltage (VCb) versus input voltage (Vin).
IV. CONTROL CIRCUIT
Fig. 8 shows the schematic of the single-stage PFC flyback converter by using controlled coupled inductors. The rectified input voltage is sensed by a circuit, including diodes D4 , D5 , zener diode Z1 , capacitor C1 , and transistor Q1 . MOSFETs Sa and Sb are connected in series with the control winding NC . When the input voltage increases above the value that is determined by VNMF , the voltage across the capacitor C1 turns the zener diode Z1 on only at high line voltages where rectified input voltage is higher than VNMF . When Z1 is turned on, switch Q1 is turned on. Thus, the gate voltage of MOSFETs Sa and Sb are 0, and they are turned off. Thus, the control winding current reduces to 0, and the coupling between NNMF and NCMP is eliminated.
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Schematic of the proposed single stage PFC with conjugated controllable inductors, NNMF and NCMP.
At low line, where the rectified input voltage is lower than VNMF , the voltage across capacitor C1 is lower than the breakdown voltage of Z1 , and Q1 is turned off and MOSFETs Sa and Sb are turned on. Therefore, the coupling between the three windings, NC , NNMF and NCMP , is established. Series combination of MOSFETs Sa and Sb makes both directions of current in the auxiliary circuit possible. The direction of control winding flux causes the voltages across LNMF and LCMP to be in opposite directions. Thus, the series combination of LNMF and LCMP acts as short circuit.
Fig. 9 shows the detailed schematic of the control and gate drive circuits for main and auxiliary switches.
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Schematic of control and gate drive circuits for main and auxiliary switches.
Two series-connected MOSFETs are used because the current of the auxiliary circuit is in both directions. This condition occurs because of the coupling between one of the auxiliary circuit windings with flyback transformer. The series-connected MOSFETs are actually source connected. However, the gate drives are opto-isolated to have a stable control loop. Thus, the gate drives could have been used even for drain-connected MOSFETs.
Controller IC is SG3525. Moreover, any feedback is unnecessary from the input voltage or current waveforms because of inherent PFC of flyback-boost PFCs.
According to Fig. 8 , the reference voltage (the break down voltage of Z1 ), which is compared with K . Vin , is constant. Increasing the amplitude of the input voltage ( Vin ) changes the auxiliary switches the turn-on angle. Thus, the total harmonic distortion increases. The simulation demonstrates that the total harmonic distortion increases by increasing the input voltage from low line to high line voltage. However, this increase is not high and is approximately 8% for the full range of input voltage variation. Fig. 10 shows the plot of THD versus input voltage ( Vin ).
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Plot of THD versus input voltage (Vin).
V. EXPERIMENTAL RESULTS
The proposed single-stage PFC flyback using conjugated controllable inductors is simulated by using computer and then implemented to verify the operation, analytical analysis, and performance of the proposed circuit. The PFC is designed to operate at 120 W and 100 V DC output. The circuit parameters are listed in Table I , and the components used for implementation of the circuit are listed in Table II and shown in Fig. 11 .
LIST OF KEY COMPONENTS
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LIST OF KEY COMPONENTS
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Implemented schematic of the proposed single-stage PFC with controllable coupled inductor LCMP.
Fig. 12 shows the input current waveform. A complete period of ILb current without and with compensated series inductor is shown in Figs. 12 (a) and 12 (b), respectively. The dead time of input current in the proposed single-stage PFC with NMF and without compensated series inductor is approximately 1 ms, which is approximately 10% of ILb period [ Fig. 12 (c)]. Applying series CMP winding with NMF winding reduces the dead angle to 0.01 ms (0.1% of ILb period), as shown in Fig. 12 (d). Fig. 12 (e) illustrates that the voltage of CMP winding is opposite that of NMF winding voltage, and they can eliminate each other. The THD of the PFC is approximately 12%.
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Experimental results of the proposed single-stage PFC. (a) ILb without controllable coupled inductors; (b) ILb with controllable coupled inductors; (c) scaled ILb without controllable coupled inductors; (d) scaled ILb with controllable coupled inductors; (e) blue color line: VCMP, red color line: VNMF.
VI. CONCLUSION
A single-stage flyback PFC with a controllable coupled NMF winding is presented in this paper. NMF inductor is used in series with the boost inductor to reduce the bulk capacitor voltage at light load condition. A new structure of coupling between the NMF and compensation (CMP) windings is used with a common control winding to overcome the problem of input current dead angle. CMP and NMF windings are coupled in opposite directions at low line voltages. Thus, no NMF winding exists in the boost inductor charge current branch, and zero crossing distortion is eliminated at low line. At high line voltage, the coupling between CMP and NMF is eliminated. Thus, NMF winding reduces the bulk capacitor voltage. Experimental results obtained from a 100 V/100 W circuit shows that the proposed PFC converter achieves the dead time of 0.01 ms for universal input voltage.
BIO
Mohammad Mehdi Tavassol was born in Isfahan, Iran, in 1975. He received his B.S. and M.S. degrees in Electrical Engineering from Isfahan University of Technology (IUT), Isfahan, Iran, in 1997 and 2000, respectively. He is currently working toward his Ph.D. in Electrical Engineering at Isfahan University of Technology (IUT), Isfahan. His research interests include soft-switching techniques in DC–DC converters and power factor correction converters.
Hosein Farzanehfard was born in Isfahan, Iran, in 1961. He received his B.S. and M.S. degrees in Electrical Engineering from University of Missouri, Columbia, Missouri, in 1983 and 1985, respectively, and his Ph.D. degree from Virginia Tech., Blacksburg, in 1992. Since 1993, he has been a faculty member of the Department of Electrical and Computer Engineering, Isfahan University of Technology, Isfahan, Iran. He is the author of more than 100 papers published in journals and conference proceedings. His research interests include high-frequency soft-switching converters, pulse power applications, power factor correction, active power filters, and high-frequency electronic ballasts.
Ehsan Adib was born in Isfahan, Iran, in 1982. He received his B.S, M.S, and Ph.D. degrees in Electrical Engineering from Isfahan University of Technology, Isfahan, Iran, in 2003, 2006, and 2009, respectively. He is currently a faculty member of the Department of Electrical and Computer Engineering, Isfahan University of Technology. He is the author of more than 50 papers published in journals and conference proceedings. His research interests include DC–DC converters and their applications, and soft-switching techniques.
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