This paper presents a method of designing optimal integer and fractionalorder proportional–integralderivative (FOPID) controllers for a boost converter to gain a set of favorable characteristics at various operating points. A Paretobased multiobjective optimization approach called strength Pareto evolutionary algorithm (SPEA) is used to obtain fast and low overshoot startup and dynamic responses and switching stability. The optimization approach generates a set of optimal gains called Pareto set, which corresponds to a Pareto front. The Pareto front is a set of optimal results for objective functions. These results provide designers with a tradeoff lookup table, in which they can easily choose any of the optimal gains based on design requirements. The SPEA also overcomes the difficulties of tuning the FOPID controller, which is an extension to the classic integerorder PID controllers and potentially promises better results. The proposed optimized FOPID controller provides an excellent startup response and the desired dynamic response. This paper presents a detailed comparison of the optimum integer and the fractionalorder PID controllers. Extensive simulation and experimental results prove the superiority of the proposed design methodology to achieve a wide set of desired technical goals.
I. INTRODUCTION
Control of DC–DC converters has been of particular interest in the last two decades
[1]

[4]
. From the control point of view, nearly all the power conversion systems are regarded as a tracking problem because the output quantity should follow the reference command with a fast transient behavior and a low steadystate error. Most of these systems are inherently time varying, uncertain
[5]
,
[6]
, have a nonminimum phase, and are nonlinear with some possible complex behavior like chaos
[7]
,
[8]
. The most popular method for modeling DC–DC converters is state space averaging. State space averaging provides an approximate linear timeinvariant (LTI) model
[2]
,
[9]
,
[10]
. This model does not adequately predict a large signal behavior of the converters. Accordingly, limited linear control approaches are designed based on the nonlinear model of the converter. These approaches cannot normally guarantee an optimized large signal behavior, including the startup regime. Even advanced linear control approaches, such as
H
^{∞}
[11]

[13]
, μ
[14]

[17]
, and Hammerstein modelbased control
[3]
,
[18]
cannot guarantee a fast and low overshoot response in the startup period
[1]
. One solution is using nonlinear and intelligent controllers, such as fuzzy controllers. Implementing these controllers is harder than implementing linear controllers, especially in the digital domain
[19]

[24]
.
Other linear solutions, such as the linear quadratic regulator
[25]
, linear quadratic Gaussian
[26]
,
[27]
, and quantitative feedback theory
[28]
, which are designed based on the linearized model of the converter, are not appropriate choices for large signal conditions. However, these solutions overcome the model uncertainties of the converters
[5]
,
[6]
. Another design difficulty based on the LTI model is that the calculated LTI model depends on the operating point of the converter. Any change in the reference command, load parameters, or input DC voltage may alter the operating condition of the system. Consequently, this change alters some parameters of the corresponding LTI model
[29]
.
The closed loop DC–DC power converter may exhibit complex and chaotic behavior in some cases
[30]

[35]
. This chaotic behavior is undesirable because it may result in lowquality output signal and undesirable acoustic noise
[36]
. Such a complex behavior and the existence of various major sources of uncertainty make the controller design task difficult. The results from Ref.
[1]
indicate that a linear controller may not be useful in overcoming switching instability.
Linear controllers are prevalently used in industrial applications because implementing them is straightforward. Attempts to improve the quality and robustness of the PID controllers have been continuously conducted
[37]
. Using fractionalorder controllers with noninteger derivation and integration parts is one method of improving the traditional PID controllers. However, the difficulties of designing fractionalorder PID (FOPID) compared with traditional PID controllers are relatively higher because FOPID controllers include derivative and integrated orders as design parameters
[38]
. Using the FOPID controller may provide better robustness for a linear system if the dynamic characteristics are basically the same using either integerorder PID controller or FOPID controller
[39]
. The conventional FOPID controller tuning methods are regularly based on estimating the order of fractional calculus using experience first, and then tuning other parameters according to the tuning methods of the integerorder controllers. The designed controller acquires better results than integerorder controllers. However, the efficiency is still relatively low. Furthermore, these tuning methods may fail to achieve the global optimal solution
[40]
.
An evolutionary approach such as the genetic algorithm with a proper objective function is a good approach in designing an integer or fractionalorder PID controller for a nonlinear and complex system. However, selecting an appropriate objective function is critical. Traditionally used objective functions, such as integral of the squared error and integral of time multiplied by absolute error, may not lead to a favorable response because they do not represent the output desired characteristics (e.g., overshoot and settling time) in an explicit manner. Therefore, several modifications in the objective function through trial and error may be required.
First, this paper aims to design a simple PID controller to gain an optimized transient, steadystate response, and switching stability for various operating points using the SPEA multiobjective optimization approach
[41]
. This approach is based on the Pareto optimality concept used in game theory literature. Settling time, overshoot, dynamic response, robustness, and switching stability are employed as objective functions. The gains of the PID controller (i.e.,
K_{p}
,
K_{i}
, and
K_{d}
) and the maximum and the minimum of the modulator harder are the design variables. Second, this paper implements the SPEA to design the FOPID controller. The FOPID controller design is considered a real parameter optimization problem in a fivedimensional hyperspace. This paper concludes with a comparison of the results of the optimized integer and the FOPID controller.
II. MULTIOBJECTIVE OPTIMIZATION
A general multiobjective problem is represented as follows:
Subject to
where x, X, y, and Y are the decision vector, parameter space, objective vector, and objective space, respectively.
Evolutionary algorithms (EAs) are often well suited for optimization problems that involve several, often conflicting objectives. The EAs are divided into three major categories
[41]
.
The first category is based on plain aggregating approaches, which combine the desired goals of the optimization problem, construct a scalar function, and use a common scalar optimization approach to solve the problem. The major problem of these methodologies is the unavailability of any straightforward methods for combining the objectives or goals of the problem. However, its advantage is its simplicity and its ability to produce a single solution.
The second category is the populationbased nonPareto approaches, where the search is guided in several directions at the same time by changing the selection criterion during the reproduction phase. The fraction of the mating pool in this type is selected according to one of the objectives or multiple linear combinations of the objectives in parallel. Some advanced approaches in this category are as follows:

 Hajela’s and Lin’s genetic algorithm[42]

 Vectorevaluated genetic algorithm[43]
The last category is the Paretobased approaches, which use the Pareto dominance to determine the reproduction probability of each individual.
According to the definition of the Pareto dominance, vector
a
in the search space dominates vector
b
if
b
is called dominated if at least one vector dominates
b
and called nondominated, otherwise. Each nondominated solution is regarded optimal in the sense of Pareto or called Pareto optimal. One is obviously the best in terms of one of the objectives between any pairs of points on a Pareto set. The set of all nondominated solutions is called the Pareto optimal set. The set of the corresponding values of the objective functions is called the Pareto optimal front (POF) or simply, the Pareto front. Some advanced Paretobased evolutionary methods are as follows:

 niched Pareto genetic algorithm[44]

 nondominated sorting genetic algorithm[45]

 SPEA[41]
The SPEA integrates established techniques used in the existing Paretobased EAs in a single unique algorithm. Its convergence to the Pareto optimal front and preserving the population diversity are its advantages over other EAs
[41]
.
 A. SPEA
A flowchart of the approach including the following major steps is presented in
Fig. 1
[41]
:
SPEA:

1. generating an initial population P and creating the empty external nondominated set P′;

2. pasting nondominated members of P into P′;

3. removing all solutions within P′, which are covered by any other members of P′;

4. pruning P′ by clustering if the number of externally stored nondominated solutions exceeds a given maximum N′;

5. calculating the fitness of all individuals in P and P′;

6. using binary tournament selection with replacement and selecting individuals from P and P′ until the mating pool is filled;

7. applying crossover and mutation operators;

8. stopping if the maximum number of generations is reached, and repeating step 2, otherwise.
Optimization flowchart of the strength Pareto.
Fitness assignment is performed using the two following steps:

 strength 0 ≤ Si <1, which is equal to the following value, is considered for every individual (i) of P′:
where
N
is the size of P, and
n
is the number of individuals in P dominated by individual (
i
) of P′. The fitness of (
i
) is equal to
S_{i}
.

 Fitness (fj) is equal to the following value for every individual (j) of P:
Small fitness values correspond to high reproduction probabilities. Hence, 1 is added to sum up the strengths of P′ individuals that dominate
j
. The members of P′ have better fitness than the members of P.
The major point of clustering is that the point with a minimal average distance to all other points in a cluster is considered the representative for that cluster
[41]
.
III. FRACTIONAL SYSTEMS
 A. Fractional Calculus
Fractionalorder systems are characterized by the fractionalorder differential equations. Fractional calculus considers any real number for derivatives and integrals. The FOPID controller is the expansion of the conventional integerorder PID controller based on fractional calculus.
Fractional calculus is a branch of mathematics that deals with real number powers of differential or integral operators. The following definition, which was proposed by Riemann and Liouville, is the most common among all the different definitions
[46]
:
The general definition of D is presented by Eq. (6) as follows:
where Γ(∙) is the wellknown Euler’s gamma function.
 B. Approximation of the FractionalOrder Derivative and Integral
The functions used in this section provide an integerorder frequencydomain approximation of transfer functions that involve the fractional powers of
s
.
The following equation is obtained for the frequencydomain transfer function C(s) given by Eq. (7) as follows:
Crone is a wellknown continuous approximation approach. Crone is a French acronym that means “robust fractionalorder control.” This approximation implements a recursive distribution of
N
zeros and N poles, which leads to a transfer function as Eq. (8):
where
K′
is an adjusted gain so that both Eqs. (7) and (8) have a unit gain at 1 rad/s. Zeros and poles have to be over a frequency domain [
w
_{l}
;
w
_{h}
] with a valid approximation. These zeros and poles are given for a positive v by Eqs. (9)–(11) as follows:
where
α
and
η
are calculated according to Eqs. (12) and (13).
The roles of zeros and poles are swapped for negative
v
values. The number of poles and zeros is initially selected. The desired performance of this approximation depends on the order
N
. A simple approximation is provided with a lowerorder
N
, which causes ripples in both gain and phase characteristics. The approximation is not satisfactory when 
v
 > 1. The fractionalorder
v
is usually separated as Eq. (14). Moreover, only the first term
s^{v}
needs to be approximated.
 C. Fractional PID Controller
Researchers found that controllers, which use fractionalorder derivatives and integrals, achieve better performance and robustness than conventional integerorder controllers
[47]
. The FOPID controller is more flexible and provides an opportunity for a better adjustment of the dynamical characteristics of the control system.
The FOPID controller, which is proposed by Podlubny in 1999, is the expansion of the conventional PID controller based on fractional calculus
[48]
,
[49]
.
The general form of the FOPID controller is PI
^{α}
D
^{β}
. Its general transfer function is given by Eq. (15) as follows:
Aside from selecting
K_{p}
,
K_{i}
, and
K_{d}
, this controller needs to select
α
and
β
, which are not necessarily integer numbers
[50]
,
[51]
.
IV. PID CONTROLLER FOR BOOST CONVERTER
The studied DC–DC converter (
Fig. 2
) is a boost converter with a switching frequency equal to 15 kHz that converts a 5 V input supply to a 12 V output.
Table I
presents the prototype circuit parameters. The parameters are similar to those used in Ref.
[24]
for easy comparison of results. The standard statespace averaging technique is usually used to obtain the outputtocontrol smallsignal transfer function. However, the controller design based on this mathematical model cannot provide the best performance because of a significant model error. Ref.
[24]
proposed a transfer function for the studied boost converter based on the measured experimental frequency response. This transfer function [Eq. (16)] is referred to in this part because it is more accurate than the theoretical one. The frequency response of the transfer function is presented in
Fig. 3
(a).
Boost converter.
CIRCUIT PARAMETERS OF THE BOOST CONVERTER
CIRCUIT PARAMETERS OF THE BOOST CONVERTER
Frequency response of the boost converter: (a) open and (b) closed loops [24].
The PID controller designed based on the measured smallsignal model in Eq. (16) is presented in Eq. (17) as follows:
The Bode plot of the PIDcompensated boost converter is illustrated in
Fig. 3
(b). The gain crossover frequency of the PIDcompensated system is approximately 290 Hz, while the phase margin is 50°. The startup response obtained using this PID controller is presented in
Fig. 4
. The settling time is 0.019 s, while the overshoot is 18%. Neither of the two values is satisfactory.
Startup response of the boost converter with the PID controller proposed in Ref. [24]
V. PID CONTROLLER OPTIMIZATION
The flowchart in
Fig. 1
is used to optimize the PID controller.
Table 2
presents the optimization parameters. The program is conducted using mfile in MATLAB. The objective functions are calculated in SIMULINK using the details of the system. Consequently, this method reduces the approximation error in the mathematical model. The parameters are sent to the SIMULINK environment so each member of each generation obtains the objective functions. The values of the objective functions are returned to the program after the simulation running time is finished.
SPECIFICATIONS OF THE EVOLUTIONARY ALGORITHMS
SPECIFICATIONS OF THE EVOLUTIONARY ALGORITHMS
The SPEA algorithm runs until the stop condition is satisfied. The members of P′ in the last iteration are the optimized parameters.
 A. LargeSignal Response Optimization
The program used to optimize the largesignal response (i.e., startup response) with the PID gains (i.e.,
K_{p}
,
K_{i}
, and
K_{d}
) as design variables generates a set of optimal gains called the Pareto set (
Fig. 5
and
Table III
). The Pareto set corresponds to a set of optimal results for the objective functions called the Pareto front (
Fig. 6
).
Pareto set (i.e., PID coefficients).
PARETO SET (I.E., PID CONTROLLER COEFFICIENTS) AND PARETO FRONT (I.E., SETTLING TIME AND OVERSHOOT)
PARETO SET (I.E., PID CONTROLLER COEFFICIENTS) AND PARETO FRONT (I.E., SETTLING TIME AND OVERSHOOT)
Pareto front.
The cost functions for this optimization are as follows:

F1= Overshoot =100%

F2= Settling time =mṅ{t:e(t) < 1.5%}
where
y
is the output voltage, and
e
is the tracking error in percent. The desired output is 12 V.
A designer can easily select any of the results based on their features and his/her own engineering view. Some results are given in
Fig. 7
. Some have low overshoot but high settling time, whereas others have low settling time but high overshoot. The fastest among these optimal responses provides an 8.4 ms settling time and causes a high overshoot of 27.4%. However, these values are all optimum in the sense of the Pareto optimality criterion.
Some startup responses selected from the Pareto front (Table 3): (a), (b), (c), (d), and (e) correspond to points 5, 13, 9, 14, and 11, respectively.
Aside from the largesignal behavior, smallsignal response is also important. Hence, the dynamic behavior of the output voltage to the step change of the input supply for one of these optimal PID gains is evaluated. The satisfactory dynamic response is depicted in
Fig. 8
. Taking the dynamic response characteristics as additional objective function(s) is also possible. Accordingly, both large and smallsignal responses are optimized at the same time using a simple PID controller. This optimization is discussed in the next section.
Smallsignal behavior of the converter with the Paretobased PID controller when a change occurs in the 5 V to 6 V input voltage (i.e., the PID gains are based on point 13 in Table III).
Some interesting information, which helps in creating an efficient design, is obtained from the Pareto front. Accordingly, a jump on the Pareto front is important. For example, that the two points cause a nearly identical overshoot (around 8%) is determined by comparing the two points marked in the Pareto front (
Fig. 9
). However, the lower point provides nearly a 50% faster settling time. Hence, from the practical point of view, the lower point provides better results if the overshoot is acceptable.
Comparison of two different points of the Pareto front.
 B. Large and Dynamic Response Optimization
Dynamic response and large signal are important for some applications. The dynamic response is added as an additional objective function to the previous optimization process. In addition to the large signal, the smallsignal response of the converter to a 20% increase in the input voltage at 0.15 s is defined as an optimization objective. The Pareto set and the Pareto front obtained from the optimization are presented in
Table IV
. The cost functions in this part are as follows:

F1: Overshoot =100%

F2: Settling time =mṅ{t:e(t) < 1.5%}

F3: Dynamic overshoot =100%
PARETO SET (I.E., PID COEFFICIENTS) AND PARETO FRONT (I.E., SETTLING TIME, OVERSHOOT, AND DYNAMIC RESPONSE)
PARETO SET (I.E., PID COEFFICIENTS) AND PARETO FRONT (I.E., SETTLING TIME, OVERSHOOT, AND DYNAMIC RESPONSE)
One set of the PID coefficients suggested by
Table 4
is selected according to the required features of the converter output response. The PID coefficient is
K_{p}
= 0.6509,
K_{i}
=75.1074, and
K_{d}
= 0.0021 if the startup overshoot, settling time, and dynamic overshoot must be below 15%, 0.03 s, 1.5%, respectively. This response is depicted in
Fig. 10
.
One of the dynamic response optimization results in addition to the largesignal optimization selected according to the design requirements (point 8 in Table IV).
 C. Largesignal Response Optimization with More Variables
The dynamic response is not considered an optimization objective in this program. However, these results also obtain satisfactory dynamic responses. The output voltage has a negligible overshoot when a 20% step increase in the input voltage occurs at 0.05 s (
Fig. 13
).
The max and min bounds of the hard limiter used to limit the duty cycle are added to the optimization variables, whereas the cost functions remain the same to improve the largesignal response.
Table V
and
Fig. 11
present the Pareto set and the Pareto front for this optimization program. The startup response of these results is given in
Fig. 12
to illustrate the significant improvement achieved using this optimization. All the points on the POF in
Fig. 11
dominate the points on the POF in
Fig. 6
.
PARETO SET (I.E., PID COEFFICIENTS AND MAX AND MIN OF THE HARD LIMITER) AND PARETO FRONT (I.E., SETTLING TIME AND OVERSHOOT)
PARETO SET (I.E., PID COEFFICIENTS AND MAX AND MIN OF THE HARD LIMITER) AND PARETO FRONT (I.E., SETTLING TIME AND OVERSHOOT)
Pareto front.
Responses of the Pareto front with the max and min hard limiter and the PID controller coefficients as optimization variables.
Smallsignal behavior of the converter with the Paretobased PID controller (max and min of the hard limiter optimization in addition to PID coefficients) when a step change from 5 V to 6 V occurs in the input voltage at 0.05 s.
 D. Switching Stability and LargeSignal Optimization
The frequency of the output voltage ripples is less than the pulsewidth modulation (PWM) generator signal (
Fig. 14
). The frequency can even be nonperiodic. This phenomenon is called chaos.
Chaotic behavior in the steadystate response of the waveform depicted in Fig. 10. (a) Chaos behavior. (b) Phase plot.
This problem is solved by considering the switching stability as an optimization objective in addition to the settling time and overshoot of the largesignal response. The sum of the errors between every two successive points of error signal sampled synchronized with the PWM clock at a steady state must tend to zero to improve the chaotic behavior.
The cost functions are as follows:
F
_{1}
: Overshoot =
100%
F
_{2}
: Settling time =
mṅ
{
t
:
e
(
t
) < 1.5%}
F
_{3}
:
where
e_{i}
is the error signal at the
i
th switching instance.
Table VI
presents the Pareto set and the Pareto front obtained from this optimization.
PARETO SET (I.E., PID COEFFICIENTS AND MAX AND MIN OF THE HARD LIMITER) AND PARETO FRONT (I.E., SETTLING TIME, OVERSHOOT, AND SWITCHING STABILITY)
PARETO SET (I.E., PID COEFFICIENTS AND MAX AND MIN OF THE HARD LIMITER) AND PARETO FRONT (I.E., SETTLING TIME, OVERSHOOT, AND SWITCHING STABILITY)
Chaos has completely been removed for the first point in Table VI (J
_{p2}
= 0.0000). This response is illustrated in
Fig. 15
. The dynamic response of this point is satisfactory while a load change of 100% is applied to the system (
Fig. 16
). Moreover, the system keeps switching stability after the dynamic response.
Chaos rejection for the (a) largesignal response and the first point of Table 6, (b) phase plot.
Chaotic behavior before and after the 100% load increase (at 0.2 s) for the first point in Table VI.
 E. Startup Optimization for Various Operating Points
Both poles and the righthalfplane zero of the boost converter depend on the steadystate duty cycle. Therefore, the Bode plots for various operating points exhibit a significant variation. A classical PID controller designed based on the frequency response may not respond well to the significant changes in the operating point
[24]
.
The optimization in the previous parts was performed for the nominal operating point. The optimization was conducted for several system operating points to make the system robust for different voltage references. The design variables, PID parameters, and objective functions are considered to have the worst startup response overshoot and settling time. The reference voltage is equal to 10, 11, 12, 13, and 14 V.
Table VII
presents the results of this optimization. The minimum of the hard limiter is set to zero, while the maximum is set proportional to the reference voltage to obtain these results (i.e., maximum of hard limiter = 0.058 * reference voltage). The ratio is estimated using the results in
Table V
.
PARETO SET (I.E., PID COEFFICIENTS) AND PARETO FRONT (I.E., WORST SETTLING TIME AND OVERSHOOT FOR VARIOUS OPERATING POINTS)
PARETO SET (I.E., PID COEFFICIENTS) AND PARETO FRONT (I.E., WORST SETTLING TIME AND OVERSHOOT FOR VARIOUS OPERATING POINTS)
Point one of the Pareto front is presented in
Fig. 17
. This point provides a fast startup response for a wide range of references with nearly no overshoot. A high robustness is achieved using the SPEA algorithm. Similarly, the effect of other disturbance sources in the load and input voltage is considered.
Optimized startup response for five different references (point 1 in Table VII).
VI. OPTIMIZATION OF FRACTIONAL ORDER PID CONTROLLER
 A. Design Parameter and Objective Functions
Five parameters should be designed for the FOPID controller according to the control objectives. The initial members of the first population are represented by 5dimension vectors. These initial values are randomly generated in the defined range.
The optimization stop criterion is based on the maximum number of generations to be produced. Accordingly, 100 generations are used in this paper.
The Crone approximation with an order of 5 and a frequency range equal to [0.01; 1000000] rad/s for FOPID controller is used.
 B. Optimization of StartUp Response
This optimization uses the FOPID coefficients as the design variables. The objective functions are as follows:

F1: Overshoot = Maxy

F2: Settling time = Min t, where error < 1.5%

error =
where
y
is the DC output voltage of the boost converter.
Table 8
shows the results of the SPEA program.
PARETO SET AND PARETO FRONT FOR THE FOPID CONTROLLER AND OPTIMIZATION OF THE STARTUP RESPONSE OVERSHOOT AND SETTLING TIME
PARETO SET AND PARETO FRONT FOR THE FOPID CONTROLLER AND OPTIMIZATION OF THE STARTUP RESPONSE OVERSHOOT AND SETTLING TIME
The results (
Table VIII
) show that the fractionality of the derivation and integration parts of the optimum results is very low but has a significant effect. The startup responses for these results are presented in
Fig. 18
. These simulation results verify the effectiveness of the tuning strategy proposed in this part.
Startup response for results of the Pareto front in Table 8: points (a) 1 and (b) 2.
The Pareto optimization is a useful tool for preference evaluation and parameter selection in the design of power converters. From an engineering perspective, the goal of the optimization is finding the optimal solution, gaining insight on the system properties being designed, and visualizing the tradeoff between them.
 C. Optimization of StartUp and Dynamic Responses
Aside from the characteristics of the startup response, the dynamic response is also considered an objective function in this section. The dynamic response is defined as follows:

F3: Dynamic overshoot = Maxyaftert= 0.2 s.
where the input voltage has a step change from 5 V to 6 V at 0.2 s.
Table IX
presents the results of this optimization.
PARETO SET AND PARETO FRONT FOR FOPID CONTROLLER, OPTIMIZATION OF STARTUP OVERSHOOT, SETTLING TIME, AND DYNAMIC RESPONSE
PARETO SET AND PARETO FRONT FOR FOPID CONTROLLER, OPTIMIZATION OF STARTUP OVERSHOOT, SETTLING TIME, AND DYNAMIC RESPONSE
The fractionality of the results in
Table IX
is notably higher than that in
Table 8
. The designer can design the FOPID controller according to point 5 in
Table IX
if he/she selects the dynamic response as his/her first priority. This response is presented in
Fig. 19
. Point 3 in
Table IX
can be chosen if the startup response has a higher priority considering a compromise between the startup and the dynamic responses as the objective functions. This response is illustrated in
Fig. 20
.
Startup and dynamic responses for point 5 in Table 9. Dynamic response is for a step change in the input voltage from 5 V to 6 V at t = 0.2 s: (a) startup and (b) dynamic responses.
Startup and dynamic responses for point 3 in Table IX. Dynamic response is for a step change in the input voltage from 5 V to 6 V at t = 0.2 s.
The bandwidth of the FOPID controller is changed in this part. This change in the bandwidth ensures that the controller works within a large bandwidth. The other parameters (i.e.,
K_{p}
,
K_{i}
,
K_{d}
,
α
, and
β
) need to be optimized again when the bandwidth is changed. Furthermore, a new optimization is conducted for the [0.01; 40,000] rad/s bandwidth.
Table 10
shows the optimization results for a bandwidth within [0.01; 40,000] rad/s. The startup response of these results is presented in
Fig. 21
.
PARETO SET AND PARETO FRONT FOR THE FOPID CONTROLLER, OPTIMIZATION OF STARTUP OVERSHOOT, SETTLING TIME, AND DYNAMIC RESPONSE, MAXIMUM BANDWIDTHWHOF 40,000 RAD/S
PARETO SET AND PARETO FRONT FOR THE FOPID CONTROLLER, OPTIMIZATION OF STARTUP OVERSHOOT, SETTLING TIME, AND DYNAMIC RESPONSE, MAXIMUM BANDWIDTH W_{H} OF 40,000 RAD/S
Startup response of the results in Table 10: points (a) 1 and (b) 2.
VII. COMPARISON OF INTEGERORDER PID AND FOPID CONTROLLERS
This section presents a comparison of the results of multiobjective optimization for the FOPID and integerorder PID controllers.
 A. Comparison of Pareto front for StartUp Response
The Pareto front of the startup response overshoot and the settling time optimization for the integerorder PID and FOPID controllers is presented in
Fig. 22
.
Comparison of the Pareto fronts for the integerorder PID and FOPID controllers (optimization of the startup response overshoot and settling time).
The FOPID controller provides a much better startup response (
Fig. 22
).
 B. Comparison of the Pareto Front for Dynamic and StartUp Responses
A comparison of
Tables IV
and
IX
clearly indicates that the FOPID controller provides much better results when both the startup and the dynamic responses are objective functions with the startup response as the first priority.
VIII. EXPERIMENTAL VERIFICATION
The proposed PID and FOPID controller coefficients are validated on a boost converter prototype. The passive components and the other converter parameters are similar to those mentioned in Section IV. The discrete control scheme is implemented on a F2812 DSP for the integerorder PID controller and a dSPACE 1104 for the FOPID controller.
 A. LargeSignal Response
The experimental results of the startup response for some points in
Table III
are illustrated in
Fig. 23
. Accordingly, the experimental results are quite close to the corresponding simulation results. The overshoot clearly increases from 7.5% to 30% when the settling time is reduced from 25 ms to 8 ms. One objective function becomes more desirable than the others by scrolling on the Pareto front. All these results are considered optimum, and any other PID coefficients cannot be found on the same conditions, which results in a faster settling time and a lower overshoot than the others.
Startup response for some points selected from Pareto front (Table III): (a), (b), (c), (d), (e) correspond to points 5, 13, 9, 14, 11 respectively.
 B. LargeSignal Response with More Optimization Variables
The simulation results of the optimization of startup response overshoot and settling time, with the PID coefficients and max–min of hard limiter as design variables, have very close overshoots to each other. Given that the difference between them is not significant, for only one point of
Table V
, the startup response is shown in
Fig. 24
. A numerical comparison of the experimental and simulation results of startup response is presented in
Table XI
.
Startup response for point 3 in Table V.
COMPARISON OF THE EXPERIMENTAL AND THE SIMULATION RESULTS
COMPARISON OF THE EXPERIMENTAL AND THE SIMULATION RESULTS
 B. Chaos Rejection
The experimental results for the chaotic behavior of the boost converter are presented in
Figs. 25
and
26
. The chaotic behavior of the boost converter for point 12 in
Table VI
is illustrated in
Fig. 25
. The same behavior obtained based on point 1 in
Table VI
shows 100% chaos rejection (
Fig. 26
). The chaotic behavior is completely removed if other objective functions are not as important as the switching stability.
Chaotic behavior of the output voltage for the boost converter (point 12 in Table VI).
Rejection of the chaotic behavior for the boost converter (point 1 in Table VI).
 D. LargeSignal Response with FOPID Controller
The order of the Crone approximation is 5 for the experimental implementation of the FOPID controller. Furthermore, the bandwidth with a valid approximation is [0.01; 40,000] rad/s.
Table 12
shows the experimental results, while
Fig. 27
presents the startup waveforms. A comparison of
Table 10
and
12
shows that the experimental results effectively confirm the theoretical results.
EXPERIMENTAL RESULTS FOR THE FOPID CONTROLLER
EXPERIMENTAL RESULTS FOR THE FOPID CONTROLLER
Startup response for the results of Table X: points (a) 1 and (b) 2.
IX. CONCLUSION
This study simultaneously optimizes some important features of the boost converter. These features include the largesignal response overshoot and settling time, dynamic response, and switching stability. The SPEA is used to improve these features. A designer can easily choose any of the results based on their features and his/her own engineering view with the help of the Pareto sets and fronts obtained in this paper. SPEA multiobjective optimization is employed to overcome the difficulties of designing the FOPID controller in the second part of the paper. The optimized FOPID controller exhibits a good dynamic response and an excellent startup response. The extensive simulation results verify that the tuning of the PID and FOPID controllers with the use of the SPEA multiobjective approach is highly effective, rejects chaotic behavior, and provides robustness against change in the operating point. Moreover, the experimental results validate the theoretical results that were presented and discussed.
BIO
Ahmadreza Amirahmadi received his B.S. and M.S. degrees in Electrical Engineering from Shahrood University of Technology, Shahrood, Iran, in 2007 and 2010, respectively. He has been a Ph.D. student at the University of Central Florida, Orlando, Florida, USA, since 2010. Since 2010, he has been a research assistant in the Florida Power Electronics Center, University of Central Florida, where he focuses on efficiency optimization of DC/AC inverters. He has been a marketing engineering intern from June 2013 at the International Rectifier. His research interests include highfrequency DC–DC converters, soft switching control of power electronic inverters, and efficiency optimization.
Mohammadreza Rafiei was born in 1969 in Tehran, Iran. He received his B.Sc. degree with honors from the Sistan and Baluchistan University, Zahedan, Iran, in 1991. He obtained his M.Sc. and Ph.D. degrees in Electrical Engineering from the Ferdowsi University of Mashhad, Mashhad, Iran, in 1995 and 2000, respectively. He is a senior member of the IEEE since 2004 and a member of the IEEE Control Systems, Power Electronics, and Power and Energy Societies. His fields of interest includes energy system optimization, control systems, power electronics, and power quality. He serves as a reviewer for several IEEE journals, among other publications.
Kambiz Tehrani was born in Tehran, Iran, in 1978. He received his degree in Electrical Engineering from the University of Arak, Iran, in 2003. He received his master’s degree and his Ph.D. degree from the University of Nancy (INPL), Nancy, France, in 2005 and 2010, respectively. He is currently an associate professor in Power Electronics Systems at ESIGELEC in Rouen, France. His main research interests include energy systems, current control systems, and multilevel inverters.
Giovanni Griva received his fiveyear degree and a Ph.D. degree in Electrical Engineering from the Politecnico di Torino, Torino, Italy in 1990 and 1994, respectively. He joined the Department of Electrical Engineering, Politecnico di Torino, as assistant professor in 1995. He has been an associate professor since 2002. His fields of interest are power electronics conversion, integrated electronic/electromechanical design, highperformance speed servo drives, and applications of power quality issues. He has published over 100 papers in international conferences and technical journals. He was the recipient of the IEEE Industry Applications Society First Prize Paper Award in 1992. He serves as a reviewer for the IET Proceedings and IEEE Transactions on Industrial Electronics.
Issa Batarseh received his B.S. degree in Electrical and Computer Engineering and his M.S. and Ph.D. degrees in Electrical Engineering in 1983, 1985, and 1990, respectively, from the University of Illinois, Chicago. He is currently a professor of electrical engineering in the School of Electrical Engineering and Computer Science, University of Central Florida (UCF), Orlando, FL. He became a visiting assistant professor at Purdue University, Calumet, IN from 1989 to 1990 before joining the Department of Electrical and Computer Engineering, UCF in 1991. His research interests include power electronics, developing highfrequency energy conversion systems to improve power density, efficiency, and performance, the analysis and design of highfrequency solar and wind energy conversion topologies, and power factor correction techniques. He has authored or coauthored more than 60 refereed journals and 300 conference papers in addition to securing 14 U.S. patents. He is also an author of a textbook entitled Power Electronic Circuits (New York: John Wiley, 2003). He is a registered professional engineer in the state of Florida and a fellow member of IEE. He has served as a chairman for the IEEE PESC ‘07 conference and was the chair of the IEEE Power Engineering Chapter and the IEEE Orlando Section.
Rafiei S. M. R.
,
Ghazi R.
,
Asgharian R.
,
Barakati M.
,
Toliyat H. A.
“Robust control of DCDC PWM converters: A comparison of H_inf, Miu, and fuzzy logic based approaches”
in Proc. the IEEE 2003 Control Applications Conference
2003
603 
608
Erickson R. W.
,
Maksimovic D.
2000
Fundamentals of Power Electronics
2nd ed.
Kluwer Academic Publisher
Alonge F.
,
D’ppolito F.
,
Cangemi T.
2008
“Identification and robust control of DC/DC converter Hammerstein model”
IEEE Trans. Power Electron.
23
(6)
2990 
3003
DOI : 10.1109/TPEL.2008.2005034
Beccuti A. G.
,
Papafotiou G.
,
Morari M.
“Optimal control of the DCDC converter”
in Proc. the IEEE Conference on Decision and Control
2005
4457 
4462
LeyvaRamos J.
,
MoralesSaldaa A.
2000
“Uncertainty models for switchmode DCDC converters”
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
47
(2)
200 
203
DOI : 10.1109/81.828573
Garcera G.
,
Abellan A.
,
Figueres E.
2002
“Sensitivity study of the control loops of DCDC converters by means of robust parametric control theory”
IEEE Trans. Ind. Electron.
49
(3)
581 
586
DOI : 10.1109/TIE.2002.1005383
Dean J. H. B.
,
Hamill D. C.
1990
“Instability, subharmonics, and chaos in power electronic systems”
IEEE Trans. Power Electron.
5
(3)
581 
586
Hamill D. C.
,
Dean J. H. B.
,
Jefferies D. J.
1992
“Modeling of chaotic DCDC converters by iterated nonlinear mappings”
IEEE Trans. Power Electron.
7
(1)
21 
36
DOI : 10.1109/63.124574
Middlebrook R. D.
,
Cuk S.
1977
“A general unified approach to modeling switching converter power stages”
Int. J. Electron.
42
(6)
521 
550
DOI : 10.1080/00207217708900678
PerezPinal F. J.
,
Nunez C.
,
Alvarez R.
“Direct voltage control for boost converter”
1st International Conference on Electrical and Electronics Engineering
2004
579 
583
VidalIdiarte E.
,
MartinezSalamero L.
,
ValderramaBlavi H.
,
Guinjoan F.
,
Maixe J.
2003
“Analysis and design of H∞ control of nonminimum phaseswitching converters”
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.
50
(10)
1316 
1323
DOI : 10.1109/TCSI.2003.816337
Naim R.
,
Weiss G.
,
BenYaakov S.
1997
“H∞control applied to boost power converters”
IEEE Trans. Power Electron.
12
(4)
677 
683
DOI : 10.1109/63.602563
Naim R.
,
Weiss G.
,
BenYaakov S.
“H∞control of boost converters: Comparison to voltage mode, feedforword and current mode controls”
in Proc. IEEE PESC Tage Mode, Vol. 2
1995
1327 
1332
Loannidis G. C.
,
Manias S. N.
1999
“H∞loopshaping control schemes for buck converter and their evaluation using μ analysis”
IEE ProcElectr. Power Appl.
146
(2)
237 
246
DOI : 10.1049/ipepa:19990206
Buso S.
1999
“Design of a robust voltage controller for a buckboost converter using μ –Synthesis”
IEEE Trans. Contr. Syst. Technol.
7
(2)
222 
229
DOI : 10.1109/87.748148
Wallis G. F.
,
Tymerski R.
2000
“Generalized approach for μ synthesis of robust switching regulators”
IEEE Trans. Aerosp. Electron. Syst.
36
(2)
422 
431
DOI : 10.1109/7.845219
Bu J.
,
Sznaier M.
,
Wang Z.Q.
,
Batarseh I.
1997
“Robust controller design for a parallel resonant converter using μsysnthesis”
IEEE Trans. Power Electron.
12
(5)
837 
853
DOI : 10.1109/63.623002
Alonge F.
,
D’Ippolito F.
,
Cangemi T.
“Hammerstein modelbased robust control of DC/DC converters”
in Proc. IEEE PEDS2007 Conf.
2007
754 
762
Gupta T.
,
Boudreaux R. R.
,
Nelms R. M.
,
Hung Y.
1997
“Implementation of a fuzzy controller for DCDC converters using an 8b micro controller”
IEEE Trans. Ind. Electron.
44
(5)
661 
669
DOI : 10.1109/41.633467
Ravirij V. S. C.
,
Sen P. C.
1997
“Comparative study of proportionalintegral, sliding mode, and fuzzy logic controllers for power converters”
IEEE Trans. Ind. Appl.
33
(2)
518 
524
DOI : 10.1109/28.568018
Vidal E.
,
MartinezSalamero L.
,
Guinjoan F.
,
Calvente J.
2004
“Sliding and fuzzy control of a boost converter using an 8bit microcontroller”
IEE Proc.Electr. Power Appl.
151
(1)
5 
11
DOI : 10.1049/ipepa:20040086
Balestrino A.
,
Landi A.
,
Sani L.
2002
“CUK converter global control via fuzzy logic and scaling factors”
IEEE Trans. Ind. Appl.
38
(2)
406 
413
DOI : 10.1109/28.993162
Mazumder S. K.
,
Nayfeh A. H.
,
Borojevic D.
2002
“Robust control of parallel DCDC buck converters by combining integralvariablestructure and multipleslidingsurface control schemes”
IEEE Trans. Power Electron.
17
(3)
428 
437
DOI : 10.1109/TPEL.2002.1004251
Guo L.
,
Hung J. Y.
,
Nelms R. M.
2009
“Evaluation of DSPbased PID and fuzzy controllers for DCDC converters”
IEEE Trans. Ind. Electron.
56
(16)
2237 
2249
Leung F. H. F.
,
Tam P. K. S.
,
Li C. K.
1991
“The control of switching dcdc converters – A general LQR problem”
IEEE Trans. Ind. Electron.
38
(1)
65 
71
DOI : 10.1109/41.103487
Leung F. H. F.
,
Tam P. K. S.
,
Li C. K.
1993
“An improved LQRbased controller for switching DCDC converters”
IEEE Trans. Ind. Electron.
40
(5)
521 
528
DOI : 10.1109/41.238013
Czarkowski D.
,
Pujara L. R.
,
Kazimicrczuk M. K.
1995
“Robust stability of statefeedback control of PWM DCDC pushpull converter”
IEEE Trans. Ind. Electron.
42
(1)
108 
111
DOI : 10.1109/41.345854
Chang Y.H.
,
Chen L.W.
“QFTbased robust controller design of series resonant DC/DC converters”
IEEE International Electric Machines and Drives Conference
1997
18 
21
Davoudi A.
,
Jatskevich J.
,
Rybel T. D.
2006
“Numerical statespace averagevalue modeling of PWM DcDC converters operating in DCM and CCM”
IEEE Trans. Power Electron.
21
(4)
1003 
1012
DOI : 10.1109/TPEL.2006.876848
Deane J. H. B.
1992
“Chaos in a currentmode controlled boost DCDC converter”
IEEE Trans. Circuits Syst. I, Fundam. Theory Appl.,
39
(8)
680 
683
DOI : 10.1109/81.168922
Banerjee S.
1998
“Nonlinear modelling and bifurcation in boost converter”
IEEE Trans. Power Electron.
13
(2)
253 
260
DOI : 10.1109/63.662832
Marrero J. L. R.
,
Font J. M.
,
Verghese G. C.
“Analysis of the chaotic regime for DCDC converters under currentmode control”
Power Electronics Specialists Conference, PESC
1996
1477 
1483
Shadmand M. B.
,
Mosa M.
,
Balog R. S.
,
Rub H. A.
“An improved MPPT technique of high gain DCDC converter by model predictive control for photovoltaic applications”
IEEE Applied Power Electronics Conference & Exposition (APEC)
2014
2993 
2999
Ahmadi R.
,
Paschedag D.
,
Ferdowsi M.
“Closedloop input and output impedances of DCDC switching converters operating in voltage and current mode control”
IECON 201036th Annual Conference on IEEE Industrial Electronics Society
2100
2311 
2316
Zhu N.
,
Wu W. L.
,
Shao J. A.
2004
“Chaos control strategy for the currentmode boost converter with small parameter perturbation”
Journal of Circuits and Systems
9
79 
83
Natsheh A. N.
,
Janson N. B.
,
Kettleborough J. G.
“Control of chaos in a DCDC boost converter”
IEEE International Symposium on Industrial Electronics
2008
317 
322
Maiti D.
,
Acharya A.
,
Chakraborty M.
,
Konar A.
,
Janarthanan R.
“Tuning PID and fractional PID controllers using the integral time absolute error criterion”
4th International Conference on Information and Automation for Sustainability
2008
457 
462
Jayakrishna B.
,
Agarwal V.
“FPGA implementation of QFT based controller for a buck type DCDC power converter and comparison with fractional and integral order PID controllers”
COMPEL
2008
1 
6
Luo Y.
,
Li J.
“The controlling parameters tuning and its application of fractional order PID bacterial foragingbased oriented by particle swarm optimization”
IEEE International Conference on Intelligent Computing and Intelligent Systems
2009
4 
7
Valsrio D.
,
da Costa J. S.
2006
“Tuning of fractional PID controllers with ZieglerNicholstype rules”
Signal Processing
86
(10)
2771 
2784
DOI : 10.1016/j.sigpro.2006.02.020
Zitzler E.
,
Thiele L.
1999
“Multiobjective evolutionary algorithms – A comparative case study and the strength pareto approach”
IEEE Trans. Evol. Comput.
3
(4)
257 
271
DOI : 10.1109/4235.797969
Hajela P.
,
Lin C. Y.
1992
“Genetic search strategies in multicriterion optimal design”
Structural Optimization
4
(2)
99 
107
DOI : 10.1007/BF01759923
Fourman M. P.
“Compaction of symbolic layout using genetic algorithms”
in Proc. Int. Conf. Genetic Algorithms and Their Applications
1985
Horn J.
,
Nafpliotis N.
,
Goldberg D. E.
“A niched pareto genetic algorithm for multiobjective optimization”
in Proc. 1st IEEE Conf. Evolutionary Computation, IEEE World Congr. Computational Computation, Vol. 1
1994
Vol. 1
82 
87
Srinivas N.
,
Deb K.
1994
“Multiobjective optimization using nondominated sorting in genetic algorithms”
IEEE Trans. Evol. Comput.
2
(3)
221 
248
Zhao Y.
,
Gao Y.
,
Hu Z.
,
Yang Y.
,
Zhan J.
,
Zhang Y.
“Damping inter area oscillations of power systems by a fractional order PID controller”
International Conference on Energy and Environment Technology
2009
103 
106
Cao J.Y.
,
Cao B.G.
2006
“Design of fractional order controller based on particle swarm optimization”
Int. J. Control, Automat., Syst.
4
(6)
775 
781
Kundu D.
,
Suresh K.
,
Ghosh S.
,
Das S.
“Designing fractionalorder PID controller using a modified invasive weed optimization algorithm”
World Congress on Nature and Biologically Inspired Computing
2009
1315 
1320
Podlubny I.
1999
“Fractionalorder system and PIαDβ– controller”
IEEE Trans. Automat. Contr.
44
(1)
208 
214
DOI : 10.1109/9.739144
Cao J.Y.
,
Liang J.
,
Cao B.G.
“Optimization of fractional ordered PID controllers based on genetic algorithms”
in Proc. the Fourth International Conference on Machine Learning and Cybernetics
2005
5686 
5689
Cai M.
,
Pan X.
,
Du Y.
“New elite multiparent crossover evolutionary optimization algorithm of parameters tuning of fractionalorder PID controller and its application”
Fourth International Conference on Innovative Computing, Information and Control
2009
64 
67