A new inverter topology for singlephase photovoltaic (PV) systems is proposed in this study. The proposed inverter offers a fourlevel voltage in its output terminals. This feature results in easier filtering in comparison with other conventional twolevel or threelevel inverters. In addition, the proposed fourlevel inverter (PFLI) has a transformerless topology, which decreases the size, weight, and cost of the entire system and increases the overall efficiency of the system. Although the inverter is transformerless, it produces a negligible leakage ground current (LGC), which makes this inverter suitable for PV gridconnected applications. The performance of the proposed inverter is compared with that of a fourlevel neutral point clamped inverter (FLNPCI). Theoretical analysis and computer simulations verify that the PFLI topology is superior to FLNPCI in terms of efficiency and suitability for use in PV transformerless systems.
I. INTRODUCTION
Among the photovoltaic (PV) systems, gridconnected PV systems and singlephase systems of up to 5 kW play an important role. It is attempted to determine the benefits of these systems. As most of these systems are private, efficiency and reliability should be maximized and size, weight, and cost should be minimized
[1]
,
[2]
. Depending on the isolation between the PV panels and the grid, the inverter can be either isolated or nonisolated. Isolation is usually achieved using a transformer, which significantly affects the efficiency of the PV system
[3]
. Isolation occurs in two ways: first, by using a stepup lowfrequency transformer in the grid side [
Fig. 1
(a)]; second, by using a highfrequency transformer in the direct current (DC) side [
Fig. 1
(b)]. A transformerless inverter can decrease the weight, size, cost, and installation complexity of the entire PV system (see
Fig. 2
). A drawback of using transformerless PV systems is that omitting the transformer induces DC current in the output AC terminal. Semiconductor parameter variations and filter elements may affect the increase in DC current. However, some manufacturing techniques decrease such effects to an acceptable level
[4]
. One of the important advantages of the transformerless inverters is an increase in overall system efficiency of up to 2%
[5]
. Various inverter topologies are proposed in the literature for gridconnected PV systems, such as fullbridge (FB) based or neutral point clamped (NPC)based
[4]
,
[6]

[12]
.
Isolation in a gridconnected PV system. (a) Lowfrequency transformer in the AC side. (b) Highfrequency transformer in the DC side.
Gridconnected PV system with a transformerless inverter.
The paper is organized as follows: The proposed topology is studied in Section II. A singlephase fourlevel NPC inverter (FLNPCI) is considered in Section III. The analysis of losses and LGC are presented in Sections IV and V, respectively. The simulation results are presented in section VII. Section VIII concludes this study.
II. PFLI TOPOLOGY
The proposed fourlevel inverter (PFLI) has ten IGBTs along with freewheeling diodes and three PV sources that have the same voltages. This topology is FBbased and can generate a fourlevel and symmetrical voltage on its output terminals. The PFLI topology is shown in
Fig. 3
, where
C_{PV}
is the parasitic capacitance between the PV panels and ground
[13]
. This topology is composed of two FB structures with outputs connected to each other. One of them is connected to the middle of the DC bus through two switches (S
_{31}
and S
_{32}
). These two switches enable the middle DC bus voltage to connect to the output directly or inversely without necessarily changing the direction of the output current. Switching states of the PFLI topology for generating a fourlevel output voltage are listed in
Table I
. The switches states for each voltage level (++, +, −−, −) are shown in
Fig. 4
, where the switches states are drawn for positive sign of the current in levels ++ and + and the negative sign of the current in levels − and −−. In voltage level ++ [
Fig. 4
(a)], switches S
_{11}
and S
_{14}
are on and the current flows through their IGBTs. When the sign of the current reverses (in nonunity power factors), the current flows through freewheeling diodes of S
_{11}
and S
_{14}
. In voltage level + [
Fig. 4
(b)], the output current flows through the IGBTs of S
_{21}
and S
_{24}
and freewheeling diodes of S
_{31}
and S
_{32}
. However, in the case that the power factor is nonunity or in the negative halfcycle of the output current, the current will flow through the freewheeling diodes of S
_{21}
and S
_{24}
and IGBTs of S
_{31}
and S
_{32}
. In voltage level −− [
Fig. 4
(c)], switches S
_{12}
and S
_{13}
are on and the current flows through the IGBTs. In nonunity power factors, where the sign of the current reverses, the current will flow through their corresponding freewheeling diodes. In voltage level – [
Fig. 4
(d)], the output current flows through the IGBTs of S
_{22}
and S
_{23}
and the freewheeling diodes of S
_{31}
and S
_{32}
. However, in the case that the power factor is nonunity or in the positive halfcycle of the output current, the current will flow through the freewheeling diodes of S
_{22}
and S
_{23}
and IGBTs of S
_{31}
and S
_{32}
. To modulate the PFLI switches, a pulsewidth modulation (PWM)based method is used. The modulating and carrier signals of the PWM method are shown in
Fig. 5
(a). In this figure, CS1, CS2, and CS3 are the carrier signals and MS is the modulating signal.
Fig. 5
(b) switches gate signals of the PFLI topology in one cycle of fundamental frequency.
PFLI topology.
SWITCHING STATES FOR THE PFLI TOPOLOGY
SWITCHING STATES FOR THE PFLI TOPOLOGY
Switches states of the PFLI topology in voltage levels. (a) ++. (b) +. (c) −−. (d) −.
Modulation signals of PFLI switches. (a) Modulating and carrier signals. (b) Switches gate signals.
The desired output voltage from the modulation procedure is shown in
Fig. 6
. As shown in
Fig. 6
, the inverter output voltage has four modes. In this figure, modes I and III are derived from modulating CS2 with MS, which results in a switch between + and − levels. The only difference between these modes is the direction of the output current.
Desired output voltage from PWM.
Mode II is also derived from modulating CS1 with MS, which results in a switch between ++ and + levels. Mode IV is derived from modulating CS3 with MS, which results in a switch between −− and − levels. The voltages of all switches of the PFLI are demonstrated in
Table II
. As shown in
Table II
, the maximum voltage that should be tolerated by switches is 3
V_{PV}
, which is related to S
_{11}
to S
_{14}
. By contrast, switches with the lowest stress are S
_{31}
and S
_{32}
, which have a voltage of 1/4
V_{PV}
.
SWITCH VOLTAGES OF THE PFLI TOPOLOGY
SWITCH VOLTAGES OF THE PFLI TOPOLOGY
III. FLNPCI TOPOLOGY
The NPC topology was introduced by Nabae et al.
[14]
in 1981. In this topology, switch stress is improved and it can be used in singlephase and threephase systems
[15]
. High voltage requirement in the DC bus is the main disadvantage of this topology. If high DC voltage is unavailable, then a boost stage will be required. Thus, the overall efficiency of the system decreases considerably
[4]
. In this topology, the transient voltage across the inner switches is greater than the outer switches. This finding is due to the fact that the inner switches are not clamped to DC link capacitors same as the outer switches. The inner switches are also directly affected by parasitic components in the system layout
[16]
,
[17]
. In this section, the topology of singlephase FLNPCI is analyzed.
Unlike the threephase types of NPC inverters, the singlephase types (in structures with an even number of output voltage levels) encounter the neutral point problem because the neutral wire cannot be connected directly to DC link capacitors.
To solve this problem, bidirectional (four quadrants) switches have to be used to connect the neutral wire to the middle capacitor of the DC link. The FLNPCI topology with asymmetrical DC sources (FLNPCIASDC) is shown in
Fig. 7
. In this topology, the voltage of the middle DC source is half of the other ones. This property allows the FLNPCIASDC to provide a symmetrical fourlevel voltage to its output terminal. By contrast, the FLNPCI topology with symmetrical DC sources (FLNPCSDC) has identical DC sources in its input. In this case, the magnitude of the levels in the output fourlevel voltage will not be the same. The FLNPCIASDC topology consists of 10 IGBTs with freewheeling diodes and four diodes for clamping. As shown in
Fig. 7
, the output voltage of PV sources is not identical. If the PV source voltages are equal (FLNPCISDC), the loworder current harmonics will be increased, which are difficult to filter, and the levels of the output fourlevel voltage will not be the same. To resolve this problem, the upper and lower sources should be identical and the middle source should be half the other sources (FLNPCIASDC). As a result, the magnitude of the output voltage in each mode will be the same. The FLNPCIASDC has five DC sources, whereas the FLNPCISDC has three DC sources in its input.
Singlephase FLNPCIASDC topology.
The modulation method for the FLNPCI topology is phase disposition PWM (PDPWM)
[18]
. Modulating and carrier waveforms for this method are shown in
Fig. 5
(a). Switching signals generated by the PDPWM method are applied to S
_{1}
, S
_{2}
(S
_{8}
), and S
_{3}
, and complimentary signals are applied to S
_{4}
, S
_{5}
(S
_{7}
), and S
_{6}
, respectively. Thus, a fourlevel voltage will be obtained as output of the inverter. The voltages of all switches in each operational mode are shown in
Table III
. Based on
Table III
, the maximum voltage of the switches is 3
V_{PV}
, which is associated with D
_{12}
and D
_{21}
. Switches with the lowest stress are S
_{7}
and S
_{8}
, which have the voltage of 1/2
V_{PV}
.
SWITCH VOLTAGES OF THE FLNPCIASDC TOPOLOGY
SWITCH VOLTAGES OF THE FLNPCIASDC TOPOLOGY
IV. ANALYSIS OF LOSSES
 A. Switching Losses
1) Switching Losses of the FLNPCIASDC:
Given the nonuniform PV resources and switches gate signals, switching losses will differ. The average switching losses of a switch can be approximately expressed as follows
[19]
:
In (1),
t
_{c(off)}
and
t
_{c(on)}
are the times that the switch is turned off and on completely, respectively,
f_{s}
is the switching frequency, and
I_{on}
and
V_{off}
are the current and voltage of the onstate and offstate of the switch, respectively. Assuming that all switches are identical and based on the same switching frequency and current of all switches, the difference factor of switching losses is the difference between offstate voltages (
V_{off}
) of the switches; one can write.
According to
Table III
, in mode I, the switching losses of back to back switches (S
_{7i}
and S
_{8i}
, where
i
= A, B) are related to the 7A (7B) and 8A (8B) IGBTs (diodes). By contrast, in mode III, they are related to the 7B (7A) and 8B (8A) IGBTs (diodes).
Imposing
V_{off}
=
V_{PV}
, we derive the following equation:
In relation to
Fig. 5
, we observed that
With regard to (4), the operating time of modes I and III (II and IV) are identical. Based on
Table III
, the switching losses in mode I are the same as those in mode III and those in mode II are the same as those in mode IV. Based on
Table I
and
the switching losses of IGBTs (
P_{SWI}
) in
t
_{1}
and
t
_{2}

t
_{1}
can be represented as follows:
According to the switching losses of diodes (
P_{SWD}
), we derive the following equation:
With regard to (3) and (4) and
Table III
, the average switching losses in one cycle of fundamental frequency (see
Fig. 5
) can be expressed as follows:
Also, it can be deduced,
Thus, based on (7), (8), and (9), we will have:
In (10),
P_{SWIFLNPC ASDC}
and
P_{SWDFLNPC ASDC}
are the switching losses of the IGBTs and diodes, respectively.
2) Switching Losses of the FLNPCSDC:
In this case, the procedure of obtaining the switching losses equations is similar to the FLNPCASDC. The voltages of all switches of the FLNPCISDC in each operational mode are shown in
Table IV
. The switching losses of the IGBTs in
t
_{1}
and (
t
_{2}

t
_{1}
) are expressed as follows:
SWITCH VOLTAGES OF THE FLNPCISDC TOPOLOGY
SWITCH VOLTAGES OF THE FLNPCISDC TOPOLOGY
The switching losses of the diodes in
t
_{1}
and (
t
_{2}

t
_{1}
) are:
The switching losses of all semiconductors in one cycle of output fundamental frequency are expressed as follows:
3) Switching Losses of the PFLI:
According to
Table II
, the switching losses of S
_{22}
(S
_{21}
) and S
_{23}
(S
_{24}
) in mode I (mode III) and switching losses of S
_{31}
and S
_{32}
in modes II and IV are due to their corresponding freewheeling diodes. Based on
Table II
, the switching losses of IGBTs in
t
_{1}
and
t
_{2}

t
_{1}
can be expressed as follows:
The switching losses of diodes are:
Based on (8), (14), and (15), the average switching losses of this topology in one cycle of fundamental frequency can be expressed as follows:
where,
P_{SWIPFLI}
and
P_{SWDPFLI}
are the switching losses of IGBTs and diodes of the PFLI, respectively.
From (10) and (16), we derive the following equation:
We deduced from (17) that the switching losses of the PFLI topology are lower than those of the FLNPCIASDC topology. Based on (13) and (16), one can write,
As shown in (18), the switching losses of the IGBTs of the PFLI are higher than those of the FLNPCISDC. However, the switching losses of the diodes of the PFLI are lower than those of the FLNPCISDC.
 B. Conduction Losses
Conduction losses of a switch can be calculated as follows
[19]
:
where
t_{on}
is the onstate time,
T_{s}
is the switching period, and
I_{on}
and
V_{on}
are the onstate current and voltage of the switch, respectively. As
I_{on}
is identical for all conducting switches and assuming that
V_{on}
is the same for all conducting switches, the conduction losses of studied topologies can be approximately compared with each other by averaging the conducting switches in one cycle of fundamental frequency.
All conducting switches are shown in
Table V
for each voltage level of the FLNPCI topology. Based on
Table V
, the number of conducting switches should be counted in each operational mode. So, we have:
CONDUCTING SWITCHES OF THE FLNPCI TOPOLOGY
CONDUCTING SWITCHES OF THE FLNPCI TOPOLOGY
From (20),
Table V
, and the fact that modes I and III repeat twice in each cycle of fundamental frequency, it can be written as:
In
Table VI
, all conducting switches are shown for the PFLI topology in each voltage level. Based on (20),
Table V
, and the fact that modes I and III repeat twice in each cycle of fundamental frequency, we derive the following equation:
CONDUCTING SWITCHES OF THE PFLI TOPOLOGY
CONDUCTING SWITCHES OF THE PFLI TOPOLOGY
Finally, from (21) and (22), we derive the following equation:
Equation (23) shows that the PFLI topology has lower conduction loss in comparison with the FLNPCI topology. We noted that (20) to (23) are valid for the FLNPCIASDC and FLNPCISDC topologies. However,
I_{on}
in (19) is different in these topologies.
V. ANALYSIS OF THE LGC
Most PV panels have a metallic frame that should be grounded to satisfy standards. This frame with wide surface of PV panel constructs a parasitic capacitor. As such, one of its electrodes is PV cells and the other is grounded frame. The value of this parasitic capacitance depends on factors such as PV array and grounded frame surface, distance between PV cell and module, dust, and weather conditions. Parasitic capacitance ranges between some nanofarads and some microfarads
[20]
,
[21]
. When the transformerless PV system is used to increase efficiency and decrease weight, size, and cost, the isolation between PV panels and grid will be lost. Based on the type of inverter, PV panel, and modulation method, the LGC may exceed the allowed value. This leakage current causes safety problems, increases losses and electromagnetic interference, and injects harmony to the grid
[20]

[22]
. In other words, the LGC is a common mode current that flows in the ground through a loop. This loop includes PV panel parasitic capacitance, filter elements, inverter, load (grid), and ground. The common mode current and voltage (
V_{cm}
and
i_{cm}
) are defined as follows:
Differential mode current and voltage (
V_{dm}
and
i_{dm}
) are defined as follows:
In (24) and (25),
V_{AN}
and
V_{BN}
are the voltages of A and B terminals related to DC link neutral (
N
is indicated in
Figs. 3
and
7
), respectively. In
[13]
and
[23]
, the common mode model of a PV system is proposed, of which the common mode voltage (CMV) of the system should be constant for nongenerating LGC. Equivalent common mode circuit of the studied topologies is shown in
Fig. 8
, in which
L_{AB}
=
L_{A}
║
L_{B}
. The CMVs of the PFLI and FLNPCI topologies are shown in
Tables VII
and
VIII
, respectively. Based on
Table VII
, we observed that the CMV of the PFLI topology is constant at all times and its LGC is expected to be low. According to
Table VIII
, the CMV of the FLNPCIASDC topology fluctuates at a high frequency and its LGC is expected to be high.
Common mode model of the studied PV systems.
COMMON MODE VOLTAGES OF THE PFLI TOPOLOGY
COMMON MODE VOLTAGES OF THE PFLI TOPOLOGY
COMMON MODE VOLTAGES OF THE FLNPCIASDC TOPOLOGY
COMMON MODE VOLTAGES OF THE FLNPCIASDC TOPOLOGY
VI. SIMULATION RESULTS
In this section, the PFLI and FLNPCI topologies are compared with each other in terms of output quality, LGC value, and losses. The specifications of the simulated system are shown in
Table IX
. The PV panel voltages are controlled by means of maximum power point tracker (MPPT). In all simulations, the PV panels are replaced by the ideal DC voltage sources to mitigate the need for MPPT. Based on the VDE 012611 German standard, the leakage current must have an amplitude less than 300 mA and a root mean square value of up to 30 mA
[24]
.
Fig. 9
(a) shows the voltage and current of the PFLI topology. We observed that this topology could produce a fourlevel voltage in its output terminals. The LGC of this topology is depicted in
Fig. 9
(b). As expected, the LGC is low, which can evidently satisfy the VDE 012611 German standard. As such, the PFLI topology can be used in a transformerless PV system.
Figs. 9
(c) and
9
(d) show the voltage THD (THDv) and current THD (THDi) of the PFLI topology. We observed that the THDi of the PFLI topology is low. The voltage and current of the FLNPCIASDC topology are shown in
Fig. 10
(a). This topology also produces a fourlevel voltage in its output terminals.
Fig. 10
(b) shows the LGC. As expected, the LGC is high, which cannot satisfy the standard. Thus, the FLNPCIASDC topology cannot be used in transformerless PV systems.
Figs. 10
(c) and
10
(d) show the THDv and THDi of the FLNPCIASDC topology, respectively. The THDi of the FLNPCIASDC topology is higher than that of the PFLI topology. The voltage and the current of the FLNPCISDC topology are shown in
Fig. 11
(a). This topology also produces a fourlevel voltage in its output terminals, but the magnitudes of the operational modes are not identical. In addition, the maximum output voltage of the FLNPCISDC topology is lower than that of the PFLI topology.
SIMULATED SYSTEM SPECIFICATIONS
SIMULATED SYSTEM SPECIFICATIONS
PFLI waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.
FLNPCIASDC waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.
FLNPCISDC waveforms. (a) The inverter voltage and current. (b) The LGC. (c) The THDv. (d) The THDi.
In
Fig. 11
(b), the LGC is illustrated. As expected, the LGC is high, which cannot satisfy the standard. Thus, the FLNPCISDC topology cannot be used in transformerless PV systems.
Figs. 11
(c) and
11
(d) show the THDv and THDi of the FLNPCISDC topology. The THDi in the FLNPCISDC topology is higher than that of other topologies because the magnitudes of the voltage in operational modes are not identical. To simulate the switching and conduction losses of the studied topologies, the PSIM software (from Powersim Inc.) is used. For IGBTs with freewheeling diodes, the characteristics of IKW30N60T (600 V, 30 A) are used. For diodes, the characteristics of CS240650 (600 V, 50 A) are used. The simulation results of the switching and conduction losses are shown in
Table X
. Based on
Table X
, we derive the following equations:
Notably, the value of (26) is slightly different from (17). However, (27) and (28) have more significant differences from their theoretical values [(17) and (23)]. This finding is due to the fact that the characteristics of the diodes are different from the characteristics of the freewheeling diodes of the IGBTs in the FLNPCI topology. Comparing (29) to (31) and their corresponding theoretical values [(18) and (23)], a high discrepancy between power losses is observed because the output current of the FLNPCISDC topology is lower than that of other topologies (see
Figs. 9
,
10
, and
11
).
SWITCHING, CONDUCTION, AND TOTAL LOSSES
SWITCHING, CONDUCTION, AND TOTAL LOSSES
From
Table X
, we deduced that the total losses of the PFLI topology is lower than those of other topologies.
VII. CONCLUSIONS
In this study, a new inverter topology is proposed for transformerless PV systems. This topology can generate a fourlevel voltage in its output terminals, which, in comparison with conventional twolevel and threelevel topologies, has better quality and easier filtering. Based on the theoretical calculations and simulation results (
Table XI
), the PFLI topology is superior to the FLNPCIASDC topology. The PFLI topology is better than the FLNPCISDC topology in terms of the number of semiconductor devices, the maximum output voltage, the conduction and switching losses of diodes, the LGC, and the THDi. The number of PV panels in the PFLI topology is the same as that of the FLNPCISDC topology. The maximum switch voltage and switching losses of the IGBTs of the FLNPCISDC topology are lower than that of the PFLI topology. Overall, the PFLI topology is superior to the FLNPCI topology because of low construction costs (because of the lower number of switches), low losses, high quality of output waveforms, and suitability for use in transformerless PV applications (because of low LGC, which decreases the overall losses of the system considerably). In practice, we suggest the use of the previously mentioned semiconductor devices in constructing the PFLI. To control the PFLI, a microcontroller, such as AT91SAM7S256 (ARMbased Flash MCU), is suggested.
COMPARISON OF THE STUDIED TOPOLOGIES
*Values in parentheses are based on the simulation results.
BIO
Saeed YousofiDarmian was born in Birjand, Iran, in 1989. He received his B.S. and M.S. degrees in Electrical Engineering from the University of Sistan and Baluchestan, Zahedan, Iran, in 2011 and 2013, respectively, graduating with first class honors. He is currently pursuing his Ph.D. degree in the Department of Electrical and Computer Engineering at the University of Sistan and Baluchestan, Zahedan. His research interests include power electronic converters, control of inverters, and photovoltaic systems.
Seyed Masoud Barakati received the B.Sc. and M.Sc., and Ph.D. degrees from Mashhad University, Mashhad, Tabriz University, Tabriz, Iran, and University of Waterloo, Waterloo, Ontario, Canada, in 1993, 1996, and 2008, respectively. He is presently Assistant Professor with the Faculty of Electrical and Computer Engineering at the University of Sistan and Baluchestan, Zahedan, Iran. He had Associate Research position in University of WisconsinMadison, USA (2008–2009) and extended visiting Professor positions at the Universities of Ryerson in Toronto and Ecole Polytechnique de Montréal, Canada. His current research interests include power electronic circuits, control systems, renewable energy, FACTS devices, matrix and multilevel converters, and mechatronic systems.
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Standard din vde 012611