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Asymmetrical Pulse-Width-Modulated Full-Bridge Secondary Dual Resonance DC–DC Converter
Asymmetrical Pulse-Width-Modulated Full-Bridge Secondary Dual Resonance DC–DC Converter
Journal of Power Electronics. 2014. Nov, 14(6): 1224-1232
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : April 30, 2014
  • Accepted : August 22, 2014
  • Published : November 20, 2014
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About the Authors
Zhangyong Chen
Department of Electronic Eng., Southwest Jiaotong University, Chengdu, China
Qun Zhou
Department of Electronic Engineering and Information Technology, Sichuan University, Chengdu, China
zhouqunsc@163.com
Jianping Xu
Department of Electronic Eng., Southwest Jiaotong University, Chengdu, China
Xiang Zhou
Department of Electronic Eng., Southwest Jiaotong University, Chengdu, China

Abstract
A full-bridge secondary dual-resonant DC–DC converter using the asymmetrical pulse-width modulated (APWM) strategy is proposed in this paper. The proposed converter achieves zero-voltage switching for the power switches and zero-current switching for the rectifier diodes in the whole load range without the help of any auxiliary circuit. Given the use of the APWM strategy, a circulating current that exists in a traditional phase-shift full-bridge converter is eliminated. The voltage stress of secondary rectifier diodes in the proposed converter is also clamped to the output voltage. Thus, the existing voltage oscillation of diodes in traditional PSFB converters is eliminated. This paper presents the circuit configuration of the proposed converter and analyzes its operating principle. Experimental results of a 1 kW 385 V/48 V prototype are presented to verify the analysis results of the proposed converter.
Keywords
I. INTRODUCTION
The traditional phase-shifted full-bridge (PSFB) converter shown in Fig. 1 (a) benefits from zero-voltage switching (ZVS) for all switches without the help of any auxiliary circuits [1] , [2] . However, this PSFB converter suffers from a narrow ZVS range of lagging-leg switches under wide load variation, which severely affects its light load efficiency [2] . Given the resonance between transformer leakage inductance and parasitic junction capacitance of a rectifier diode, serious voltage spikes across the diode rectifier are generated [3] , which increases the diode voltage rating and causes electromagnetic interference problems. Excessive circulating current in the primary side during the freewheeling interval also increases the primary side conduction and turn-off switching losses of the lagging-leg switches [4] - [6] . From the corresponding waveforms of a traditional PSFB converter shown in Fig. 1 (b), duty losses exist in the traditional PSFB converter, which increase the turns ratio of the transformer and current stress in the diodes [2] .
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(a) Traditional PSFB converter. (b) The corresponding waveforms.
Many studies have attempted to overcome the said problems in a traditional PSFB converter [2] , [4] - [21] . In order to extend the ZVS range and eliminate voltage spike of diode rectifier, additional auxiliary circuits are required [2] , [4] - [6] , [8] - [11] , [14] , which increase complexity of the converter and cause additional conduction losses.
A new PSFB converter proposed in [4] always operates at a maximum duty ratio of 50% by varying the primary turns of the transformer, thus eliminating the circulating current and decreasing primary-side conduction losses. The power rating for switches decreased and the efficiency improved in the input-series-connected FB converter proposed in [17] , [18] . However, this technique increases the controller complexity.
The transformer secondary side resonance technique is proposed in [22] - [29] to achieve zero current switching (ZCS) for the diode. The ZCS for the output diode is achieved with the resonant tank in the secondary side, whereas the ZVS for switches is realized through the active clamp technique [22] - [28] . However, such resonant technique results in an increased current stress of power switches. A hybrid switching mode step-down resonant-PWM converter is proposed in [29] to decrease the current stress of the power switch. It operates in PWM mode when the switch is turned on, whereas it operates in resonant mode when the switch is turned off. This condition decreases the current stress of the power switch.
This paper presents a full-bridge secondary dual-resonant (FB-SDR) DC–DC converter using the asymmetrical pulse width modulated (APWM) strategy, as shown in Fig. 2 . A magnetizing inductor current is used in the proposed converter to achieve the ZVS for switches. The ZCS for the rectifier diodes is achieved because of the resonance between the leakage inductor and capacitor in the secondary side. Therefore, switching losses and diode reverse-recovery losses are eliminated. Circulating current losses that exist in traditional PSFB converters are largely eliminated because of the APWM strategy. Unlike traditional PSFB converters, the proposed converter can eliminate secondary voltage spikes and voltage oscillation across the rectifier diodes and clamp the diode voltage to the output voltage.
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Proposed FB-SDR converter.
The circuit configuration and operation principle of the proposed converter are presented in Section II. The analysis results are provided in Section III. The performance of the proposed converter is verified by the experimental results of a 1 kW 385 V/48 V prototype in Section IV. The conclusion is presented in Section V.
II. PROPOSED SECONDARY SIDE DUAL-RESONANT FULL BRIDGE CONVERTER
- A. Circuit Configuration
Fig. 2 shows the circuit configuration of the proposed converter. The proposed converter is composed of a full bridge configuration with a blocking capacitor C b on the primary side, a resonant network that consists of a leakage inductor L lk , capacitors C r1 and C r2 in the secondary side, output filter capacitor C o , and load R . When the transformer secondary voltage v S is positive, the leakage inductor L lk and resonant capacitor C r1 constitute a resonant tank, capacitor voltage v cr1 increases, and capacitor voltage v cr2 decreases. When the transformer secondary voltage v S is negative, the leakage inductor L lk and resonant capacitor C r2 constitute a resonant tank, capacitor voltage v cr1 decreases, and capacitor voltage v cr2 increases.
- B. Operating Principle
The following assumptions are made to simplify the analysis of the proposed converter: power switches S 1 , S 2 , S 3 , and S 4 are ideal except for their anti-paralleled diodes and output capacitances; the output capacitances of switches S 1 , S 2 , S 3 , and S 4 are equal, i.e. C oss = C oss1 = C oss2 = C oss3 = C oss4 ; capacitors C b and C o are large enough that voltages V cb and V o can be considered constants in a switching cycle; the transformer is modeled as an equivalent circuit composed of a magnetizing inductor L m , leakage inductor L lk , and an ideal transformer with a turns ratio of n :1, with L m ˃˃ n 2 L lk . The converter operates in a steady state and C r1 = C r2 = C r .
Fig. 3 illustrates key waveforms of the proposed converter in a switching cycle. The operation of power switches S 1 and S 4 , as well as S 2 and S 3 , are the same. Switches S 1 and S 3 are asymmetrical and complementary to the duty ratio D of power switch S 1 . Dead time exists between the on/off states of switches S 1 , S 3 and S 2 , S 4 to ensure safe operation of the power switches in the inverter leg. The proposed converter has seven operational modes in a switching cycle with their corresponding equivalent circuits in each operation mode as shown in Fig. 4 .
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Key waveforms of the proposed converter.
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Operational modes of the proposed converter.
Mode 1 [t0 ~ t1]: At t = t 0 , as i P ( t ) is negative, the anti-paralleled diodes of switches S 1 and S 4 are conducted to provide the flowing path for i P ( t ). The magnetizing inductor current i m ( t ) increases linearly from negative with the current slope of ( V in ˗ V cb )/ L m . As v s is positive, diode D 1 is turned on, and leakage inductor L lk and capacitor C r1 are resonant. Thus, the current through the transformer secondary and voltage across the resonant capacitor C r1 increase, whereas the voltage across resonant capacitor C r2 decreases. i m ( t ) can be expressed as follows:
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where i m ( t 0 ) is negative as shown in Fig. 3 .
The following equation can be derived from the secondary side of the transformer:
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From Equations (2) and (3), the following can be derived:
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where ω r =1/
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is the resonant angle frequency and Z r =
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is the characteristic impedance, I sp1 = [( V in - V cb )/ n - v cr1 ( t 0 )]/ Z r .
i P ( t ) and diode current i D1 ( t ) can be expressed as follows:
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Mode 2 [t1~t2] : As the anti-paralleled diodes of S 1 and S 4 are conducted in mode 1, the zero voltage turn-on of switches S 1 and S 4 are guaranteed. At t = t 1 , i P ( t ) increases to zero and switches S 1 and S 4 are turned on. i m ( t ) increases linearly, diode D 1 continues to conduct, and the resonant tank remains resonant. All the circuit equations in this operation mode are the same as those in operation mode 1.
Mode 3 [t2~t3] : At t = t 2 , switches S 1 and S 4 are turned off, and i P ( t ) charges the output capacitors of switches S 1 and S 4 as well as discharges the output capacitors of switches S 3 and S 2 . The voltages across S 1 to S 4 can be expressed as follows:
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where I p1 represents the transformer primary-side current i p ( t ) at t = t 2 as shown in Fig. 3 . Z 1 = 1/( ω 1 C oss ) = 1/(2 πfs C oss ), where ω 1 = 1/2
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, f s is the switching frequency, and C oss = C oss1 = C oss2 = C oss3 = C oss4 . Note that L kp is the primary-side leakage inductor of the transformer (i.e., L kp = n 2 L lk ).
From Equations (7a) and (7b), the time interval T c1 for the ZVS commutation of S 1 to S 4 can be expressed as follows:
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where t 2-3 is the dead time of the gate signals of S 1 / S 3 and S 2 / S 4 .
Mode 4 [t3~t4] : After the resonance between capacitors C oss1 to C oss4 and primary side leakage inductor L kp , the anti-paralleled diodes of S 2 and S 3 are forward biased. The gates of S 2 and S 3 are triggered during this time interval, and the ZVS for switches S 2 and S 3 are achieved. v p ( t ) is negative (i.e., v p ( t ) = V p = ˗ V in ˗ V cb ). i m ( t ) decreases linearly from positive to negative with the slope of ˗( V in + V cb )/ L m . The transformer secondary voltage is v s ( t ) = v p ( t )/ n = ˗( V in + V cb )/ n .
The following equation can be derived from the secondary side of the transformer:
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Solving Equations (9) and (10) obtains the following:
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Currents i P ( t ) and i D1 ( t ) can be expressed as follows:
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Mode 5 [t4~t5] : As the anti-paralleled diodes of S 2 and S 3 are conducted, the zero voltage turn-on for switches S 2 and S 3 is guaranteed. At t = t 4 , i P ( t ) decreases to zero, switches S 2 and S 3 are turned on, and i D1 ( t ) decreases to zero. Diode D 2 is conducted to provide the current flowing path with leakage inductor L lk and capacitor C r2 .
The circuit equation in this mode can be expressed as follows:
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Thus,
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Currents i P ( t ) and i D2 ( t ) can be expressed as follows:
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When i D2 ( t ) is equal to zero, diode D 2 is turned off and the ZCS for diode D 2 is achieved.
Mode 6 [t5 ~ t6] : The ZCS condition of diodes D 2 is achieved at the beginning of this mode, which eliminates the reverse recovery loss of diode D 2 . The transformer secondary side in this mode is separated from the primary side, no power is transferred from the primary to the secondary side ( Fig. 4 f), and i P ( t ) decreases.
Mode 7 [t6~t7] : At t = t 6 , switches S 2 and S 3 are turned off, and i P ( t ) charges the output capacitors of switches S 2 and S 3 and discharges the output capacitors of switches S 1 and S 4 . The voltages across S 1 to S 4 in this mode are written as follows:
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where I p2 is the transformer primary side current i p ( t ) at t = t 6 . Z 2 = 1/( ω C oss ) = 1/(2 πfs C oss ), ω 1 = 1/2
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.
From Equation (19), the time interval T c2 for the ZVS commutation of S 1 to S 4 can be expressed as follows:
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where t 6-7 represents the dead time of the gate signals for S 1 / S 3 and S 2 / S 4 .
When the output capacitors of power switches S 1 and S 4 are charged to the input voltage V in , the anti-paralleled diodes of switches S 1 and S 4 are conducted and the next switching cycle begins.
III. CHARACTERISTICS ANALYSIS
- A. Voltage Transfer Gain
Assume that the dead times in modes 3 and 7 are short enough that they can be neglected. The voltage across the transformer primary side in modes 1 and 2 is V p1 (i.e., V p1 = V in - V cb ). The voltage across the transformer primary side in modes 4, 5, and 6 is V p2 , i.e. , V p2 = ˗ V in ˗ V cb , where V cb is the average voltage across the blocking capacitor C b .
Applying volt-second balance to the magnetizing inductor L m in steady state ensures that the average voltage across the clamp capacitor is expressed as follows:
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The transformer primary side voltage can then be obtained as follows:
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The average input power in a switching cycle is equal to the output power. Therefore,
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As the transformer magnetizing inductor is large enough that the current ripple flowing through L m is close to zero, the current ripple of i Lm can be neglected. From Equations (4), (6), (11), (13), (16), and (18), Equation (23) can be solved to obtain the following:
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where
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with F = f r / f s , Q = r L lk / R .
Voltage transfer gain can then be derived as follows:
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Fig. 5 shows the voltage gain of the proposed converter at F = 1. The maximum voltage gain can be achieved when D = 0.5.
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Voltage gain of the proposed converter (F = 1).
- A. Comparison between the Proposed and Traditional PSFB Converters
The traditional PSFB converter shown in Fig. 1 (a) is compared with the proposed converter shown in Fig. 2 in this section. The output inductor current is assumed to be a constant current source in the traditional PSFB converter to simplify the analysis. Figs. 1 (b) and 3 show the key operating waveform of these two converters.
Fig. 1 (b) reveals that when switch S 1 is turned off, S 3 and S 4 are turned on simultaneously. Thus, a circulating current exists in the traditional PSFB converter, which results in additional conduction losses as shown in the shadow area in Fig. 1 (b). Fig. 3 shows that when switch S 1 is turned off, S 2 and S 3 are turned on simultaneously. The freewheeling of the primary magnetizing inductor current in a traditional PSFB converter is eliminated in the proposed converter. A small magnetizing inductor is required to achieve a wide ZVS range for all switches in the traditional PSFB converter, which results in a large current ripple and leads to additional conduction losses. It will also lose the ZVS for switches S 2 and S 4 at a light load because of insufficient energy fed by the transformer leakage inductor. However, the proposed converter uses the energy fed by magnetizing inductor L m to achieve the ZVS for all the switches. Thus, enough energy is available for the ZVS operation over the full load range.
- B. ZVS Condition
As enough energy is fed by the magnetizing inductor current and output current, the ZVS operation for switches S 2 and S 3 can be easily achieved over a wide load range ( Fig. 4 c). Fig. 4 (g) shows that the ZVS for switches S 1 and S 4 can be achieved with energy fed by magnetizing inductor L m . Thus, the ZVS condition for the switches in dead time t dead can be expressed as follows:
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From the key waveform of the proposed converter, i m ( t 6 ) can be expressed as follows:
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Thus:
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If Equation (30) is satisfied, all the switches in the proposed converter will turn on with the ZVS over full load conditions.
- C. Design of Switches S1to S4and Diodes D1to D2
Fig. 2 shows that the voltage stresses of all switches are V in and the voltage of diodes D 1 and D 2 are clamped to the output voltage V o . The average current that flows through diodes D 1 , D 2 in a switching cycle is equal to the output current as follows:
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Then,
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From Equation (32), the current stress of diodes D 1 and D 2 can be obtained as follows:
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- D. Design of Resonant Tank (Llks and Cr1, Cr2)
Fig. 6 shows the key current waveforms of the proposed converter with different resonant frequencies. As shown in Fig. 6 , when T r / 2 ˃ DT s , where T r is the resonant period and T s is the switch period, the turn-off currents of switches S 1 and S 4 decrease and the zero-current turn-off for the diode rectifier can be achieved. This condition lowers the turn-off loss of switches S 1 and S 4 and reverse recovery loss of the diode rectifier. However, the peak current of switches S 1 and S 4 as well as the conduction loss increase. When T r / 2 ˃ (1 ˗ D ) T s , the ZCS for the diode rectifier cannot be achieved and the turn-off current of switches S 1 and S 4 also increases. This condition increases the reverse recovery loss of the diode rectifier and turn-off loss of switches S 1 and S 4 . Therefore, having T r / 2 ˃ DT s and T r / 2 ˃ (1 ˗ D ) T s is not preferred. Consider the tradeoff between the reverse recovery loss of the diode rectifier and turn-off loss of switches S 1 and S 4 , T r should be designed such that DT s ˂ T r / 2 ˂ (1 ˗ D ) T s . Cr can then be obtained according to T r = 2π
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.
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Key current waveforms of the proposed converter under different Tr.
IV. EXPERIMENTAL RESULTS
Experimental studies of the proposed converter have been performed to verify the above analysis results of the following converter parameters:
1) input voltage V in = 385 V;
2) output voltage V o = 48 V;
3) maximum output power P o = 1 kW;
4) switching frequency f s = 50 kHz.
With these parameters, the maximum output current is determined as I o = 20.8 A. f r is designed such that f s /[2(1 ˗ D )] ≤ f r ˂ f s /(2 D ). From the voltage gain given by Equation (27) and considering the dead time, the duty cycle D = 0.45 is designed. TDK EE55/21 core is used for the transformer design. The primary and secondary turns of the transformer are n p = 38T and n s = 3T. According to Equation (30), the magnetizing inductance L m = 1010 μH is designed to ensure the ZVS condition for all switches over the whole load conditions. The secondary leakage inductance of the transformer is L lk = 1.29 μH. According to the condition f s /[2(1 ˗ D )] ≤ f r ˂ f s /(2 D ), the resonant capacitor is designed as C r = 4 μF and the resonant frequency is f r =1/ 2 π
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= 51.4 kHz. The blocking capacitor C b is added to set the average current that flows through primary magnetizing inductor to zero, thereby avoiding transformer saturation. Notably, C b does not participate in resonance with L m because the resonant frequency f m ( f m =1/ 2 π
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) of capacitor C b and magnetizing inductance L m is much lower than the switching frequency f s . f m = (
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) f s is generally selected. Thus, C b = 1 μF is designed in the experimental circuit. The dead time of switches S 1 / S 3 and S 2 / S 4 is selected as 300 ns in the experimental circuit according to Equations (8) and (20). The ZVS operation for switches is fed by a magnetizing inductor current and output current. Thus, the ZVS operation can be easily achieved over a wide load range. The parameters of passive components and semiconductors are shown in Fig. 7 with the circuit parameters given in Table I .
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Laboratory prototype circuit of the proposed converter.
PARAMETERS OF THE PROPOSED CONVERTER
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PARAMETERS OF THE PROPOSED CONVERTER
- A. Experimental Results
Fig. 8 shows key waveforms of the proposed converter at a nominal input voltage (i.e., 385 V) and under a full load of 20.8 A. All measured waveforms in the figure closely follow the theoretical waveforms described in Fig. 3 . Figs. 8 (d) and 8 (e) also show that the secondary diode voltages v D1 ( t ) and v D2 ( t ) have no voltage overshoot and oscillation. The ZCS for diodes D 1 and D 2 can also be achieved. Fig. 9 shows the switch voltage and switch current of the proposed converter at full and 10% loads, respectively. Fig. 9 shows that all the switches in the proposed converter are turned on with the ZVS over full load conditions. Unlike PSFB converters, the circulating current and turn-off switching losses are decreased.
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Key experimental waveforms of the proposed converter at a full load of 20 A. (a) Vin and iin(t); (b) vAB(t) and primary current ip(t); (c) Vo, vCr1(t), and vcr2(t); (d) vD1(t) and iD1(t); (e) vD2(t) and iD2(t).
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Voltage and current waveforms of the proposed converter: (a) and (b): at full load; (c) and (d): at 10% of the full load.
- B. Efficiency
Fig. 10 shows the efficiency at an input voltage of 385 V. The proposed converter has higher efficiency than a PSFB converter, especially under light load conditions. At light loads, the ZVS operation of traditional PSFB converter switches is difficult to achieve. The efficiency improvement of the proposed converter is achieved because of the ZVS operation over a whole load range as well as decreased circulating current and turn-off switching losses. Without secondary-voltage overshoot and oscillation, a low voltage-rating diode can be used, which also contributes to the efficiency improvement.
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Efficiency of the proposed converter.
IV. CONCLUSIONS
This paper presents an FB-SDR DC–DC converter that solves the drawbacks of PSFB converters, such as a narrow ZVS range against load variation, large circulating current, and serious secondary-voltage overshoot and oscillation. The theoretical analysis results show the advantage of the proposed converter over a traditional PSFB converter. The experiment results of a prototype converter verify the results of the theoretical analysis. However, given that the APWM strategy obtains the current stress of the switches, the proposed converter is available for applications in a narrow input voltage range and is also applicable to high-voltage applications such as high-voltage battery chargers(200 V–400 V).
Acknowledgements
This research is supported by the National Natural Science Foundation of China under grant no. 51177140, the Fundamental Research Funds for the Central Universities under project number SWJTU11CX029, and the 2014 Doctoral Innovation Funds of Southwest Jiaotong University.
BIO
Zhangyong Chen was born in Sichuan, China, in 1988. He received his B.S. in Electrical Engineering and Automation from Southwest Jiaotong University (SWJTU), Chengdu, China, in 2010, where he is currently working toward a Ph.D. degree at the School of Electrical Engineering. His research interests include switching-mode power supplies, soft switching techniques, power factor correction converters, and renewable energy sources.
Qun Zhou received her B.S. and Ph.D. in Automation Engineering from the University of Electronic Science and Technology of China, Chengdu, China, in 1989 and 2009, respectively. She has been with the School of Electrical Engineering Information, Sichuan University, Chengdu since 1989, where she has been an associate professor since 1998. Her research interests include power quality analysis and control.
Jianping Xu (M’09) received his B.S. and Ph.D. in Electronic Engineering from the University of Electronic Science and Technology of China, Chengdu, China, in 1984 and 1989, respectively. He has been with the School of Electrical Engineering, SWJTU, Chengdu since 1989, where he has been a professor since 1995. He was a visiting research fellow with the Department of Electrical Engineering, University of Federal Defense, Munich, Germany from November 1991 to February 1993. He was a visiting scholar with the Department of Electrical Engineering and Computer Science, University of Illinois, Chicago from February 1993 to July 1994. His research interests include modeling, analysis, and control of power electronic systems.
Xiang Zhou was born in Shanxi, China, in 1991. He received his B.S. degree in Electrical Engineering and Automation from SWJTU, Chengdu, China in 2013, where he is currently working toward his Ph.D. degree at the School of Electrical Engineering. His research interests include high step-up DC–DC converters, soft switching techniques, and renewable energy sources.
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