Commonmode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high
dv/dt
causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulsewidth modulation (PWM) strategy for threelevel Ttype NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the threelevel Ttype NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulsewidth modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reducedCMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phaseshift PWM method has good output waveform performance and reduces CMV.
I. INTRODUCTION
Interest in multilevel topologies has been increasing because of the many possibilities in power electronics applications, such as in the military, evehicles, and renewable energy. Multilevel converters synthesize output voltage from more than two voltage levels. Therefore, the spectrum of the output signal is significantly improved when compared with that of classical twolevel converters. The multilevel inverter reduces voltage constraints on switches while lowering the total harmonic distortion (THD) of output voltages
[1]

[5]
. The main drawback of multilevel converters is the number of switches, which increases with the number of levels.
Multilevel inverters are classified into three groups: neutralpointclamped (NPC) inverters, floating point capacitor inverters, and cascade H–bridge inverters, with NPC inverters being the most widely used
[6]

[8]
. Recently, Ttype NPC (TNPC) inverters have been proposed as more efficient alternatives to traditional NPC inverters
[9]
,
[10]
. Until recently, multilevel NPC inverters have received considerable attention for commercial applications, and many researchers have focused on improving the output performance while reducing the power losses, the number of power switches, and the commonmode voltage (CMV) of such converters
[11]

[15]
. Previous research deemed CMV reduction to be important in extending the lifetime of electrical equipment.
CMV attributed to highspeed pulsewidth modulation (PWM) in power converters introduces numerous problems within an electrical system. CMW is the main source of early motorwinding failure, bearing deterioration, and wideband electromagnetic interference. Reducing the CMV within the power converter is important. Two main solutions used to reduce CMV have been presented in previous research. One solution is based on the use of additional hardware, such as passive filters, active cancellers, or electromagnetic interference filters, to mitigate CMV
[16]
,
[17]
. However, this method introduces increased converter volume, weight, and cost. Another solution is to investigate the modulation technique. Using suitable PWM, mitigating the CMV is achievable within the power converter. Several studies have proposed CMV reduction for NPC topology by applying the appropriate modulation techniques. However, these methods focus on the SVPWM method, which has several disadvantages
[18]
,
[19]
. This method requires complex calculations and tables to synthesize the reference output voltage. In
[20]

[22]
, the phase opposition disposition (POD) was proposed to reduce CMV for NPC. However, this method has high THD in the output voltage, a high RMS value, and a poor harmonics spectrum in the CMV.
To overcome the drawbacks of phase disposition (PD) PWM and POD PWM schemes, this study proposes a novel carrierbased PWM method for use with TNPC to eliminate CMV. The proposed strategy uses threephase carriers of the same frequency with a phase difference of 120°. The proposed method is simple to implement and does not require any additional hardware. The advantages of the proposed method are as follows:

 Eliminates the peak value of the CMV, and the magnitude is reduced by 50% compared with that when using the conventional PD PWM scheme.

 Exhibits better harmonic spectrum for CMV and reduces the RMS of CMV when with the conventional POD PWM scheme.
The remainder of this paper is organized as follows: The threelevel Ttype NPC operation and the effect of the switching state on CMV are described in Section II. The conventional PD and POD schemes are also presented in this section. The proposed method is presented in Section III. The simulation and experimental results are provided in Sections IV and V, respectively. Study conclusions are provided in the final section.
II. CMV ANALYSIS AND CONVENTIONAL METHODS
 A. ThreeLevel TType NPC Inverter Topology
The threelevel Ttype NPC inverter topology is illustrated in
Fig. 1
. Each leg of the TNPC consists of four powerswitch devices: IGBT1X and IGBT4X (X = A,B,C) are connected to the positive and negative poles of the dc power supply, respectively, and one bidirectional switch (IGBT2X and IGBT3X) connects the middle point of the dclink to the load. The threelevel Ttype NPC topology is simpler than that of conventional NPC and provides some advantages that are unavailable in conventional NPC, such as low conduction losses, fewer power switches, and small size
[9]
,
[10]
.
Threelevel TNPC Inverter topology.
The switching states of the power switches and the output voltage of the threelevel TType NPC are shown in
Table I
. The three phase levels of common point voltage that can be generated on each phase leg are +V
_{dc}
2, 0, and −V
_{dc}
/2, where Vd
_{dc}
is the dclink voltage, and X represents each phase (X = A, B, or C).
SWITCHING STATES OF THE TNPC
SWITCHING STATES OF THE TNPC
 B. CommonMode Voltage Analysis
The CMV of the threelevel TType NPC is defined as the voltage between load neutral point
n
and the midpoint of dclink voltage g, as shown in
Fig. 1
. We assumed that the threephase RL load is balanced. The CMV is derived from the following equations:
where v
_{Ag}
, v
_{Bg}
, and v
_{Cg}
are the three phase output voltages with respect to ground point
g
; and i
_{A}
, i
_{B}
, and i
_{C}
are the three phase output currents.
Given that the threephase load is balanced, the CMV becomes
The CMV depends on the switching states of the threelevel Ttype NPC inverter and can be determined using the following switching functions:
Eq. (3) and
Table I
show that the CMV has seven values: 0, ±V
_{0}
/6, ±V
_{0}
/3, and ±V
_{0}
/2. They are provided in detail in
Table II
. Regardless of the AC source, the CMV is determined by the output voltages, which depend only on the switching states of the threelevel Ttype NPC inverter.
CMV ACCORDING TO SWITCHING STATES
CMV ACCORDING TO SWITCHING STATES
 C. Conventional Methods
1) Phase Disposition (PD) PWM Scheme:
The PD PWM scheme is used in the carrierbased implementation
[15]
,
[16]
.
Fig. 2
shows the basic principle of the PD PWM scheme using double triangle carrier signals. The upper carrier signal (V
_{carrier1X}
) is used to generate the gate signal for switch IGBT1X, IGBT3X. The lower carrier signal (V
_{carrier2X}
) is used to generate the gate signal for the switch IGBT2X, IGBT4X. Two carrier waveforms are arranged so that every carrier is in phase; one is above zero and the other is below zero.
Carrier and reference waveforms for threelevel TNPC inverter using PD PWM scheme.
2) Conventional ReducedCMV Method Based on Phase Opposition Disposition PWM Scheme:
For POD schemes, the three carrier signals above zero are in phase, and the three carrier signals below zero are also in phase. However, the upper carrier signal and the lower carrier signal are in opposite phase, as shown in
Fig. 3
.
Carrier and reference waveforms for threelevel TNPC inverter using POD PWM scheme.
As shown in
Figs. 3
and
4
, the upper triangle magnitude is normalized from 1 to 0, and the lower triangle magnitude is normalized from −1 to 0.
Reference output voltage, triangle carrier signals, and switching states of the conventional PD PWM method.
III. PROPOSED CARRIER PHASESHIFT PWM METHOD FOR CMV REDUCTION
Table II
shows that by employing 19 switching states (000, −101, 101, 011, 011, 110, −110, 111, 111, −111, −100,010,001, 111, 111, −111, 100,010,001) to synthesize the reference output voltage, the peak value of CMV is limited at V
_{dc}
/6.
We assume that the normalized threephase reference outputs are given as
where
m
is the modulation index, and
ω
is the input angular frequency.
Two conditions are possible for the six different situations when the three phase output voltages are balanced. In the first condition, two input phase voltages are positive, and one phase voltage is negative. In the second condition, two input phase voltages are negative, and one phase voltage is positive. Without losing the generality of the analysis, we assume that the output voltage of Phase A is positive and the output voltages of Phases B and C are negative, as shown in
Fig. 3
. Therefore, the possible switching states for Phase A are 1 or 0, and the possible switching states for Phases B and C are 0 or −1.
Fig. 4
shows that the switching state (011) causes the CMV to be at –V
_{dc}
/3. Thus, to reduce the CMV peak, we must avoid using this switching state to synthesize the reference output voltages. Two carrier signals are used in the conventional PD and POD methods. In this study, carrier phaseshift PWM is proposed based on six carrier signals that are used to generate a gating pulse for the threelevel Ttype NPC.
The proposed carrier phase shift is developed based on the conventional PD PWM method. According to
Table II
, the peak CMV can be reduced from V
_{dc}
/2 to V
_{dc}
/6 if the switching states 111, −111, 110, 101, 011, −110, −101, and 011 are not used.
Given that the input voltages are balanced as shown in Eq. (7), two other conditions are possible: (1) Two input phase voltages are positive and one phase voltage is negative; and (2) Two input phase voltages are negative and one phase voltage is positive.
Without losing the generality of the analysis, we assume that
V_{A}
> 0,
V_{B}
< 0,
V_{C}
< 0 .
Table II
and
Fig. 1
shows that the switching stage becomes 011 and it causes the peak CMV to become higher than V
_{dc}
/6.
The relationship between the reference output voltage and the carrier signals are given in Eq. (8) for the switching state 011.
From
Fig. 2
, the relationship between the upper and lower carrier signals is
Substituting Eq. (9) into Eq. (8), we have
From Eqs. (8) and (10), we can obtain Eq. (11):
Therefore,
To reduce CMV, the state 011 must be avoided. Therefore, the relationship between three carrier signals has to fully meet Eq. (13).
Fig. 5
shows the three upper carrier signals for legs A, B, and C through the conventional SPWM method. The sum of the three carrier signals is larger than 2. Therefore, a peak CMV with the value V
_{dc}
/3 is obtained.
Carrier waveforms for threelevel Ttype NPC inverter using PD PWM scheme.
If the three carrier signals for Phases A, B, and C are chosen with a displacement of 120°, as shown in
Fig. 6
, the sum of the three carrier signals is less than 2. Thus, the maximum CMV is V
_{dc}
/6. In the proposed carrier phaseshift method, the upper carrier signal and lower carrier signals for each leg are in phase. However, three upper and lower carrier signals for legs A, B, and C are out of phase by 120°.
Carrier waveforms for threelevel Ttype NPC inverter using proposed carrier phase shift PWM scheme.
IV. SIMULATION RESULTS
We conducted simulations using PSIM 9.0 software to verify the effectiveness of the new SVM method. The system is simulated with the following parameters:

 Dclink voltage Vdc= 530 V

 Threephase RL load: R = 30 Ω, L = 15 mH

 Modulation index m = 0.8

 Output frequency: fout= 50 Hz

 PWM frequency = 10 kHz
Figs. 7
to
9
show the linetoline output voltage, its FFT, and the threephase output currents for the modulation index m = 0.8 and output frequency 50 Hz using the PD, POD, and PWM schemes, respectively. The proposed PWM method provides the same sinusoidal output currents as those of the other PWM methods. The different output voltage waveforms result from different modulation methods. The fast Fourier transform (FFT) results of the linetoline output voltage show fewer harmonics for the proposed method than for the conventional reducedCMVbased POD method. However, the THD of the linetoline output voltage with the proposed method slightly increases compared with that of the conventional PD PWM method.
(a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Three phase output currents using the PD PWM method.
(a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Three phase output currents using the POD PWM method.
(a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Three phase output currents using the proposed carrier phaseshift PWM method.
Figs. 10
to
12
show the CMV waveforms and their FFT analysis when employing the PD, the conventional reducedCMVbased POD method, and the proposed method, respectively, at an output frequency of 50 Hz and a modulation index of 0.8. The conventional reducedCMVbased POD method and the new carrier phaseshift method provide the same CMV peak value (88 V).
Fig. 10
shows the CMV pulses of magnitude V
_{dc}
/3 (177 V) when the PD method is applied. Compared with the conventional PD method, the proposed method significantly reduces the CMV peak value by 50%. Furthermore, the spectrum analysis of the CMV shows that the CMV of the proposed PWM scheme contains fewer harmonic components compared with the conventional PD and POD PWM schemes.
(a) Commonmode voltage. (b) FFT using the PD PWM method with m = 0.8 and f_{out} = 50 Hz.
(a) Commonmode voltage. (b) FFT using the POD PWM method with m = 0.8 and f_{out} = 50 Hz.
(a) Commonmode voltage. (b) FFT using the proposed PWM method with m = 0.8 and f_{out} = 50 Hz.
V. EXPERIMENTAL RESULTS.
To validate the proposed theories and simulations, we designed an experimental setup in the laboratory. The experimental prototype is shown in
Fig. 13
. The halfbridge IGBT modules SEMiX202GB128Ds (1,200 V) were selected for switch pairs IGBT1X, IGBT4X. The bidirectional IGBT modules SK60GM123 (1,200 V) were chosen for the switch pairs IGBT2X, IGBT3X. The prototype is controlled with the use of a highperformance, floatingpoint digital signal processor (DSP) 90 MHz TMS320F28069 from Texas Instruments. The parameters used in the experiment are the same as in the simulation. The PWM operates at 10 kHz.
Laboratory TNPC prototype.
Figs. 14
to
16
show the experimental results for the linetoline output voltage, its FFT, and the output currents of the conventional PD, POD, and proposed PWM methods, respectively. Every method provides almost pure sinusoidal output currents, and the proposed PWM method does not decrease the performance of the output currents. The spectrum and phase output voltage are comparable to the output performance for the two conventional methods and the proposed carrier phaseshift PWM method.
Figs. 14
b,
15
b, and
16
b show the harmonic spectrum of the output linetoline voltage for the three PWM methods. The spectrums indicate that the proposed PWM method has good output voltage compared with the conventional reducedCMVbased POD method. However, the proposed method has several drawbacks. The performance of the output voltage using the proposed method is worse than that of the PD PWM method and exhibits a tradeoff between CMV reduction and output voltage performance.
(a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Output current at an output frequency of 50 Hz and a modulation index of m = 0.8 using the PD method.
(a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Output current at an output frequency of 50 Hz and a modulation index of m = 0.8 using the POD method.
Experimental results of (a) Linetoline output voltage. (b) FFT of linetoline output voltage. (c) Output current at an output frequency of 50 Hz and a modulation index of m = 0.8 using the proposed PWM method.
Fig. 17
shows the CMV waveforms of the threelevel Ttype NPC inverter when the PD PWM method is applied. The peak value of the CMV is achieved at 177 V, which corresponds to V
_{dc}
/3.
Figs. 18
and
19
show the CMV of the threelevel Ttype NPC inverter when the conventional reducedCMV method (POD method) and the proposed method are used, respectively. The two methods reduce the peak value of CMV. The peak value of CMV decreases from 177 V to 86 V, which corresponds to V
_{dc}
/6. Compared with the conventional PD method, the proposed method significantly reduces the CMV peak value by 50%. According to an FFT of the CMV, the new SVM method generates a smaller harmonic component than that of the PD PWM method.
(a) CMV waveforms and (b) its FFT with PD method at an output frequency of 50 Hz and a modulation index of m = 0.8.
(a) CMV waveforms. (b) Its FFT with POD method at an output frequency of 50 Hz and a modulation index of m = 0.8.
(a) CMV waveforms. (b) Its FFT with proposed method at an output frequency of 50 Hz and a modulation index of m = 0.8.
The performance of the proposed PWM method has been also tested by considering low modulation index and low frequency. The CMV with PD, POD, and the proposed carrier phase shift PWM methods at f=30Hz, m=0.6, and f=20Hz, m=0.3 are shown in
Figs. 20
and
21
, respectively. The POD and carrier phase shift PWM methods provides a 50% reduction in the CMV (peak value) compared with the conventional PD PWM method.
Fig. 22
shows the RMS value of the CMV with the PD, POD, and the proposed PWM methods according to the modulation index. Compared with the conventional reduced CMV–POD PWM method, the proposed method provides a lower RMS value for the CMV at the modulation index higher than 0.5. However, at a lower modulation index, the RMS value of the CMV with the proposed method becomes higher than that using the POD PWM method. Thus, using a combined PWM algorithm that uses the proposed POD PWM method with a low modulation index as well as using the proposed method at high modulation index to control full output voltage range is recommended.
CMV waveforms. (a) PD PWM. (b) POD PWM methods. (c) The proposed method at an output frequency of 30 Hz and a modulation index of m = 0.6.
Experimental result of CMV waveforms. (a) PD PWM. (b) POD PWM methods. (c) The proposed method at an output frequency of 20 Hz and a modulation index of m = 0.3.
Comparison with the RMS values for different CMV.
VI. CONCLUSIONS
A carrier phaseshift PWM method is proposed in this study to reduce CMV for threelevel Ttype NPC inverters. The proposed method achieves a peak value of CMV, which is reduced by 50% compared with that of the conventional PD PWM method. The proposed method has a lower RMS value of CMV than the POD PWM method at a modulation index higher than 0.5. The proposed method is implemented simply, and no additional computations are needed beyond those of conventional PD and POD PWM schemes. Finally, experimental results have been provided to verify the theoretical analysis and simulation results.
Acknowledgements
This work was supported by 2014 Research Funds of Hyundai Heavy Industries for University of Ulsan.
BIO
Tuyen D. Nguyen was born in BinhDinh, Vietnam, in 1982. He received his B.S. degree in electrical engineering from the University of Technology, Hochiminh City, Vietnam, in 2004 and his Ph.D degree from the University of Ulsan, Ulsan, Korea in 2012. He is currently a lecturer for the Faculty of Electrical and Electronics Engineering, Hochiminh city University of Technology, VNUHCM, Vietnam. His research interests include power electronics, electrical machine drives, and low cost inverter and renewable energy, especially matrix converters.
Dzung Quoc Phan was born in Saigon, Vietnam, in 1967. He received his Dipl.Eng. degree in electromechanical engineering from Donetsk Polytechnic Institute, Donestk City, Ukraine, in 1991 and his Ph.D degree in engineering sciences from Kiev Polytechnic Institute, Kiev City, Ukraine, in 1995. He became an Associate Professor in electrical engineering at University of Technology, Hochiminh City, Vietnam in 2010. He is currently senior lecturer for the Faculty of Electrical and Electronics Engineering, University of Technology, Hochiminh City, Vietnam. His research areas include power electronics and electric machines, static power converters, especially multilevel converters and its applications in renewable energy and microgrids.
Dat Ngoc Dao was born in BinhDinh province, Vietnam on 24 February 1990. He studied electrical engineering five years at the University of Technology, Hochiminh city, Vietnam and received his B.S. degree in 2014. He focused on power electronics, digital control and designing power converter, inverter, photovoltaic applications, motor drivers during his studies. His thesis dealt with design and a highpower highefficiency threephase threelevel inverter used to inject the power of PV panels into the national grid. Since 2012, Dat Ngoc Dao has worked at the Advanced Power Electronics Laboratory in the university, where he is conducting research on a national project.
HongHee Lee received his B.S., M.S., and Ph.D. in Electrical Engineering from Seoul National University, Seoul, Korea, in 1980, 1982, and 1990, respectively. From 1994 to 1995, he was a Visiting Professor at the Texas A&M University. He has been a Professor in the School of Electrical Engineering in the Department of Electrical Engineering, University of Ulsan, Ulsan, Korea since 1985. He is also the Director of the Networkbased Automation Research Center (NARC), which is sponsored by the Ministry of Trade, Industry and Energy. His research interests include power electronics, networkbased motor control, and renewable energy. Dr. Lee is a member of the Institute of Electrical and Electronics Engineers (IEEE), the Korean Institute of Power Electronics (KIPE), the Korean Institute of Electrical Engineers (KIEE), and the Institute of Control, Robotics and Systems (ICROS). He is now the President of KIPE.
Rodriguez J.
,
Lai J.S.
,
Peng F. Z.
2002
“Multilevel inverters: a survey of topologies, controls, and applications”
IEEE Trans. Ind. Electron.
49
(4)
724 
738
DOI : 10.1109/TIE.2002.801052
Lai J.S.
,
Peng F. Z.
1996
“Multilevel convertersa new breed of power converters”
IEEE Trans. Ind. Appl.
32
(3)
509 
517
DOI : 10.1109/28.502161
Tsang K.M.
,
Chan W.L.
2014
“Single DC source threephase multilevel inverter using reduced number of switches”
IET Power Electron.
7
(4)
775 
783
DOI : 10.1049/ietpel.2013.0319
Barros J. D.
,
Silva J. F. A.
,
Jesus E. G. A.
2013
“Fastpredictive optimal control of NPC multilevel converters”
IEEE Trans. Ind. Electron.
60
(2)
619 
627
DOI : 10.1109/TIE.2012.2206352
Rodriguez J.
,
Bernet S.
,
Wu B.
,
Pontt J. O.
,
Kouro S.
2007
“Multilevel voltagesourceconverter topologies for industrial mediumvoltage drives”
IEEE Trans. Ind. Electron.
54
(6)
2930 
2945
DOI : 10.1109/TIE.2007.907044
Kouro S.
,
Malinowski M.
,
Gopakumar K.
,
Pou J.
,
Franquelo L. G.
,
Wu B.
,
Rodriguez J.
,
Perez M. A.
,
Leon J. I.
2010
“Recent advances and industrial applications of multilevel converters”
IEEE Trans. Ind. Electron.
57
(8)
2553 
2580
DOI : 10.1109/TIE.2010.2049719
Pharne I. D.
,
Bhosale Y. N.
“A review on multilevel inverter topology”
Power, Energy and Control (ICPEC), 2013 International Conference on
2013
700 
703
Vishvakarma R. P.
,
Singh S. P.
,
Shukla T. N.
“Multilevel inverters and its control strategies: A comprehensive review”
Power, Control and Embedded Systems (ICPCES), 2012 2nd International Conference on
2012
1 
9
Choi U.M.
,
Lee H.H.
,
Lee K.B.
2013
“Simple neutralpoint voltage control for threelevel inverters using a discontinuous pulse width modulation”
IEEE Trans. Energy Convers.
28
(2)
434 
443
DOI : 10.1109/TEC.2013.2257786
Schweizer M.
,
Kolar J. W.
“High efficiency drive system with 3level Ttype inverter”
Power Electronics and Applications (EPE 2011), Proceedings of the 201114th European Conference on
2011
1 
10
Palanivel P.
,
Dash S. S.
2011
“Analysis of THD and output voltage performance for cascaded multilevel inverter using carrier pulse width modulation techniques”
IET Power Electron.
4
(8)
951 
958
DOI : 10.1049/ietpel.2010.0332
Jiao Y.
,
Lu S.
,
Lee F. C.
2014
“Switching performance optimization of a high power high frequency threelevel active neutral point clamped phase leg”
IEEE Trans. Power Electron.
29
(7)
3255 
3266
DOI : 10.1109/TPEL.2013.2277657
Irouz Y.
,
Bina M. T.
,
Eskandari B.
2014
“Efficiency of threelevel neutralpoint clamped converters: analysis and experimental validation of power losses, thermal modelling and lifetime prediction”
IET Power Electron.
7
(1)
209 
219
DOI : 10.1049/ietpel.2012.0711
Chen Q.
,
Wang Q.
,
Li G.
,
Jiang W.
2012
“Analysis and comparison of power losses in 3LNPC inverter with SHPWM control”
Electrical Machines and Systems (ICEMS), 2012 15th International Conference on
1 
5
Tsang K.M.
,
Chan W.L.
2014
“Single DC source threephase multilevel inverter using reduced number of switches”
IET Power Electron.
7
(4)
775 
783
DOI : 10.1049/ietpel.2013.0319
Akagi H.
,
Hasegawa H.
,
Doumoto T.
2004
“Design and performance of a passive EMI filter for use with a voltagesource PWM inverter having sinusoidal output voltage and zero commonmode voltage”
IEEE Trans. Power Electron.
19
(4)
1069 
1076
DOI : 10.1109/TPEL.2004.830039
Akagi H.
,
Doumoto T.
2004
“An approach to eliminating highfrequency shaft voltage and ground leakage current from an inverterdriven motor”
IEEE Trans. Ind. Appl.
40
(4)
1162 
1169
DOI : 10.1109/TIA.2004.830748
Bharatiraja C.
,
Raghu S.
,
Palanisamy R.
2012
“A new space vector pulse width modulation for reduction of common mode voltage in three level neutral point diode clamped multilevel inverter”
Advances in Engineering, Science and Management (ICAESM), 2012 International Conference on
694 
699
Long L.
,
Zhang Y.
,
Kuang G.
“A modified space vector modulation scheme to reduce common mode voltage for cascaded NPC/Hbridge inverter”
Power Electronics and Motion Control Conference (IPEMC), 2012 7th International
2012
1837 
1841
Radan A.
,
Shahirinia A. H.
,
Falahi M.
“Evaluation of carrierbased PWM methods for multilevel inverters”
Industrial Electronics, 2007. ISIE 2007. IEEE International Symposium on
2007
389 
394
Salagae I. M.
,
du T Mouton H.
“Natural balancing of neutralpointclamped converters under POD pulsewidth modulation”
Power Electronics Specialist Conference, 2003. PESC '03. 2003 IEEE 34th Annual, Vol. 1
2003
47 
52
Renge M. M.
,
Suryawanshi H. M.
2011
“Multilevel inverter to reduce common mode voltage in AC motor drives using SPWM technique”
Journal of Power Electronics
11
(1)
21 
27
DOI : 10.6113/JPE.2011.11.1.021