This study proposes a finitestate model predictive controller to regulate the load current and balance the DClink capacitor voltages of a fourleg neutralpointclamped converter. The discretetime model of the converter, DClink, inductive filter, and load is used to predict the future behavior of the load currents and the DClink capacitor voltages for all possible switching states. The switching state that minimizes the cost function is selected and directly applied to the converter. The cost function is defined to minimize the error between the predicted load currents and their references, as well as to balance the DClink capacitor voltages. Moreover, the current regulation performance is improved by using a twostep prediction horizon. The feasibility of the proposed predictive control scheme for different references and loads is verified through realtime implementation on the basis of dSPACEDS1103.
NOMENCLATURE
DClink voltage
v
Converter voltage
i
Load (output) current
i
^{∗}
Reference load current
C_{dc}
DClink capacitance [
C
_{1}
C
_{2}
]
^{T}
L_{f}
Filter inductance [
L_{fa}
L_{fb}
L_{fc}
]
^{T}
R_{f}
Filter leakage resistance [
R_{fa}
R_{fb}
R_{fc}
]
^{T}
R
Load resistance [
R_{a}
R_{b}
R_{c}
]
^{T}
L_{n}
,
R_{n}
Neutral inductance and its leakage resistance
L_{nl}
,
R_{nl}
Nonlinear load inductance and resistance
T_{s}
Sampling time
N
Prediction horizon
x
Timevarying quantity
I. INTRODUCTION
Imbalanced and nonlinear loads cause a large amount of neutral current in threephase fourwire systems. Hence, conventional threeleg, threephase power converters are unsuitable for such applications. Correspondingly, fourleg converters provide the best path for neutral currents
[1]

[3]
. Many applications, including distributed generation, universal power quality conditioners, electric drives, shunt active power filters, and active frontend rectifiers, that utilize fourleg converters require precise current control
[4]

[8]
.
Multilevel diodeclamped converters reach high power levels with reduced common mode voltages, total harmonic distortion, and electromagnetic interference
[9]
. Hence, these converters are highly suitable for mediumvoltage, highpower applications. Moreover, diodeclamped converters employ clamping diodes and cascaded DC capacitors to produce AC voltage waveforms with multiple levels
[10]
. Threelevel diodeclamped converters commonly known as neutralpointclamped (NPC) converters are used in numerous highpower, mediumvoltage industrial applications
[11]
. These fourleg NPC converters provide a promising topology in fourwire, mediumvoltage systems, as well as offer full utilization of DClink voltage and less stress on the DClink capacitors
[12]
,
[13]
. Both carrierbased and threedimensional space vector modulations are available for fourleg converters
[12]

[18]
.
The finitestate or finite control set model predictive control (FCSMPC) is a simple, intuitive, and powerful class of receding horizon control algorithm
[19]
controlling power converters with diverse and complex control challenges and restrictions
[20]
,
[21]
. The tool is a true modelbased optimization control strategy involving a large number of calculations
[22]

[24]
. Accordingly, available digital implementation platforms, such as microprocessors, digital signal processors, and fieldprogrammable gate arrays, can handle such computations. Recent scholarly works demonstrate the easy application of the FCSMPC in various power converters
[25]

[34]
.
This study proposes an FCSMPC to regulate the load currents while minimizing the imbalance between the DClink capacitor voltages in a fourleg NPC converter. These objectives are expressed as a cost function. The future values of the control variables for each possible switching state of the converter are predicted using the discretetime model of the system. The switching state that minimizes the cost function and meets the control goals is then selected and applied to the converter. Variable prediction is conducted over one or more sample periods. The onestep prediction horizon provides simplified analysis and computational cost, such that is widely applied in FCSMPC works on power converters
[25]
,
[30]

[32]
. Refs.
[35]
and
[36]
used simulations to demonstrate the control performance improvement under a prediction horizon of more than one step. However, Ref.
[37]
has reported that its feasibility is only verified by realtime implementation for threephase converters, but not for fourleg converters. This study uses the concept of twostep prediction to improve the regulation of load currents for different reference and load conditions. The experimental results are presented using the dSPACE DS1103 rapid prototyping realtime implementation platform to validate the feasibility of the proposed control method.
The remainder of this paper is organized as follows: Section II presents the mathematical model of the converter. Section III explains the proposed control strategy. Section IV discusses the experimental results. Section V draws the conclusions.
II. FOURLEG NPC CONVERTER TOPOLOGY
A threephase, fourleg NPC converter with an output
L
filter is shown in
Fig. 1
. This converter presents a connection format similar to that of the conventional threephase NPC converter, albeit with an additional leg connected to the neutral point of the load. The converter is composed of 16 active switches and 8 clamping diodes. The switching states and the corresponding converter terminal voltages are shown in Table I. The table shows that (a) only two switches are conducted at any time and (b) switch pairs (
S
_{1x}
,
) and (
S
_{2x}
,
) operate in a complementary manner
[10]
. A total of 81 (3
^{4}
) switching combinations are available for this converter.
Topology of the fourleg NPC converter with arbitrary load.
The voltage in any phase
x
of the converter measured from the negative point of the DClink (
N
) is expressed in terms of switching states and DClink capacitor voltages as follows (
Table I
):
SWITCHING STATES AND CONVERTER TERMINAL VOLTAGES (x=a,b,c,n)
SWITCHING STATES AND CONVERTER TERMINAL VOLTAGES (x = a, b, c, n)
The preceding converter voltages are expressed with respect to the midpoint (
n
) of the neutral leg as follows:
By solving Eqs. (1) and (2), the load voltages are expressed in terms of switching states and DClink capacitor voltages as follows:
The equivalent circuit of the fourleg NPC converter with an output
L
filter is shown in
Fig. 2
.The variables in the figure are defined in the Nomenclature section. Subscripts
a
,
b
, and
c
represent the three phases.
n
and
o
represent the converter and load neutrals, respectively. By applying Kirchhoff's voltage law in
Fig. 2
, the converter AC side voltages are expressed in terms of load voltages, load currents, and load neutral current as follows:
Representation of L filter and load connected to the fourleg NPC converter.
where
R_{f}
=
R_{fa}
=
R_{fb}
=
R_{fc}
and
L_{f}
=
L_{fa}
=
L_{fb}
=
L_{fc}
.
The relationship between the load currents and the load neutral current is obtained as follows:
By substituting Eq. (5) into Eq. (4), the converter AC side voltages can be expressed independent of the load neutral current as follows:
Where
The differential load currents from Eq. (6)are expressed as follows:
The DClink capacitor voltages are expressed in terms of DClink capacitor currents as follows:
The capacitor currents (i.e.,
are estimate during the threephase load currents (i.e.,
and the converter switching states as follows:
where
K_{x}
and
Q_{x}
depend on the voltage levels, such that
where
S_{n}
and
S_{x}
correspond to the neutral and phase levels, respectively.
sgn
is the argument sign with a value corresponding to 0, 1, or −1.
Based on Eqs. (7) and (9), the load currents and the DClink capacitor voltages are related to the switching states. Moreover, they are controlled by choosing a proper switching state.
III. FINITESTATES MODEL PREDICTIVE CONTROL
 A. Control Strategy
The proposed predictive control aims to regulate the load currents and balance the DClink capacitor voltages (
Fig. 3
). The proposed FCSMPC uses the discretemodel of the system, current state (
k
) load currents, DClink capacitor voltages, and 81 switching states to predict the future behavior of the control variables.
Proposed FCSMPC control scheme for a fourleg NPC converter.
A cost function is utilized to evaluate the predictions. The switching state leading to the minimal value of the cost function is chosen and directly applied to the converter. The proposed FCSMPC does not require linear current regulators (i.e., PI controllers) and modulation.
The 81 switching states at sampling time
k
are used to predict the converter voltage
v
^{k}
for the onestep prediction horizon, as shown in
Fig. 4
(a). The number of feasible switching states becomes 81
^{2}
= 6561 for a prediction horizon of
N
= 2. This value provides optimal performance
[38]

[40]
but greater computational burden. A modified twostep prediction is used to reduce the switching changes (i.e., switching frequency) and the computational burden caused by 6561, as shown in
Fig. 4
(b).
Control variable prediction for a fourleg NPC converter. (a) Onestep prediction. (b) Modified twostep prediction.
This approach uses 81 switching states projected to the sampling time
k
+ 2. Subsequently, the state variables achieve 81 possible conditions. The algorithm calculates all these conditions in the future sample
k
+ 2. The control strategy chooses a switching state in the sampling instant
k
, which minimizes the cost function in the
k
+ 2 sampling instant.
The system applies this switching state during the next sampling period.
 B. Cost Function Design
The defined cost function has two objectives: (a) minimize the error between the predicted load currents
i
^{k+2}
and theirreferences
i
^{∗k+2}
and (b) balance the DClink capacitor voltages. These control objectives are represented as follows:
where λ
_{dc}
is the weighting factor adjusted according to the desired performance.
The future reference currents are obtained by fourthorder Lagrange extrapolation using present and past current references. This process is demonstrated as follows
[41]
:
The final cost function is defined as follows:
The switching state that minimizes the cost function is chosen and applied at the next sampling instant. Additional constraints (e.g., switching frequency reduction, current limitation, and spectrum shaping) can be included by adding them in the cost function
[20]
.
 C. Predictive Variables with Twostep Horizon
As shown in
Fig. 3
, the cost function requires predicted load currents
i
^{k+2}
and capacitor voltages
in discretetime form.The load current prediction is obtained from continuous time state–space system in Eq. (7) as follows:
where
The load current prediction at the
k
+ 2 instant is obtained as follows:
Comparing Eq. (17) with Eq. (14), the same converter voltage vector is used in both
k
+ 1 and
k
+ 2 predictions.
The firstorder nature of the state equations describes the model in Eqs. (1)(10). Hence, this study considers a firstorder forward Euler approximation for the derivative providing sufficient accuracy. The calculation is as follows:
By substituting Eq. (18) in Eq. (8), the DClink capacitor voltages are represented in discretetime form as follows:
where
T_{s}
is the sampling time, and
C
_{1}
and
C
_{2}
are the capacitances of the DClink capacitors1 and 2, respectively.
The DClink capacitor currents are expressed in discretetime as follows:
The DClink capacitor voltages for the twostep prediction are obtained by shifting variables into one future sample. This process is exhibited as follows:
where
IV. REALTIME IMPLEMENTATION AND VALIDATION
The block diagram of the experimental setup for the proposed finitestate model predictive control of the fourleg NPC converter is shown in
Fig. 5
. The MATLAB/Simulink software is used along with a realtime implementation block set for all the control and feedback syntheses. The DS1103 controller is employed to handle the control processes (e.g., load current prediction and cost function minimization). The load currents and the DClink capacitor voltages are measured using LEM LA55P and LV25P transducers, respectively. The feedback from the sensors is sent to the controller through the CP1103 I/O connector. The DC power supply is obtained by employing the Xantrex XDC60020.
Experimental setup block diagram.
The predictive controller directly generates the gating signals. These signals are then sent to the converter through the SKHI22B gate drivers. The experimental results are obtained during the steady and transient states with balanced, unbalanced, and nonlinear loads considering a sampling time of
T_{s}
= 100 μs. The converter and controller parameters are summarized in
Table II
. The performance index parameters (i.e.,
, % total harmonic distortion (THD) and
f_{sw}
) are defined in Refs.
[42]
and
[43]
. The onestep and the proposed twostep predictions are shown in
Figs. 6
and
7
, respectively. A balanced reference of 10 A (rms) and a balanced load of 10 Ω are considered. The load currents with one stepprediction are shown in
Fig. 6
(a). This approach produces 5% reference tracking error
and 3.8%THD. The average switching frequency
f_{sw}
is 1996 Hz. The converter line–line voltage
v_{ab}
produces higher
dv
/
dts
and THD, as shown in
Fig. 6
(b). The load currents with the proposed twostep prediction are shown in
Fig. 7
(a).
, THD, and
f_{sw}
are 3.3%, 3.1%, and 724 Hz, respectively. Furthermore, the switching frequency significantly decreases with the proposed approach.
and THD are lower than those in the onestep predictiondespite the 2.8 times lower switching frequency. This method gives a new approach of controlling highpower converters that requiresan operation with alower switching frequency. The converter line–line voltage shown in
Fig. 7
(b) produces low
dv
/
dts
compared to the onestep prediction. The fast Fourier transform window shows that the peak magnitude of the harmonics is lower with the twostep prediction. The error between the DClink capacitor voltages lowers with the twostep prediction.
Experimental results of the onestep prediction during steady state with balanced references and balanced resistive load. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (100 V/div); Ch2: DClink capacitor2 voltage (100 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
Experimental results of the modified twostep prediction during steady state with balanced references and balanced resistive load. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (100 V/div); Ch2: DClink capacitor2 voltage (100 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
FOURLEG NPC CONVERTER AND CONTROLLER PARAMETERS
FOURLEG NPC CONVERTER AND CONTROLLER PARAMETERS
The experimental results of the unbalanced references (i.e.,
=12A,
=10A, and
=8A) and the balanced loads (i.e.,
R_{a}
=
R_{b}
=
R_{c}
= 10 Ω) are presented in
Fig. 8
. The setup in the figure is a typical application for the threephase, fourwire systems with different load demands in each phase. The controller independently handles each phase current. Hence, the load currents track to their references with less steadystate error, as shown in
Fig. 8
(a). The neutral current, which is the sum of the threephase currents, flows through the fourth NPC leg. The neutral current in the fourleg NPC converter does not circulate through the DClink capacitors, unlike the case of threeleg NPC converters. Hence, the DClink capacitor voltages remain balanced, as shown in
Fig. 8
(b). The converter line–line voltage perfectly shows five voltage levels.
, %THD, and
f_{sw}
are similar to the operating conditions of the previous balanced references and loads (
Fig. 7
). The operating condition discussed in
Fig. 8
is repeated with the combined unbalanced resistive load and nonlinear load (
Fig. 9
). The unbalanced load values are
R_{a}
= 8 Ω,
R_{b}
= 10 Ω,
R_{c}
= 12 Ω.The nonlinear load values are
R_{nl}
= 20 Ω and
L_{nl}
= 2.5 mH. The load variation information is not provided to the predictive controller. The controller chooses a switching state producing a minimal error in the reference tracking and DClink capacitor voltages even though the load parameters change. Consequently, the load currents effectively track to their references [
Fig. 9
(a)]. The DClink capacitor voltages are also perfectly balanced [
Fig. 9
(b)].
, %THD, and
f_{sw}
are 4.1%, 3.6%, and 1235 Hz, respectively. This increase is insignificant although these values are higher than those of the previous operating condition (
Fig. 8
). This operating condition demonstrates that the proposed FCSMPC controller is robust and handles the load parameter variations. The transient analysis is conducted considering the balanced loads (i.e.,
R_{a}
=
R_{b}
=
R_{c}
= 12 Ω). A balanced step change in the reference currents is applied from “no load” to 10 A(rms) in the first case (
Fig. 10
). The load currents track to the references with fast rise time and no overshoot [
Fig. 10
(a)]. The DClink capacitors are perfectly balanced even under the noload condition [
Fig. 10
(b)]. Step change is applied from the balanced reference currents (i.e.,
=
=
= 10 A at 60 Hz) to the unbalanced reference currents (i.e.,
= 12 A at 60 Hz,
= 10 A at 120 Hz, and
= 8 A at 120 Hz) in the second case (
Fig. 11
). The load currents track to their references and exhibit no overshoots during the transient period [
Fig. 11
(a)]. Accordingly, the load neutral current changes because of the changes in the reference currents. The DClink capacitor voltages remain balanced despite of the transient change in the reference currents [
Fig. 11
(b)]. The effectiveness of the proposed FCSMPC controller to track to any kind of references is exhibited in
Fig. 12
. A square wave reference with 5 A amplitude and 60 Hz frequency is considered. The loads are similar to those of the preceding transientstate analysis. A good load current tracking to its reference is observed with a fast and dynamic response and no oscillations in
Fig. 12
.
Experimental results of the modified twostep prediction during steady state with unbalanced references and balanced resistive load. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (50 V/div); Ch2: DClink capacitor2 voltage (50 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
Results of the modified twostep prediction during steady state with unbalanced references and unbalanced resistive + nonlinear load. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (50 V/div); Ch2: DClink capacitor2 voltage (50 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
Experimental results of the modified twostep prediction and balanced resistive load (10 Ω) during step change from “no references” to balanced references. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (50 V/div); Ch2: DClink capacitor2 voltage (50 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
Experimental results of the modified twostep prediction and balanced resistive load (10 Ω) during step change from balanced to unbalanced references. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (50 V/div); Ch2: DClink capacitor2 voltage (50 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
Experimental results of the modified twostep prediction for square wave reference and balanced resistive load (10 Ω). (a) Ch1: reference current (10 A/div) and Ch2: load current (10 A/div).
An external resistor
R_{x}
(100 Ω) is deliberately connected across the DClink capacitor
C
_{1}
to verify the robustness of the proposed algorithmin minimizing the imbalance of the DClink capacitor voltages. The balanced references of 10 A(rms) and the balanced loads of 10 Ωare considered for this test. The turnon and turnoff signals for the relay connecting and disconnecting
R_{x}
are shown in
Fig. 13
(b). The controller acts in a few sampling instants even with the stepconnection of the resistor. Hence, the capacitor voltages are continuously balanced [
Fig. 13
(b)]. The load currents continue to track to their references during this process as in
Fig. 13
(a). The feasibility of the proposed predictive control scheme is verified for different references and loads.
Experimental results of the modified twostep prediction during steady state with balanced references, balanced resistive load (10 Ω), and a resistor across the DClink capacitor1. (a) Ch1: phasea output current (10 A/div); Ch2: phaseb output current (10 A/div); Ch3: phasec output current (10 A/div); and Ch4: output neutral current (10 A/div). (b) Ch1: DClink capacitor1 voltage (50 V/div); Ch2: DClink capacitor2 voltage (50 V/div); Ch3: difference between the DClink capacitor voltages (5 V/div); and Ch4: converter line–line voltage (200 V/div).
The FCSMPC strategy strongly relies on the system model and the converter and load parameters. The tests in
Figs.9
and
13
validate that the FCSMPC strategy compensates for the changes in the load and the DClink parameter variations, respectively. The FCSMPC strategy also effectively handles the inductive filter parameter variations
[25]
,
[41]
,
[43]
. Extreme variations in the converter and load parameters deteriorate the control performance. An online parameter estimation algorithm should be used in conjunction with the FCSMPC strategy in such conditions
[33]
.
This study uses a sampling time
T_{s}
of 100 μs. This value represents the minimum execution time required to perform the optimization algorithm during each sampling interval. The
T_{s}
value dictates the switching frequency
f_{sw}
in the classical control techniques. However, the converter switching frequency in the FCSMPC strategy varies according to the operating conditions. The nature of the variableswitching frequency is controlled by including a constraint in the cost function. The steadystate performance offered by the classical and predictive control techniques is almost similar. However, the latter approach provides a superior and dynamic performance because of the elimination of internal current loops and modulators
[25]
,
[28]
,
[34]
,
[41]
. The comprehensive comparison and analysis between the classical and the proposed twostep FCSMPC are not covered in the scope of this study. Hence, these two aspects are considered as topics for future work.
V. CONCLUSIONS
This study proposes a finiteset model predictive control strategy with a twostep prediction horizon to control a threephase, fourleg NPC converter. The proposed twostep prediction significantly decreases the switching frequency while maintaining an acceptable load current quality. This method is simple and promising for the control of highpower converters. The control algorithm evaluates each of the 81 possible switching states and chooses a switching state that minimizes the cost function. The ideal minimum of the cost function is zero, which indicates that the control objectives are perfectly achieved. The load currents are tracked to their references with acceptable error using the proposed predictive control. Furthermore, the DClink capacitor voltages are balanced during all the operating conditions. The control scheme also compensates for the perturbations in the DClink and load parameter changes, while the load currents continue effective tracking to their references. This compensation is achieved without sacrificing the converter operation. The linear PI controllers and the modulation stage are further eliminated. As a result, a fast and dynamic response is achieved. Therefore, the proposed methodology is an attractive alternative for controlling fourleg NPC converters. The feasibility of the proposed algorithm is experimentally verified.
Acknowledgements
The authors wish to thank the financial support from the Natural Sciences and Engineering Research Council of Canada (NSERC) through Wind Energy Strategic Network (WESNet) Project 3.1, Fondecyt Initiation into Research 11121492, CONICYT PCCI 12048 Project and Universidad Tecnica Federico Santa Maria. This publication was made possible by NPRP grant 40772028 from the Qatar National Research Fund (a member of Qatar Foundation). The statements made herein are solely the responsibility of the authors.
BIO
Venkata Yaramasu(S'08M'14)received his M.E. and Ph.D degrees in Electrical Engineering from SGS Institute of Technology and Science, Indore, India, in 2008 and Ryerson University, Toronto, Canada, in 2014, respectively. He is currently a Postdoctoral Research Fellow with Ryerson University. His research interests include renewable energy, high power converters, electric vehicles, and predictive control.
Marco Rivera (S’09M’11) received his B.Sc. in Electronics Engineering and M.Sc. in Electrical Engineering from the Universidad de Concepción, Chile in 2007 and 2008, respectively. He earned his PhD degree at the Department of Electronics Engineering, Universidad Técnica Federico Santa María, in Valparaíso, Chile, in 2011. He is currently a professor in the Department of Industrial Technologies at Universidad de Talca, Curicó, Chile. In 2013 Prof. Rivera was awarded with the Premio Tesis de Doctorado Academia Chilena de Ciencias 2012, which is awarded to the best PhD Thesis developed in 2011 for national and foreign students in any exact or natural sciences program that is a member of the Academia Chilena de Ciencias, Chile.
Mehdi Narimani received his B.S. and M.S degrees from Isfahan University of Technology (IUT), Isfahan, Iran in 1999 and 2002 respectively, and his PhD degree from University of Western Ontario, Ontario, Canada, all in Electrical Engineering. He is currently a Postdoctoral Research Associate at the Department of Electrical and Computer Engineering at Ryerson University and Rockwell Automation Canada. He worked as a faculty member of Isfahan University of Technology from 2002 to 2009, where he was involved in design and implementation of several industrial projects. He is the author of more than 45 journal and conference proceeding papers, and he holds three patents (pending review). His current research interests include high power converters, control of power electronics, and renewable energy Systems.
Bin Wu (S'89M'92SM'99F'08) received his M.A.Sc. and Ph.D. degrees in Electrical and Computer Engineering from the University of Toronto, Toronto, ON, Canada in 1989 and 1993, respectively.In 1993, he joined Ryerson University, Toronto, where he is currently a Professor and Senior NSERC/Rockwell Automation Industrial Research Chair in Power Electronics and Electric Drives.He has has published more than 300 technical papers, authored/coauthored two WileyIEEE Press books, and holds more than 25 issued/pending patents in the area of power conversion, mediumvoltage drives, and renewable energy systems.Dr. Wu received the Gold Medal of the Governor General of Canada in 1993, Premier's Research Excellence Award in 2001, NSERC Synergy Award for Innovation in 2002, Ryerson Distinguished Scholar Award in 2003, YSGS Outstanding Contribution to Graduate Education Award, and the Professional Engineers Ontario Engineering Excellence Medal in 2014.He is a Fellow of the Engineering Institute of Canada and Canadian Academy of Engineering (CAE).
Jose Rodriguez (M'81SM'94F10) received his degree in Electrical Engineering from the Universidad Federico Santa Maria (UTFSM), Valparaiso, Chile, in 1977 and his Dr.Ing. degree in Electrical Engineering from the University of Erlangen, Erlangen, Germany, in 1985. He has been with the Department of Electronics Engineering, University Federico Santa Maria since 1977, where he is currently Full Professor and Rector. He has coauthored more than 350 journal and conference papers. His main research interests include multilevel inverters, new converter topologies, control of power converters, and adjustablespeed drives. Prof. Rodriguez is the Associate Editor of the IEEE TRANSACTIONS ON POWER ELECTRONICS, INDUSTRIAL ELECTRONICS, and INDUSTRIAL INFORMATICS. He has received a number of Best Paper Awards from different IEEE Journals. Prof. Rodríguez is a Fellow of the Chilean Academy of Engineering and of the IEEE. He was the recipient of the National Applied Sciences and Technology Award of Chile 2014.
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