This study proposes a quasifixedfrequency hysteresis current tracking control strategy for modular multilevel converters (MMCs) on the basis of voltage partition principle. First, by monitoring the grid voltage and the deviation between the output and reference currents, the output voltage is determined, thus prompting the output current to quickly and efficiently track the given current. Second, the voltages of the upper/lower capacitor of the arm and the voltages between the upper and lower arms are balanced by combining these arms with virtual loop mapping and arm voltage balance control, respectively. In particular, the proposed method is designed for any level and number of submodules. The validity of the proposed method is verified by simulations and experimental results of a fivelevel MMC prototype.
I. INTRODUCTION
Modular multilevel converter (MMC) is an innovative multilevel technology that was first used in a high voltage direct current (HVDC) transmission project in 2010
[1]
. Compared with conventional multilevel topologies, MMC offers several advantages, including low switching frequency, low harmonic, and favorable redundancy. Also, as a new topology based on doublestar chopper cell, MMC presents numerous desirable features, such as adaptability to high voltage and highpower applications, excellent fourquadrant performance, and modular structure and redundant design
[2]
,
[3]
.
To fully utilize the favorable features of MMC, considerable effort has been exerted to extend the applications of MMC from HVDC
[4]

[6]
to various fields, including highpower motor drives
[7]
, mediumvoltage STATCOM
[8]
,
[9]
, and renewable energy generation
[10]
. However, only a few reports have been published on MMC for active power filters (APFs). As a type of static power converter, APF is normally controlled to compensate for the current harmonics drained from nonlinear loads, reactive power, and imbalances of load terminals
[11]
. The dynamic performance of APF essential and largely depends on two factors, namely, realtime harmonic detection and rapid output current response. The former has been efficiently solved by instantaneous power theory, whereas the latter still requires sophisticated modulation methods.
This specific challenge has been addressed in the related literature with the implementation of several advanced modulation methods for APF. These methods include the nearest level modulation (NLM)
[12]
, phaseshifted PWM modulation (PSPWM)
[13]
and phase disposition PWM modulation (PDPWM)
[14]
. Nevertheless, NLM has limited applications because it cannot be used for multilevel converters with below 21 levels
[15]
. Meanwhile, PSPWM and PDPWM exhibit good performances in lowlevel converters, but require additional PI controllers to transfer the current reference to the output voltage, which may reduce the robustness of the system
[16]
. Moreover, these three methods have other disadvantages, including overshooting in current errors, subharmonic components in the current, limiting cycle oscillations, and nonoptimum switching vector selection
[17]
.
Hysteresis current tracking control has an inherent simplicity and rapid dynamic response, thus facilitating its wide use in many situations that require high harmonic current and current response rates, such as lowvoltage APF
[18]
and reactive power compensation
[19]
. In this method, the output current of the converter, instead of the PI controllers of the inner loop in PSPWM and PDPWM, can be directly compared with the current reference. Hysteresis current tracking control is also a closedloop control and has the advantages of high current response rate, fast realtime ability, and no need of carriers. Accordingly, applying this control in MMC is promising and can facilitate the implementations of MMC in middle and high voltage power systems.
However, due to the different topologies of MMC and common twolevel inverters, applying the hysteresis current control in MMC may induce certain problems, including the unbalanced voltage of the capacitor, unbalanced voltage between the upper and lower arms, partition of the grid side voltage, and spectral characteristics of the current ripple.
This study intends to solve the above issues by proposing a quasifixedfrequency hysteresis current tracking control (QHCTC) strategy for MMC. In this novel strategy, the frequency of MMC output current is fixed, whereas the switching frequency of submodule (SM) is quasifixed. In particular, the quasifixedfrequency is realized via virtual loop mapping (VLM), in which the SM switching frequency is similar to the output current frequency. This design can benefit the selection of switching devices and the assessment of system performances. The contributions of the proposed QHCTC are briefly described below.
First, by monitoring grid voltage and the deviation between the output and reference currents, the designed MMC can generate corresponding levels to force the output current to track the given current quickly and efficiently. In particular, the nonaverage voltage partition principle is used for the current tracking to prevent the overlap of the output and grid voltages in every voltage region.
Second, varied hysteresisband current tracking control is adopted by implementing fixed output current frequency on the basis of the above nonaverage voltage partition principle.
Third, the capacitor voltage of the upper/lower arm and the voltage between these arms are considered in the MMC design and are efficiently balanced with VLM and arm voltage balance (AVB), respectively. Accordingly, a balance control system and a quasifrequency switching device driver are achieved.
Furthermore, the proposed method is validated with the simulations and experimental results of a fivelevel prototype of MMC.
II. STRUCTURE AND OPERATION PRINCIPLES OF MMC
 A. Basic Structure
A basic threephase fourleg MMC topology is shown in
Fig. 1
, in which the MMC is composed of three legs and six arms; each leg consists of one upper arm and one lower arm, and each arm contains a buffer inductor
L
and
N
series connected SMs
[21]
. Also, phase voltages
U_{a}
,
U_{b}
, and
U_{c}
, are outputs from the intermediate connection point of the upper and lower arms, and their values depend on the difference between these arms.
Structure of a modular multilevel converter.
In
Fig. 1
, SMs adopt the half–bridge submodule (HBSM) design, which consists of a DC capacitor and two controllable power switches. HBSM is widely used in practice; its working status is shown in
Table I
where S
_{k1}
and S
_{k2}
are the driving signals of the upper and lower devices, respectively, whereas
Vc
is the average capacitor voltage of the
k^{th}
SM.
HALFBRIDGE SUBMODULE WORKING STATES
HALFBRIDGE SUBMODULE WORKING STATES
Table I
particularly illustrates that each SM has “1” and “0” statuses, and the corresponding output voltages
U_{sm}
are
Vc
and 0. In this case, “1” and “0” imply that SM is inserted and bypassed, respectively. When HBSM is inserted, the direction of
I_{sm}
signifies the working status of the capacitor. If
I_{sm}
>0, the capacitor is charging, whereas if
I_{sm}
<0, the capacitor is discharging.
 B. Operation Principles
Since the operation principles of three legs (phase
j
=
a
,
b
,
c
) are comparable, this research selects and analyzes only one leg (phase
a
) of MMC. The Kirchhoff’s voltage law demonstrates the below equations.
where
U_{P}
and
U_{N}
are DC bus voltages,
U_{ap}
and
U_{an}
are the sum of the upper and lower arm capacitor voltages, respectively,
I_{ap}
and
I_{an}
are the instantaneous current of the upper and lower arms, respectively, and
I_{a}
is the output current of MMC.
By substituting (2) in (1), the below expressions are obtained.
In traditional modulation methods, control systems provide the MMC modulation signals, which can be normalized and expressed as follows:
where
m
is the modulation index (0 ≤
m
≤ 1), and
φ_{j}
is the angular displacement of the fundamental frequency.
Without considering the circulating current suppression, the normalized reference voltage signals of the upper/lower arm should be demonstrated as follows:
These signals, in which the effects of buffer inductor
L
are ignored, have been widely used in MMC modulations such as NLM, PSPWM, and PDPWM. However,
L
has to be considered in the hysteresis current tracking control. This condition will be analyzed in the next section.
III. HYSTERESIS CURRENT TRACKING CONTROL STRATEGY
 A. Hysteresis Current Tracking Control
In general, gridconnected inverters have two control loops, namely, the outer voltage and inner current control loops, in which DC voltage regulation and current reference tracking are implemented, respectively. This research focuses on the latter and applies the hysteresis current tracking method to MMC.
In particular, this study illustrates the principle of hysteresis current tracking control by simplifying the MMC model shown in
Fig. 1
into the model depicted in
Fig. 2
, where
U_{da}(t)
is the equivalent output voltage,
L_{a}
is the equivalent inductance, and
U_{AN}
denotes the deviation between
U_{da}(t)
and grid voltage
e_{a}(t)
.
Simplified singlephase MMC circuit.
The simplified model above can be expressed by taking (3) into (4), as specified below.
Based on (8) to (12),
Fig. 3
is generated to illustrate the principle of the hysteresis current tracking control, where
h
is the hysteresis width, 0.5 and –0.5
h
denote the upper and lower thresholds, respectively, and
△i_{j}
is the deviation between output
I
and reference currents
I_{j_ref}
, as displayed in (13).
Principle of hysteresis current tracking control.
As signified in
Fig. 3
, when
△i_{j}
> 0.5h,
I_{a}
holds a downward trend with
U_{AN}
<0. Similarly, when
△i_{j}
< –0.5h,
I_{a}
holds an upward trend with
U_{AN}
>0. Thus,
I_{a}
is bounded within the hysteresis band, which is centered by the reference current. In practice, these operations can be implemented with the trigger signal of converter
D(t)
, which is defined below.
Moreover,
Fig. 3
indicates that
U_{AN}
is critical to the performance of the hysteresis current tracking control because it determines the trend of
I_{a}
and helps control the current within hysteresis bands. According to (9), generating the optimal
U_{AN}
requires an effective design of the equivalent output voltage
U_{da}(t)
and grid voltage
e_{a}(t)
. In this research, the optimal
U_{AN}
for
U_{da}(t)
is a staircase in (11) and is further expressed in (15). Meanwhile, the optimal
U_{AN}
for
e_{a}(t)
is partitioned into
N
+1 regions because converter output voltage
U_{da}
has
N
+1 levels with
N
+1 level modulation from
L_{1}
to
L_{N+1}
.Partitioned
e_{a}(t)
is expressed with the intermediate symbol
D(t)
in (16).
Notably, the width of
1^{st}
and
N+1^{th}
regions is 0.5
V_{C}
, while that of the others is
V_{C}
. This arrangement is designed to prevent misjudging the region of
e_{a}(t)
, particularly at the vicinity of the converter output level.
An example of fivelevel converter is shown in
Fig. 4
to demonstrate the relationship between the output voltage levels and grid voltage regions. In this figure,
e_{amax}
and
e_{amin}
are the peak and trough values of
e_{a}(t)
, respectively;
L_{0}
to
L_{4}
are the five output voltage levels of the MMC; and
V(t)
represents the corresponding regions. The adjacent levels generating
U_{AN}
in a specific region are grouped in common parentheses (e.g., working levels (
L_{2}
,
L_{4}
) implies
V(t)
= 4).
Output voltage levels and grid voltage regions of fivelevel converter.
In addition,
Fig. 4
presents the operation of the designed fivelevel MMC under the hysteresis current tracking control. When grid voltage
e_{a}(t)
exists in certain regions, the following cases emerge: 1) if
△i_{j}
exceeds the upper threshold (
D(t)
= 0), the MMC output voltage will be controlled to
U_{da2}(t)
to reverse the current rising trend; 2) if
△i_{j}
decreases below the lower threshold (
D(t)
= 1), the MMC output voltage will be set to
U_{da1}(t)
. Hence, the relationships of
D(t)
,
V(t)
, and
U_{da}(t)
can be summarized as denoted in
Table II
, where
U_{da1}(t)
and
U_{da2}(t)
(
U_{da1}(t)
>
U_{da2}(t)
) in each voltage partition represent the MMC output levels during the rise
T_{1}
and fall times
T_{2}
, respectively.
RELATIONSHIPS OF D(T), V(T), AND UDA(T)
RELATIONSHIPS OF D(T), V(T), AND U_{DA}(T)
Table II
suggests that the number of the inserted lower arm SMs of the MMC is equal to
N
(
t
)
[21]
.
 B. Performance Analysis
The proposed method is further analyzed by evaluating the hysteresis control in a shortterm period
T
, which consists of
T_{1}
and
T_{2}
. By assuming that the switching frequency is sufficiently high and that the influence of fundamental frequency is ignored, the switching rise and fall times can be expressed as follows:
Accordingly, the output current frequency is
By combining the previous analysis in
Table II
, the below expressions are derived.
Equations (21) to (23) indicate that the switching frequency of PWM signals for hysteresis control shows great uncertainty with a constant hysteresis width
h
. This issue induces difficulties in selecting switching devices and assessing system performance.
 C. QuasiFixedFrequency Hysteresis Current Tracking Control
The above challenges are tackled in this section by presenting the proposed QHCTC, which aims to obtain a fixed output current ripple frequency by controlling hysteresis width
h
in realtime. A brief scheme of QHCTC is illustrated in
Fig. 5
, where S/H represents the sample and hold function.
Scheme of the quasifixedfrequency hysteresis current tracking control.
As depicted in
Fig. 5
, the MMC control system has two control loops, which are the outer DC voltage and the inner current control loops. The outer loop provides current references for the inner loop to utilize QHCTC, which adjusts the closedloop current and transforms the current reference signals into corresponding PWM switching signals. These tasks can be performed with the following procedures: 1) calculate the deviation currents
△i_{a}
,
△i_{b}
, and
△i_{c}
with (13); 2) generate
D(t)
by comparing the deviation currents and hysteresis width
h
in (24); 3) obtain
N(t)
with (17).
D(t)
,
V(t)
, and
N(t)
are all available; hence, the proposed QHCTC can be implemented. From (20), hysteresis width
h
can be acquired as follows:
where
f_{M}
is a fixedfrequency square wave similar to the system sample frequency.
In this study, the control process is simplified by expressing the calculation of (17) with the true value table. Consequently, the system efficiency is expected to be improved. In this case, the Virtual SubModule (VSM)
[14
,
20]
is implemented, in which the driving signals are directly mapped from VSMs to RSMs. An
N
= 4 example is illustrated, where the PWM signals of VSMs are arranged according to (17) and are listed in
Table III
. The VSMs of lower/upper arms are numbered from
1
’ to
2N’
; 0 and 1 stand for “OFF” and “ON” status, respectively. The hysteresis result
D(t)
is assigned to VSM 5’ and VSM 6’ when V(t) is equal to 2 to 4, and /
D(t)
denotes the negated
D(t)
.
TRUE VALUE TABLE OF THE LOWER ARM VSMS
TRUE VALUE TABLE OF THE LOWER ARM VSMS
IV. BALANCE CONTROL SCHEME
In this section, the issue of balancing arm capacitor voltages, which has not been covered in the above analysis, is solved by balancing the capacitor voltage of the upper/lower arm and the voltage between the upper and lower arms with VLM and AVB, respectively.
 A. Capacitor Voltage Balance Control
VLM is applied to balance the arm capacitor voltage in each arm. VLM has been successfully used with PDPWM to balance the capacitor voltages of SMs
[20]
. The principle of VLM is to use a countup counter
C_{M}
for mapping VSMs to RSMs. The working frequency of
C_{M}
can be set as required (in this paper, it is set as 50 Hz), and its counting range is from 0 to
N
1. The entire mapping process has been technically addressed by
[14]
and
[20]
. With this method, the capacitor voltage can be efficiently balanced in case of system symmetry (Selective Virtual Loop Mapping can also be used to acquire the capacitor voltage dynamic balance even if MMC loses its symmetry, but this issue is not the focus of this research).
After implementing VLM, the PWM signals will periodically combine the components of the fundamental and high order frequencies (e.g., fixed frequency
f_{M}
). This instance is the reason why the proposed method is named as “quasifixedfrequency hysteresis current tracking control.”
 B. Arm Voltage Balance Control
Apart from the unbalance voltage issue of a single arm, the unbalance voltages over the upper and lower arms should also be considered in MMC design. The unbalance voltages over the arms are mainly derived from the difference of energy losses among the arms and the zero drift error of MMC output current. Traditionally, the voltages of the arms are balanced by adding compensation into modulation signals
[7]
. This method, however, has the following disadvantages: 1) it is complex; 2) it requires PI controllers, which may reduce the robustness of the system; 3) its output waveform can be easily distorted; 4) it cannot be applied in hysteresis control. Therefore, this study implements the AVB
[23]

[25]
control method to address the abovementioned drawbacks. The block diagram of AVB is displayed in
Fig. 6
, where
U_{jp}
and
U_{jn}
are the sum of the upper and lower arm capacitor voltages (
j
=
a, b, c
), respectively, and they can be replaced by capacitor voltages
U_{cp}
and
U_{cn}
in the single phase MMC.
Arm voltage balance control.
In
Fig. 6
, the arm voltage balance correction signal
△I_{j_ref}
is generated by a PI controller, the input of which is the difference between
U_{jp}
and
U_{jn}
, and is added to the current reference Ij_ref, that can acquire the balance between
U_{jp}
and
U_{jn.}
.
V. SIMULATIONS
The proposed method is validated by implementing a simulation on the singlephase fivelevel MMC model. The schematic figure of the tested prototype is shown in
Fig. 7
[20]
. As depicted in
Fig. 7
, the model has four SMs in one arm, and the ground point is directly connected to the midpoint of two DC sources. In this case,
e_{a}(t)
can be the grid voltage or the voltage across the load. The related system parameters are those specified in
Table IV
, in which the SM capacitor voltage is set as an average value and the influence of voltage ripple is neglected.
Prototype of a single phase MMC.
SIMULATION PARAMETERS
Fig. 8
shows the relationships of grid voltage
e_{a}(t)
, corresponding
V(t)
, and hysteresis width
h
during 0.03 s to 0.06 s. Hysteresis width
h
is variable; thus, five regions (–400, –300), (–300, –100), (–100, 100), (100, 300), (300, 400) evidently exist, as indicated by
V(t)
= 1 to
V(t)
= 5, respectively.
Relationships of e_{a}(t), V(t), and h.
Fig. 9
indicates the relationships among
V(t)
,
U_{da1}(t)
, and
U_{da2}(t)
. In particular, this figure demonstrates that
U_{da1}(t)
>
U_{da2}(t)
holds in general, but the difference between
U_{da1}(t)
and
U_{da2}(t)
varies. Moreover, if
V(t)
is equal to 1 or 5, the voltage difference is
V_{c}
; otherwise, the voltage difference is 2
V_{c}
.
V(t) and the corresponding MMC output levels U_{da1}(t) and U_{da2}(t).
Fig. 10
presents the consequences of the proposed QHCTC. In particular, the MMC output voltage with reference current
I_{a_ref}
and MMC output current
I_{a}
are shown in
Figs. 10
(a) and (b), respectively. Meanwhile,
Fig. 10
(c) is the zoomed results of
Fig. 10
(b) from 0.04 s to 0.042 s, indicating that the actual current can efficiently follow the reference current with a fixedfrequency.
Consequence of QHCTC: (a) Ua(t), (b) I_{aref}, and I_{a}, (c) and zoomed results between 0.04 and 0.042 s.
Figs. 11
(a) to (d) exhibit the PWM signals of RSMs 1 to 4 in the upper arm. These figures particularly illustrate that the frequency components in each PWM signal have two kinds, namely, the lowfrequency and fixed highfrequency components. The lowfrequency component depends on the PWM signals continuity, as specified in
Table III
. For example, when
V(t)
is equal to 1, 2, and 3, the PWM signals of VSMs 4’ are all working in “1” state, whereas the PWM signals of VSMs 4’ are working in “0” statewhen
V(t)
is equivalent to 4 and 5. Meanwhile, the high frequency component of PWM 4 is zoomed in
Fig. 11
(e), and its frequency is about 5 kHz, which is equal to
f_{M}
. A 0.02 s delay exists among these PWM signals due to the 50 Hz counter frequency of VLM.
PWM signals of SMs 1 to 4 between 0 and 0.12 s. (a) PWM1; (b) PWM2; (c) PWM3; (d) PWM4; (e) Zoomed PWM4 between 0.08 and 0.09 s.
Fig. 12
is the spectrum of
I_{a}
. In this case, THD is about 3.07%, and the main frequency component is concentrated at nearly 5 kHz.
Spectrum of output current I_{a}.
VI. EXPERIMENTS
The feasibility of the proposed method is further verified by conducting singlephase experiments under low voltage on an MMC test bench. This time, grid voltage source
e_{a}(t)
is replaced with a 15 Ω resistor. The experimental parameters are listed in
Table V
.
EXPERIMENTAL PARAMETERS
Fig. 13
(a) shows the output voltage and current of the MMC in the case of fivelevel modulation, and
Fig. 13
(b) depicts the corresponding zoomed region of
Fig. 13
(a).
(a) Output voltage and current of the experimental system. (b) Zoomed voltage and current waveforms of the experimental system.
Fig. 14
reveals the output waveforms between PDPWM (VLM is used) and QHCTC. In particular, this figure evidently demonstrates that the latter has a smoother current waveform, particularly in the vicinity of the peak output current.
Output voltage and current of the experimental system.
Fig. 15
(a) describes the output voltage and corresponding PWM signal of one SM, and
Fig. 15
(b) is the corresponding zoomed region.
(a) Output voltage and PWM signal. (b) Zoomed voltage and PWM signal waveforms.
Meanwhile,
Fig. 16
shows the MMC output voltage and current waveforms when the reference current amplitude and phase transitions simultaneously occur. The reference current amplitude changes from 6.2 A to 4 A, accompanied by a 90° phase shift. The result of the test indicates that the actual output current can rapidly track the reference current and demonstrates the high dynamic response capability of the proposed method.
Output voltage and current of the experimental system in the condition of the reference current’s amplitude and phase transition
In this experiment, the arm voltage balance control is also tested with the existence of some zero drift in the output current sensor.
Fig. 17
(a) illustrates the output voltage and current when the lower arm voltage is greater than the upper arm voltage. The output voltage and current distortion evidently occur in 17(a). Meanwhile,
Fig. 17
(b) presents the variation processes of the output voltage and current when the arm voltage control is applied. The results of the test show that the unbalance voltage of arms is effectively corrected.
(a) Output voltage and current when arm voltage loses balance. (b) Output voltage and current when arm voltage control is adopted.
VII. CONCLUSIONS
This study proposes a new QHCTC strategy for MMCs based on the nonaverage voltage partition principle. The inserted number of the MMC lower arm SMs
N(t)
is presented by derivation. By implementing both VLM and AVB, the capacitors’ voltages of the upper/lower arms are efficiently balanced.
The proposed method is designed for any number and levels of SMs, and its validity is verified with the experimental results on a singlephase fivelevel MMC prototype.
BIO
Jun Mei received his B.S. degree in radio engineering from the Chongqing University in 1994 and his M.S. and Ph.D. degrees in electrical engineering from the Southeast University, Nanjing, China, in 2001 and 2006, respectively. At present, he is an Associate Professor in the Department of Electrical Engineering, Southeast University. His interests include electric power converters for distributed energy sources, FACTS, and power quality control.
Yu Ji received his B.S.E.E and M.S.E.E. degrees from the Southeast University, Nanjing, China, in 2009 and 2012, respectively. He is currently pursuing his Ph.D. degree in electrical engineering at the same academe. His current research interests include the application of power electronics in power system, voltage source converterbased HVDC, controlling technique and developing the multilevel inverters of HVDC.
Xiaozhou Du received his B.S.E.E degree from Anhui University, Hefei, China, in 2012, and is currently pursuing M.S.E.E. in electrical engineering at Southeast University, Nanjing, China. His current research interests include the application of power electronics in power system and voltage source converterbased HVDC.
Tian Ma received his B.S.E.E degree from Southeast University, Nanjing, China, in 2013, and is currently pursuing M.S.E.E. in electrical engineering in Southeast University, Nanjing, China. His current research interests include the application of power electronics in power system and voltage source converterbased HVDC.
Can Huang received his B.S.E.E degree from Hohai University, Nanjing, China, in 2008, and M.S.E.E. degree from Southeast University, Nanjing, China, in 2011. He was with the State Grid Electric Power Research Institute (NARI Group Corporation), Nanjing, China, from 2011 to 2012. Currently, he is a Ph.D. candidate in electrical engineering at the University of Tennessee, Knoxville, TN, USA. His research interests include energy conversion and integration, power system operation and planning, and IT applications in power system measurement, protection. and communication.
Qinran Hu received his B.S.E.E. degree from Southeast University, Nanjing, China, in 2010, and M.S.E.E. degree from the University of Tennessee, Knoxville, TN, USA, in 2013. He is currently pursuing his Ph.D. degree in electrical engineering at the University of Tennessee. His research interests include renewable energy integration, smart energy management system, and power system optimization.
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