This study analyzes a ladder multilevel converter (double ladder topology) with the use of a new averaging modeling technique. This technique introduces an analytical method to compute for the switching losses and is used to conduct an indepth analysis of the influence of the switching frequency and parasitic resistance of components on converter efficiency. The obtained results enable the selection of switches and switching frequency to minimize losses. Moreover, simulation results and experimental measurements validate the analytical calculations.
I. INTRODUCTION
Achieving high efficiency on power converters is one of the main issues of power electronics
[1]
,
[2]
,
[37]
,
[38]
. Two main issues related to efficiency are conduction and switching losses. Conduction losses can be resolved by reducing the ON resistance on power MOSFETs, reducing the forward voltage on power diodes or IGBTs and using passive components with low parasitic resistance
[22]

[26]
. Semiconductor devices are also becoming faster. Power diodes with low reverse recovery current have also been developed to reduce switching losses
[3]
.
In addition to the reduction of switching losses, semiconductor devices with high reverse voltage have also been developed. Although these new devices expand the possibilities for highvoltage and highfrequency use, classical converters, such as buck or boost, still face some limitations in terms of applications of several kilovolts
[4]

[8]
,
[27]
,
[28]
. Multilevel converters were proposed to deal with the highvoltage problem of classical converters. Multilevel converters manage the highvoltage problem (several kilovolts) with the use of lowvoltage components (hundreds of volts). Among the multilevel converters, some, such as the ladder multilevel DC/DC converter, use only capacitive components (switched capacitors (SC)) in their power circuit, reducing size and weight
[9]

[15]
,
[29]

[31]
. In
[16]
, the classical ladder topology (CLT) and two variations were presented. The double ladder topology (DLT) was shown to produce less output resistance and less output voltage ripple, which makes this topology highly efficient and suitable for implementation.
In addition to efficiency, a control law is required by power converters. In most cases, a mathematical model of the converter is required. These converters are often modeled with the use of the classical averaging technique
[32]
. However, this technique works under the assumption of slow dynamics on each switching state. If such assumption is unfulfilled, then an inaccurate model can be obtained.
In an SC converter, capacitors with different voltages can be connected in parallel, producing current spikes. Given that the equivalent series resistance (ESR) of the capacitors and the ON resistance of the interconnection switches are usually small, the equivalent time constant
τ
of the resulting circuit is also small. Therefore, the dynamics are rapid compared with the switching period
T
(see
Fig. 1
). With consideration of the rapid dynamics of the current of the capacitors, the assumption for the classical averaging model is unfulfilled. In
[17]
, a new analytical modeling technique that obtains an equivalent continuous model of a switched converter regardless of the dynamics on each switching state is proposed. The technique is called generalized equivalent continuous model (GECM). In this study, this technique is used to analyze the behavior of the converter and optimize its efficiency.
Capacitor current waveform for different τ values. T represents the switching period.
Fig. 1
shows that, for a small
τ
(i.e., small ESR and switch ON resistance), the current waveform presents an exponential shape and higher current spikes than for a large
τ
value (i.e., higher ESR and switch ON resistance). Moreover, given the charge balance, the waveforms should have the same average in each cycle. If the average is the same, then we can conclude that the exponential waveform has a higher root mean square (
RM S
) value. Therefore, reducing the resistor value
R
implies an increase in the
RM S
value. Given that the power losses in resistor
R
are expressed as
, no conclusion on power losses can be easily drawn.
In
[1]
,
[18]

[20]
,
[33]
, and
[34]
, power losses in SC converters are resolved and analyzed. In SC converters, reducing the ON resistance of the switches or ESR does not necessarily imply higher efficiency. In
[1]
and
[18]
, analytical calculations of the conduction energy losses of an SC converter are presented. These calculations are essentially the same that the GECM conducted under all matrix operations. Therefore, the results of conduction losses only are the same. However, the GECM is easier to compute using a convenient state space form and works for any circuit topology modeling its dynamics. In
[33]
, an analysis method that completely omits parasitic resistances is presented. Therefore, it cannot be computed in the state space form (GECM). References
[20]
and
[34]
provide a basic mathematical demonstration on how an ideal SC converter (without parasitic resistances) generates energy losses and how to prevent energy losses. However, no specific calculation of the losses is conducted. In
[19]
, a different approach is presented. Using the example proposed in Section VI of reference
[19]
, an approximation of the output resistance is obtained at the switching frequency of 30 MHz, producing a 5% error. This error can be eliminated using GECM. Notably, none of the previous works considered switching losses.
In this study, the GECM approach is applied to the DLT converter with eight cells for highvoltage application. The components of the converter are selected to optimize its efficiency with consideration of conduction and switching losses. Moreover, the converter is implemented and experimental measurements are taken.
This paper is organized as follows: Section II presents the DLT. Section III highlights the different modeling techniques. Section IV analyzes the switching losses. Finally, Section V demonstrates the efficiency of the DLT with the use of the new modeling technique.
II. LADDER MULTILEVEL CONVERTER
Fig. 2
shows the generalized DLT proposed in
[16]
. This converter has
N_{C}
basic cells (
Fig. 3
) and an ideal output voltage
V_{out}
= (
N_{C}
+ 1)
V_{in}
. This converter works with two control signals, one with 50% duty cycle for switches
SW
_{1}
and the other complementary for switches
SW
_{2}
[21]
,
[35]
. The DLT presents less output voltage drop and less ripple in comparison with the CLT
[16]
.
DLT of a DC/DC voltage multilevel elevator with N_{C} cells. SW_{1} and SW_{2} are complementary. Average currents are shown during each cycle.
Basic cell of the ladder multilevel converter.
The basic cell shown in
Fig. 3
consists of two capacitive elements (
C
_{1}
and
C
_{2}
) and four switching components (two
SW
_{1}
and two
SW
_{2}
). When switches
SW
_{1}
are ON while
SW
_{2}
are OFF , the input voltage source
V_{in}
charges the capacitor
C
_{1}
. In the other half cycle, with
SW
_{2}
ON and
SW
_{1}
OFF, the capacitor
C
_{1}
charges the capacitor
C
_{2}
, which ideally results in
V_{out}
= 2
V_{in}
.
The connection between capacitors is affected by the ON resistance of the switches and the ESR of each capacitor, thus producing voltage drops. Furthermore, the time constant of the equivalent circuit, which depends on the capacitance and resistance values, affects the current waveform on the capacitors: a large time constant produces a square waveform, whereas a small time constant produces an exponential waveform, as previously shown in
Fig. 1
.
As stated previously, when the time constant is small compared with the switching period, the classical averaging model cannot produce an accurate model
[17]
.
III. MODELING TECHNIQUES
The model of ladder converters can be written as a switched system. Mode 1 is represented by
σ
= 1 and occurs when
SW
_{1}
= ON (
SW
_{2}
= OFF) . Mode 2 is represented by
σ
= 2 and occurs when
SW
_{1}
= OFF(
SW
_{2}
= ON) . Thus, the dynamics of the converter can be written as follows:
where
x
and
are the voltages of the capacitors and their derivatives, respectively.
u
represents input variables (input voltage
V_{in}
) and
y
represents output variables (output voltage
V_{out}
). The matrices of each mode
A
_{1}
,
B
_{1}
,
F
_{1}
,
G
_{1}
and
A
_{2}
,
B
_{2}
,
F
_{2}
,
G
_{2}
can be computed using classical circuit analysis. The values of these matrices depend on the value of each capacitor, as well as the values of the ESR and the resistances of the switches.
From this switched model, we can deduce two modeling techniques, namely, the classical averaging model and the GECM.
 A. Classical Averaging Model
When we assumed that the state space vector
x
is constant when each mode is active, the classical averaging technique is deduced
[32]
. With this assumption, the average model from Eqs. (1) and (2) can be computed as follows:
where 〈∗〉 is the average of the argument and
d
is the duty cycle. However, as shown in
Fig. 1
, capacitor voltages in ladder topologies can considerably vary during each mode. Then, classical averaging model is not an appropriate method to characterize ladder converters.
 B. Generalized Equivalent Continuous Model
A new analytical modeling technique was proposed in
[17]
to deal with highspeed dynamics. In this method, the assumption of slow variation in the state vector
x
during each mode is eliminated. This subsection briefly presents the method. The following steps show the procedure to obtain this model:
1) Obtain the State Space Matrices of Each Switching State:
The analysis starts with the matrices
A_{σ}
,
B_{σ}
,
F_{σ}
, and
G_{σ}
for
σ
= {1,2}. These matrices are obtained from the model shown in Eqs. (1) and (2).
2) Reorganize the State Space Matrices:
Previous matrices are unsuitable for the model. Then, the matrices
,
,
, and
are computed as follows:
with
σ
= {1,2}. Thus, the system is transformed into
where
3) Calculate Φ
_{1}
(
dT
)
and
Φ
_{2}
((1 −
d
)
T
) : The state transition matrices are computed, but have to be evaluated in
dT
. Thus,
Φ
_{1}
(
dT
) and
Φ
_{2}
(
dT
) are expressed as follows:
4) Calculate
: Matrix
represents the transition matrix in one switching period
T
. The two modes are presented in this matrix.
is computed as follows:
5) Calculate
Ω
_{1}
and
Ω
_{2}
:
Ω
_{1}
and
Ω
_{2}
are defined as the integrals of the functions
Φ
_{1}
(
t
) and
Φ
_{2}
(
t
), respectively. These integrals enable the generation of the average dynamics of each mode, which are obtained as follows:
An analytical solution of
Ω
_{1}
and
Ω
_{2}
exists when
,
σ
= {1,2} is nonsingular. In this case, we obtain the following equation:
where
d
_{1}
=
d
and
d
_{2}
= 1 −
d
. When
is singular, it should be numerically computed. Indeed, numerical integration is an approximation of the integral real value.
6) Calculate Γ
: Defining the matrix
Γ
in the function of
Ω
_{1}
and
Ω
_{2}
is also necessary. Using the results of the previous step, the value of
Γ
can be computed as follows:
7) Obtain the Matrix
: The proposed continuous model is expressed as follows:
Information on 〈
A
〉 and 〈
B
〉 is inside matrix
. This matrix describes the average dynamics and can be obtained as follows:
Γ
and
are previously defined. Indeed,
has the following form:
Then, 〈
A
〉 and 〈
B
〉 can be derived from
.
8) Calculate Γ_{Ƒ}
: Matrix
Γ_{Ƒ}
is necessary to compute the output model, as follows:
9) Obtain the Matrix
〈
Ƒ
〉: The continuous model for 〈
x
〉 is obtained using Eq. (14). The continuous model for the output
y
is obtained as follows:
As shown in Step 7, matrix 〈
Ƒ
〉 exists, which contains 〈
F
〉 and 〈
G
〉. This matrix is expressed as follows:
where 〈
Ƒ
〉 is derived from:
where
Γ_{Ƒ}
and
Γ
are derived from Eqs. (17) and (13), respectively.
10) Obtain the Final State Space Matrices
: Finally, the results from Steps 7 and 9 are separated as shown respectively in Eqs. (16) and (19), to obtain the state space matrices 〈
A
〉, 〈
B
〉, 〈
F
〉, and 〈
G
〉. These matrices describe the average system behavior.
 C. Basic Cell Example
In this section, the GECM is applied to the basic ladder multilevel converter shown in
Fig. 3
.
Fig. 4
shows the two possible modes of the basic cell, with the parasitic resistances of each component (ESR of capacitors denoted as
R_{C}
and ON resistance of the MOSFETs denoted as
R_{ON}
).
Switching modes with parasitic resistances. (a) SW_{1} ON; SW_{2} OFF. (b) SW_{1} OFF; SW_{2} ON.
To obtain a model of the system in state space variables, such as in Eqs. (1) and (2), the state space vector
x
, the input
u
, and the output
y
are defined as follows:
For the mode shown in
Fig. 4
(a), the state space matrices are calculated as follows:
For the mode shown in
Fig. 4
(b), the state space matrices are calculated as follows:
with:
.
For this numerical example, we considered the following values of the components:
R_{ON}
= 1.8 Ω,
C
_{1}
=
C
_{2}
= 2.2 μF,
R_{C}
= 2.5 mΩ, and
R_{bad}
= 50 Ω. The switching frequency for this example is
f
= 50 kHz, with a duty cycle
d
= 0.5.
The equivalent state space matrices that describe the system behavior using classical averaging model are computed. The matrices are expressed as follows:
The matrices for the GECM, following the steps previously explained, are expressed as follows:
Fig. 5
shows a comparison of the step response for both models (classical averaging and GECM) and the real behavior of the converter in simulation. We observed that the GECM produces better results than the classical averaging model because it is capable of computing the real average of
V_{out}
. For more information on this example, see
[36]
.
Comparison of the classical averaging model, the GECM, and the switched response.
IV. SWITCHING LOSSES
In this section, an analytical method to estimate the switching losses of the converter is presented. This method uses the results of the GECM to analyze the system dynamics.
 A. General Case
Let the voltages of the switches (open) and their currents (closed) be organized as follows:
where
j
is the number of switches.
The matrix
from Eq. (10) defines a discrete model of the initial conditions of the mode
σ
= 1. Therefore, the following model can be defined using Eq. (26):
where:
with
z
_{0}
being the discrete version of
z
and
x
_{0}
being the discrete version of
x
.
Matrices
and
represent the relationship between open voltages
and closed currents
of the switches, the capacitor voltages, and the input (
z
_{0}
).
Fig. 6
shows the switching waveforms of a switch with a trapezoidal approximation of the switching losses. We assumed that the turnon and turnoff times are small as compared with the system time constant. Under this assumption, the value of the state space vector is the same right before switching and right after switching (i.e., the value of the state space vector is
z
_{0}
(0) in time instants marked as
a
and
b
in
Fig. 6
). Therefore, the voltages of the switches (open) and their currents (closed) can be computed in terms of
z
_{0}
regardless their state in each subsystem.
Switching waveforms of Q_{1} with switch turnon time t_{tom} and turnoff time t_{off}.
Notably, all voltages and currents in the instants marked as
a
and
b
in
Fig. 6
are calculated. Computing the same voltages and currents in the next switching instant
z
_{1}
is also necessary. The state space vector in the next switching instant can be defined as follows:
Using this definition, additional voltages and currents can be computed and added to the system in Eq. (27), expanding matrices
and
as follows:
Therefore, the new system is defined as follows:
Similar to the case of the GECM, the matrices of Eq. (31) can be decomposed to be used with the original discrete state space vector
x
_{0}
and the input
u
, as follows:
To compute the switching losses in steady state, the steadystate value of the outputs is required. The steadystate values of the voltages and currents can be computed as follows:
Finally, the switching losses in steady state can be obtained using the previous results as follows:
where:
and
where the function
diag
(∗) generates a diagonal matrix with the elements of the argument. Matrix
M
is scaled by 1/6 because of the trapezoidal resistive switching approximation
[37]
.
 B. Basic Cell Example
In this subsection, a numerical example on how to compute the switching losses is applied to the basic ladder multilevel converter shown in
Fig. 3
. The switches are numbered from bottom to top (
Fig. 3
). Only the computation of the losses for switches
Q
_{1}
and
Q
_{2}
is shown. Therefore, the following vectors can be defined:
1) Compute the Voltages and Currents of the Switches
: We compute the matrices
and
from Eq. (27). For instance, the calculation of the open voltage of
Q
_{1}
should be computed in the mode
σ
= 2 (
Fig. 4
(b)) and
Q
_{2}
should be computed in the mode
σ
= 1 (
Fig. 4
(a)), as follows:
where:
Replacing numerical values, the following results are obtained:
2) Create the Matrices
*
and
*: We expand the matrices
and
using Eq. (9), as follows:
3) Create Matrix M
: The matrix
M
contains the information on the turnon and turnoff time of the switches. For this numerical example,
t_{ton}
= 200 ns and
t_{toff}
= 150 ns.
4) Decompose the Matrices
: We obtain the matrices from Eq. (32) using the results in Eqs. (10), (43), and (44), as follows:
5) Compute the SteadyState Values of the Currents and Voltages
: We compute the steadystate values of the voltages and currents using Eq. (33) and the results of the previous step (
u
=
V_{in}
= 340), as follows:
6) Compute the Switching Power Losses
:
Using Eqs. (34) and (45) and the results of the previous step, the total switching power losses for
Q
_{1}
and
Q
_{2}
can be computed as follows:
With consideration of the switching power losses, the efficiency of the converter can be computed as follows:
For this case, the output voltage of the converter is not significantly affected by switching losses. Therefore,
P_{out}
and
P_{Cbss}
can be computed with the GECM.
Fig. 7
shows a comparison between the theoretical calculation of efficiency (with and without switching losses) and the respective simulations for different switching frequencies while considering all switches in the basic cell. The estimation obtained using the analytical method reflects correctly the behavior of these losses.
Comparison of theoretical efficiency with simulation for the basic cell.
V. ANALYSIS OF THE CONVERTER
In this section, the DLT is analyzed using the new techniques introduced in Sections III and IV. An indepth analysis is conducted for this topology to show the effect on the efficiency caused by the switching frequency and the parasitic resistances of the switches. The GECM is validated using the DLT in
[36]
.
Fig. 8
shows an equivalent model of the converter. In this model,
N
represents the ideal voltage gain and the resistance
R_{out}
represents the losses. The resistance
R_{out}
is dependent on the switching frequency of the converter and the values of ON resistances of the switches and ESR of the capacitors.
Equivalent model of an SC converter with a DC/DC transformer, where N is the gain of the converter with no load and R_{out} is the output resistance.
Given that the new modeling technique is able to model accurately the SC converter, it is used to analyze and optimize the DLT for implementation.
The nominal values of the converter are as follows: input voltage
V_{in}
= 350 V; output voltage
V_{out}
= 3,000 V; output current
I_{out}
= 100 mA; number of cells
N_{c}
= 8. For this example, a commercial capacitor
C
= 2.2 μF ,
ESR
= 2.5 mΩ is used.
Using the GECM, we observed that the duty cycle of maximum gain is independent of the load value and switching frequency and is always
d
= 0.5. Moreover, the gain
V_{out}
/
d
is insufficient to use
d
as control signal. Therefore, the duty cycle is set to a constant value
d
= 0.5. As mentioned previously, no conclusion on efficiency can be easily drawn because of the effect on the current waveform when the time constants are small compared with the switching period. Using the results obtained in Section IV, the efficiency of the converter can be computed analytically.
The following criteria is considered when selecting an adequate value for the switching frequency and
R_{S}
: The value of
R_{S}
should be as high as possible without compromising efficiency. In this converter, the lower the
R_{S}
, the higher the current spikes in the switches, producing overcurrents.
Fig. 9
shows efficiency as a function of
f
and
R_{S}
. The values of
R_{S}
and
f
are selected as follows: First, the highest possible value of
R_{S}
that can be classified into the lighter region is selected and restricted to commercial values. A frequency value that can also be classified into this region is then selected.
Fig. 10
shows the detailed effect of switching frequency on a given
R_{S}
. The value that produces the highest efficiency can be easily selected. The values of
R_{S}
= 1.8 Ω (NMOS transistor P8NK100Z) and
f
= 80 kHz are selected, with an efficiency of 92.5%. We observed no increments in efficiency of over 1% for any other possible values of frequency and resistance.
Efficiency as a function of the switch resistance R_{S} and switching frequency f. The dot marks the selected values R_{S} = 1.8 Ω and f = 80 kHz, with an efficiency of 92.5%.
Comparison of the efficiency obtained using the theoretical model for three different values of switch ON resistance R_{S} (conduction losses only (CL) and conduction and switching losses (CL+SL)).
Fig. 10
shows the efficiency of three different switch resistances as a function of switching frequency to compare in detail the influence of switching frequency and switch resistance. The results of the GECM (where no switching losses are considered) are compared with the results of the GECM with the addition of switching losses for each switch. When the charging and discharging process of capacitors is completed in one switching period, the losses are independent of the
R_{S}
(conduction only) value and are attributed to the inherent energy losses caused by voltage differences of the capacitors when they are connected. However, including switching losses, at low frequencies, the lower the
R_{S}
, the higher the losses.
Although efficiency is slightly higher with
R_{S}
= 0.18 Ω at different frequencies in comparison with
R_{S}
= 1.8 Ω at
f
= 80 kHz (increment < 1% ), the current spikes are dramatically higher with
R_{S}
= 0.18 Ω (up to 16.6 A ) in comparison with the selected values (up to 3.3 A).
Experimental measurements are conducted to validate the analysis of the converter.
Fig. 11
shows a comparison among the analytical, simulated, and experimental efficiencies. The simulated and experimental results present a relative error below 4% compared with the analytical results, with switching losses for all the tested cases. Power loss attributed to switching is 5.5%, with
R_{S}
= 1.8 Ω and
f
= 80 kHz.
Comparison of the efficiency obtained using the theoretical model with and without switching losses, simulation results, and experimental measurements with R_{S} = 1.8 Ω.
VI. CONCLUSIONS
In this study, a method for computing switching losses is introduced, and a new modeling technique is used to analyze the efficiency of an SC converter. This technique is helpful when the dynamics of each mode of the switched system are characterized as rapid when compared with the switching period.
The DLT was analyzed with the use of the new model, and the optimal parameter values were obtained. We observed that the highest efficiency is not necessarily achieved with the smallest resistor values and it depends on the switching frequency. Therefore, careful analysis is required to achieve the highest efficiency point.
Experimental measurements and simulations were conducted to validate the analytical results. An efficiency of 92.5% was obtained at 80 kHz, with switching losses of 5.5%.
Acknowledgements
The authors acknowledge the support provided by the research project “Conversión de múltiples puertos, interconexión y asignación dinámica de energía de generadores PV distribuidos” of Pontificia Universidad Javeriana—Vicerectoría de Investigación—Project No. 004018.
BIO
Andrés Lopez obtained his B.Sc. degree in Electronics Engineering from Pontificia Universidad Javeriana, Bogotá, Colombia in 2010. He obtained his M.Sc. degree from the same university in 2012. Currently, he is doing his Ph.D. in Australia. His research interests include SC converters and modeling and control of power converters.
Diego Patino was born in Manizales Colombia. He has written several articles. He obtained his degree in Electronics Engineering from la Universidad Nacional. He obtained his Master’s Degree from la Universidad de Los Andes, Bogota. He has a Ph.D. in automatic control from Nancy University, France. Currently, he works as fulltime professor at Pontificia Universidad Javeriana, Bogota, Colombia. His main research interests are hybrid dynamical systems, power converters, and nonlinear control theory.
Rafael Diez received his B.Sc. degree in Electronics Engineering from Pontificia Universidad Javeriana, Bogotá, Colombia in 2001. He obtained his M.Sc. in Microelectronics in 2005 and his Ph.D. in Electrical Engineering in 2008 from Université de Toulouse, France. He is currently with the Department of Electronics of Pontificia Universidad Javeriana. His main interest is the development of power converters for electric discharges.
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