This study proposes a novel fivelevel threephase hybridclamped converter composed of only six switches and one flying capacitor (FC) per phase. The capacitorvoltagedrift phenomenon of the converter under the classical sinusoidal pulse width modulation (SPWM) strategy is comprehensively analyzed. The average current, which flows into the FC, is a function of power factor and modulation index and does not remain at zero. Thus, a specific modulation strategy based on space vector modulation (SVM) is developed to balance the voltage of DClink and FCs by injecting a commonmode voltage. This strategy applies the fivesegment method to synthesize the voltage vector, such that switching losses are reduced while optional vector sequences are increased. The best vector sequence is then selected on the basis of the minimized cost function to suppress the divergence of the capacitor voltage. This study further proposes a startup method that charges the DClink and FCs without any additional circuits. Simulation and experimental results verify the validity of the proposed converter, modulation strategy, and precharge method.
I. INTRODUCTION
Multilevel converters have attracted considerable attention from both the industry and the academia for their use in highpower applications, such as highvoltage directcurrent (HVDC) transmission, reactive power compensation, and mediumvoltage industrial drives
[1]
. In this voltage range, multilevel converters are preferred to overcome the voltage blocking limitations of the available semiconductor switches
[2]
,
[3]
. Multilevel converters used in low voltage have recently become a focus
[4]

[7]
, given that such technology can produce more levels than the conventional twolevel converters in the output voltage waveforms, thus resulting in a superior harmonic spectrum and lower switching losses
[8]
. However, in multilevel converters, the increasing number of components containing switches, clamping diodes, and capacitors tends to increase the conduction losses and reduce the overall reliability
[9]
. Thus, to design a multilevel converter with reduced components remains an attractive but challenging task.
The basic concept of a multilevel converter is to synthesize a desired AC voltage through several voltage levels, which are produced by separate DC sources or large capacitors with voltage balance control. Among numerous multilevel converter topologies that have been proposed over the past decades, three classic or traditional topologies exist. These topologies are the neutral point clamped (NPC)
[10]
,
[11]
, the flying capacitors (FCs)
[12]
, and the cascade Hbridge (CHB)
[13]
. In CHB converters, several isolated DC sources are necessary to produce active power. The DC sources are mainly generated by isolation transformers, which are bulky and expensive
[1]
. Thus, the NPC and FC with a single DC source is preferred. In NPC, different voltage levels are provided by series DClink capacitors. However, the NPC converter providing more than three levels requires numerous clamping diodes and encounters a voltagedrift phenomenon in some operating regions
[14]

[16]
. Correspondingly, the operating regions are enlarged in FC converters, in which different voltage levels are clamped by FCs in each phase. However, massive FCs are required as voltage level increases, thus increasing the cost and control complexity
[17]
.
According to the aforementioned drawbacks of NPC and FC, lowlevel converters are commercially used in industrial applications, such as the 3LNPC and 4LFC
[18]
. To improve the voltage levels with one DC source, hybrid multilevel converters are developed
[19]
. In hybrid multilevel converters, more voltage levels can be generated with the same number of components by adopting different intermediatecircuit capacitor voltages
[9]
. The NPCHB multilevel converter, which is composed of a series connection of a main threelevel NPC converter and an auxiliary floating Hbridge, has been studied in
[3]
,
[9]
, and
[20]
. Given the different capacitor voltages of the Hbridge, the NPCHB converter can be a five, seven, or ninelevel converter, which is flexible and attractive. However, eight switches are used in each phase of the NPCHB, and four series switches should pass through the conduction path. The conduction voltage drop is relatively large if the converter is adopted in lowvoltage applications. A fivelevel active neutralpoint clamped (ANPC) converter is another attractive hybrid converter
[21]

[23]
that can be considered as the combination of a threelevel ANPC converter and a twolevel cell. Eight switches are necessary for one phase of ANPC if different blockingvoltage switches are adopted. In this case, three switches, fewer than that in NPCHB, are on the conduction path.
Based on the principles of reducing components and conduction losses, a novel fivelevel hybrid converter is proposed in this study. Each phase of the proposed converter contains only six switches, and the switches on the conduction path are reduced to two. The hybrid converter is a combination of an FC cell and a threelevel transistorclamped converter (TCC), which has high efficiency in lowvoltage applications
[6]
.
This paper is organized as follows: Section II introduces the topology and operating principles of the proposed converter. Section III presents an analysis of the voltagedrift phenomenon of the converter based on SPWM. Section IV discusses a modulation strategy based on space vector theory to balance the voltage of DClink and FCs. Section V evaluates the performance of the introduced converter under the proposed modulation strategy in various operating conditions on the basis of simulation studies. Section VI presents the implementation of the method to precharge capacitors before the converter startup without additional circuits. In addition, the feasibility of the converter and modulation strategy is verified through an experiment.
II. CONVERTER TOPOLOGY
 A. Proposed FiveLevel HybridClamped Converter
Fig. 1
shows the topology of Phase A. The hybrid converter combines the 3LTCC and FC cell into one circuit. In the converter, S
_{5}
and S
_{6}
are combined into a bidirectional switch. Another type of the bidirectional switch could also be selected, as discussed in
[24]
. As shown in
Fig. 1
, the DC bus is composed of two series capacitors,
C
_{d1}
and
C
_{d2}
, which is shared by three phase legs. If the DClink voltage is assumed constant and equals 4E, where E is the voltage across the FC
C_{fa}
, then the voltage across
C
_{d1}
or
C
_{d2}
is 2E. The two series DClink capacitors provide three voltage levels. Combining the function of the FC
C_{fa}
, a fivelevel voltage waveform can be generated at the output point. Six switches are used in one phase of the proposed converter. The voltage stresses of (S
_{1}
, S
_{4}
), (S
_{5}
, S
_{6}
), and (S
_{2}
, S
_{3}
) are 3E, 2E, and E, respectively.
Phase A of the proposed fivelevel hybridclamped converter.
Insulated gate bipolar transistors (IGBTs), which are mostly used in applications in which breakdown voltage should be larger than 600 V, such that the voltage drops change slightly under different voltage levels at the same rated current and technology. As explained in
[5]
, 1200 V IGBTs feature onstate voltages that are roughly 10% larger than that of a 600 V IGBT. Correspondingly, the switching loss energies of a 1200 V IGBT are larger by a factor of 3 to 5. In an appropriate modulation strategy, such as the method proposed in
[19]
, higher voltage cells could operate at lower switching times to reduce switching losses. In situations in which the breakdown voltage is smaller than 300 V, metaloxidesemiconductor fieldeffect transistors (MOSFETs) could be used to reduce conduction losses further.
The numbers of the components in different fivelevel converter topologies are compared in
Table I
. The components include switches, clamping diodes, and FCs. Given that the smaller number of components tends to improve reliability and reduce conduction losses, different voltage ratings of power semiconductors are used to minimize the component numbers in lowvoltage applications, in which suitable voltage level switches are available. As shown in
Table I
, the largest advantage of the proposed circuit is the minimal number of components used. Furthermore, the only two power semiconductors are on the conduction path(illustrated in Part B), which indicates that the voltage drop on the conduction path is relatively low, thereby enabling the proposed converter to be employed in lowvoltage applications. However, the proposed converter has a number of drawbacks. For instance, the voltage of the FCs is not naturally balanced. This drawback limits the operation region of the converter, which will be analyzed in Section III.
COMPARISON OF POWER SEMICONDUCTOR AND FC IN FIVELEVEL CONVERTERS
Note: different voltage ratings of power semiconductor are used to minimize the component numbers
 B. Operation Principle
The conduction paths in different voltage levels of Phase A are shown in
Fig. 2
, where
i_{a}
is the output current,
i_{Cfa}
is the current flowing into the FC
C_{f a}
, and
i_{ma}
is the current flowing out of the middle point M. Only two switches are on the conduction path, regardless of the output voltage. For instance, if the output voltage is 0, switches S
_{3}
and S
_{4}
are on the conduction path. In the proposed converter, all available paths are maximally utilized. Five conduction paths correspond to five different voltage levels. However, no redundant conduction paths can be chosen to keep the FC voltage balanced in a switching period.
Conduction paths of the fivelevel hybridclamped converter. (a) u_{a}=4E, Path.A; (b) u_{a}=3E, Path.B; (c) u_{a}=2E, Path.C; (d) u_{a}=E, Path.D; (e) u_{a}=0, Path.E.
In different conduction paths, the adopted switching states are listed in
Table II
, where state condition 1 and 0 indicate ON and OFF switch status, respectively. As shown in this table, a conduction path corresponds to a set of switching states apart from Path.C. Two sets of switching state in Path.C are designed to avoid the phenomenon in which the output voltage is clamped to unwanted levels during deadtime periods
[6]
,
[21]
when 2E voltage level is necessary. For example, assuming that the switching state V2.A is chosen when the output voltage changes between E and 2E, the output voltage will be clamped at 0 if the output current is positive during the deadtime period. The clamped voltage level of 0 should be avoided. Thus, the switching state of V2.A should be used to generate an output voltage larger than 2E. By contrast, V2.B is chosen to configure a voltage smaller than 2E.
SWITCHING STATES OF THE PROPOSED FIVELEVEL HYBRIDCLAMPED CONVERTER IN PHASE A
SWITCHING STATES OF THE PROPOSED FIVELEVEL HYBRIDCLAMPED CONVERTER IN PHASE A
This study adopts the phasedisposition (PD) PWM
[28]
,
[29]
technique to control the proposed converter to output the expected voltage. PDPWM is a simple method by which to relate each carrier with the gating signal of switches
[1]
. This technique generates relatively low total harmonic distortion
[15]
. PDPWM is based on the comparison of a sinusoidal reference with four symmetrical carriers in a fivelevel converter.
Fig.3
illustrates the sinusoidal PDPWM waveforms of Phase A. Each phase contains three complimentary switch pairs, namely, ( S
_{2}
,
), ( S
_{1}
,
), and ( S
_{6}
,
). For the two switches in a complementary pair, the switching states are converse. For example, if S
_{2}
is in ON status, S
_{3}
should remain in OFF status. As shown in
Fig. 3
, only a pair of complementary switches acts in each switching cycle. With high modulation index
m
and under low voltage stress, S
_{2}
and S
_{3}
switch more times within one fundamental period, which contributes to the reduction of the switching losses.
Sinusoidal PDPWM waveforms of the proposed fivelevel hybridclamped converter. (a) Carrier waveforms. (b) Phase voltage. (c)(e) gating signals.
III. VOLTAGEDRIFT PHENOMENON IN SPWM MODULATION
In the proposed hybrid converter with single DC source, the most critical issue is the voltage balancing problem of the clamping capacitors, including DClink capacitors and FCs. The current flowing into the clamping capacitor implies the tendency of the voltage variation. Thus, the average current could be used to illustrate the voltagedrift phenomenon in the clamping capacitors. In this section, the relationships between the average current of the clamping capacitors and the proposed converter operating index, that is, modulation index and power factor, are deduced. An analysis is conducted in sinusoidal PDPWM, as shown in
Fig. 3
.
Assuming that the output phase voltage and current are sinusoidal, we can reasonably assume that the threephase system is symmetrical. Thus, one phase, for Phase A, could be used to analyze the voltagedrift phenomenon of the proposed converter. The voltage (1) and current (2) of Phase A can be expressed as follows:
where
θ
is the phase voltage angle,
I_{m}
is the amplitude of the phase current,
φ
is the power factor angle, and
m
is the modulation index. In SPWM, the value of
m
is between 1 and 0 to output sinusoidal voltages.
In Phase A of the converter, the output current
i_{a}
flows out of the middle point M when a 2E voltage level is used to compose the wanted output voltage in PWM forms, as shown in
Table II
. For the FC
C_{fa}
,
i_{a}
flows out of
C_{fa}
when a 3E voltage level is selected. Thus, if
i_{a}
is positive,
C_{fa}
will be charged. By contrast,
i_{a}
flows into
C_{fa}
when E is used. In this situation,
C_{fa}
will be discharged when
i_{a}
is positive. According to the charging states of the clamping capacitors, one fundamental period of the phase voltage is divided into six regions, as shown in Fig.. To simplify the analysis, the assumption is made that the carrier frequency is significantly higher than fundamental frequency, such that the phase voltage and current can be considered as a constant in a carrier period.
In Region.1, as shown in
Fig. 4
, the phase voltage angle
θ
covers from zero to
θ_{0}
when
m
>0.5, where
θ_{0}
is defined as:
Diagram of the six regions in one fundamental period of the phase voltage.
In this region, the instantaneous phase voltage changes between 2E and 3E to make the average voltage equal to
u_{a}
in a carrier period. According to the voltagesecondbalance principle, the duty ratio of the higher voltage 3E in the carrier period can be deduced:
In the duty ratio time, the phase current
i_{a}
flows into the FC. In other times, the phase current flows out of the middle point
m
. Thus, the average current flowing into FC in Region.1 is derived as:
Integrating the current
, the accumulated charge on the FC in Region.1 is acquired as:
The average current flowing out of the middle point in Region.1 is derived as:
The output charge from the DClink capacitor is calculated as:
Based on similar calculations, the accumulated charge on the FC and the output charge from the middle point
m
in Region.2 to Region.6 are deduced as follows:
Based on (6) and (8)(18), when
m
>0.5, the average currents that flow into the FC or out of the middle point are respectively deduced as:
Given that the average current
in a fundamental period remains at zero, the conclusion could be drawn that the voltages across the DClink capacitors are naturally balanced under the SPWM method. However, the average current of the FC
is a function of the modulation index and power factor. When the converter transforms nonzero real power, that is, cos
φ
≠0 , the current
is not zero, according to (19). This condition results in the deviations in the FC voltage.
Unlike the 5LANPC and 5LFC converters, the proposed fivelevel converter has no redundant conduction paths to balance the FC voltage. To suppress the voltagedrift phenomenon, one direct method is to add auxiliary circuits for importing or exporting expected charges in FCs. Correspondingly, another method that injects commonmode voltage into the sinusoidal reference voltage is preferred without the addition of auxiliary circuits. To avoid the influence on the linear voltage of the threephase fivelevel converter, the injected common voltages are composed of third harmonic and its multiharmonics. Based on space vector theory, an excellent and flexible commonvoltage injection method called space vector modulation (SVM) is developed. In the SVMswitching strategy, redundant switches can be used to prevent voltage drifts of DClink and FCs in the same space vector of a linear voltage. In the next section, a balancing strategy based on a fivelevel SVM approach is proposed and analyzed.
IV. OPTIMIZED SVM FOR VOLTAGE BALANCE
 A. Space Vector Diagram
The fivelevel threephase inverter has 125(5
^{3}
) switching states. By applying Park’s transformation, 61 space voltage vectors comprise these switching states. These vectors form 96 triangles distributed in six sectors on the
αβ
coordinate, as shown in
Fig. 5
. The switching states are illustrated by 0, 1, 2, 3, and 4, which indicate the phase voltage of 0, E, 2E, 3E, and 4E, respectively. For the fivelevel SVM algorithm, the reference voltage vector
(
u_{α}
,
u_{β}
) must be located within a triangle formed by the three switching vectors adjacent to
. The three adjacent switching vectors constitute the best choice in synthesizing the reference voltage vector
[30]
. Similar to the shadowed triangle in
Fig. 5
, the reference voltage
could be composed by vectors
,
, and
in a carrier period:
where
T
_{1}
,
T
_{2}
, and
T
_{3}
are the duty cycle of the switching vectors
,
, and
, respectively.
Space voltage vectors and switching states of a threephase fivelevel converter.
To reduce the switching losses, the fivesegment method is used
[31]
,
[32]
to synthesize the reference voltage vector
. For instance, the vector
in
Fig. 5
can be constituted by three vector sequences as shown in
Fig. 6
. With the fivesegment method, one of the three phase voltages will stay still within a carrier period, and only four switching commutations are necessary, a reduction of onethird in comparison with the sevensegment method in
[21]
. Based on the number of switching states on each voltage vector, which are labeled on the top of the switching vectors, the 96 triangles can be divided into seven categories, as shown in
Fig. 7
. In different categories, the numbers of optional vector sequences based on the fivesegment method are listed in
Table III
. Apart from the advantage of reducing the typical onethird switching losses, the fivesegment method also has more optional vector sequences to balance the voltage of DClink and FCs, compared with the sevensegment method in
[21]
.
Three vector sequences constitute the voltage vector in Fig. 5.
Diagram of the triangles in seven categories of a threephase fivelevel converter.
NUMBER OF VECTOR SEQUENCES IN SEVEN CATEGORY TRIANGLES
NUMBER OF VECTOR SEQUENCES IN SEVEN CATEGORY TRIANGLES
 B. VoltageDrift Suppression
As the vector sequences in each triangle are not unique, this part shows how to select a proper vector sequence to suppress the voltagedrift phenomenon. Similar to
[15]
and
[33]
, the positivedefinite cost function based on the voltage deviations of DClink and FCs is defined as:
In the proposed fivelevel converter, assuming that the FCs of each phase and the series DClink capacitors are equal, respectively, i.e.,
C _{fa}
=
C _{fb}
=
C _{fc}
=
C _{f}
and
C
_{d1}
=
C
_{d2}
=
C_{d}
, Equation (23) is simplified as:
where Δ
u_{Cfx}
=
u_{Cfx}
 E and Δ
u_{Cdi}
=
u_{Cdi}
 2E are voltage deviations from their nominal voltage. If the DClink and the FC are kept at their nominal values, the cost function
J
can be minimized to zero. The mathematical condition to minimize
J
is
[15]
:
where
i_{Cfx}
is the current through the FC
C _{fx}
and
i_{Cdi}
is the current through the DClink capacitor
C_{di}
. Assuming that the DC bus voltage is clamped at 4E by DC source, thus:
Further, the relationship between
i
_{Cd1}
and
i
_{Cd2}
is:
Based on Equations (26) and (27), Equation (25) is simplified as:
Assuming that the capacitor voltages and phase currents can remain constant during one carrier period
T_{s}
, the average value of operator (28) over one
T_{s}
is deduced as:
In practice,
and
are acquired through the duty cycle and their relationship with phase current in a specific output voltage, as shown in
Table II
. In the case shown in
Fig. 6
(a),
= 0 ,
=
i_{b}
·
T
_{1}
/
T_{s}
,
= 
i_{c}
· (
T
_{1}
+
T
_{3}
)/
T_{s}
, and
=
i_{b}
· (
T
_{2}
+
T
_{3}
)/
T_{s}
. As shown in
Table III
, more than one vector sequences could be used to constitute a voltage vector. The vector sequences that minimize the function of Equation (29) would be the best vector sequences.
V. SIMULATION RESULTS
A simulation platform is developed to evaluate the performance of the fivelevel converter under the proposed modulation strategy. In the proposed strategy, SVM is used to inject commonmode voltages to the reference voltage to suppress the voltagedrift phenomenon. The PDPWM technique is then employed to control the proposed converter to output the expected voltages, which contain the reference voltages and the injected commonmode voltages. In the simulation platform, the SFunction model is used to realize the control system in discrete time domain. The DC side of the converter is supplied by a constant DC source. By contrast, the AC side of the converter is connected to a threephase symmetrical RL load. The system parameters are given in
Table IV
.
PARAMETERS OF THE CONVERTER IN SIMULATION
PARAMETERS OF THE CONVERTER IN SIMULATION
 A. Limits of Operation
Similar to 5LNPC, the strategy, which minimizes the differential of the cost function (dJ/dt) to mitigate the voltagedrift phenomenon, cannot guarantee the capacitor voltage under all possible operating conditions without auxiliary circuits.
Fig. 8
shows the boundary under which the proposed modulation strategy can control and achieve balanced capacitor voltages. By injecting a common voltage, the modulation index
m
could expand to 1.15, as shown in
Fig. 8
. This condition is an advantage of SVM for improved DCvoltage utilization. The solid line shows the boundary of the proposed converter. The boundary is depicted by simulation results at various modulation indices and load power factor values.
Limits of the voltage balance for the proposed converter with proposed modulation strategy. A – Operating point corresponding to Figs. 10 and 14. B – Operating point corresponding to Figs. 11 and 15.
 B. Voltage Ripples of DCLink and FCs
In specific operation conditions, the voltage ripples of DClink and FCs are depicted in
Fig. 9
. As shown in
Fig. 9
(a), the voltage ripples are changed as the modulation index varies. The DClink capacitor voltage ripple is smaller than the FC voltage ripple under the same conditions. When PF=1 and
m
>0.6, the voltage ripples are not described, as the voltagedrift phenomenon cannot be suppressed. If PF=0, the voltage ripples become larger when
m
>0.6. As shown in
Fig. 9
(a), DuCfx is larger than 100 V when PF=0 and
m
=1. If the maximum capacitor ripple was specified to 7.5% of the DClink voltage
[34]
, a larger capacitor is necessary to reduce the voltage ripples in the operation conditions. In addition, a higher output frequency is helpful to decrease the voltage ripples, as shown in
Fig. 9
(b). If the output frequency is 250 Hz, Δ
u_{Cfx}
is about 24 V when switching frequency is maintained at 10 kHz. Combined with the performance of the proposed converter, as shown in
Figs. 8
and
9
, the converter is suitable for handling high frequency reactive power. This finding is consistent with applications of the active power filter, which mainly deals with the fifth and seventh reactive harmonics.
Voltage ripples of flying and DClink capacitors when i_{o}=50 A: (a) modulation index varies when f_{o}=50 Hz; (b) output frequency varies when m=1 and PF=1
 C. Simulation Results in Different RL load
Fig. 10
shows the simulation waveforms of the proposed converter at a power factor of PF=0.16 and a modulation index of
m
=1.
Figs. 10
(a) to (d) shows the line voltage
u_{ab}
, phasea current
i_{a}
, DClink capacitor voltages, and FC voltages, respectively.
Simulation results when m=1 and PF=0.16 (L=26.7mH, R=1.36Ω): (a) line voltage u_{ab}, (b) phase current i_{a}, (c) DClinkcapacitor voltages u_{Cd1} and u_{Cd2}, (d) FC voltages u_{Cfa}, u_{Cfb} , and u_{Cfc}.
In this condition, the voltages of DClink and FCs remain stable at their nominal values.
Fig. 11
shows that the DClink and FCs voltages remain balanced at PF=1 and
m
=0.6. The waveforms in
Figs. 10
and
11
are consistent with the conclusion in
Fig. 8
. For high modulation index
m
, the line voltage has nine distinct levels. Correspondingly, in a lower modulation index, the line voltage has smaller distinct levels, i.e.,
m
=0.6 has seven distinct levels. Compared with
Figs. 10
and
11
, the voltages of DClink and FCs have smaller ripples when
m
=0.6, as the SVM strategy has more optional vector sequences to suppress the voltage deviation.
Simulation results when m=0.6 and PF≈1 (L=100μH, R=5.09Ω): (a) line voltage u_{ab}, (b) Phase A current i_{a}, (c) DClinkcapacitor voltages u_{Cd1} and u_{Cd2}, (d) flying capacitor voltages u_{Cfa}, u_{Cfb}, and u_{Cfc}.
VI. EXPERIMENTAL RESULTS
A low power threephase fivelevel converter has been constructed to verify the validity of the proposed converter and modulation strategy. The prototype of the experimental platform is shown in
Fig. 12
. Each phase board contains a 1000 μF FC, six IGBTs and their relative gate drivers, a FC voltage sampling circuit, and a phase current sampling circuit. The DCbus board includes two 1000 μF series capacitors, two DCcapacitor voltage sampling circuits, and a precharge circuit composed of precharge resistors and a bypass contactor. The controller is based on a DSP TMS320F28335 and a FPGA EP3C25Q240C8. In this section, the DClink voltage is approximately 100 V supplied by a DC source, and the switching frequency is 10 kHz.
Prototype of the proposed threephase fivelevel hybridclamped converter.
 A. Precharge Process
A special precharge method has been developed to precharge the FCs without additional equipment. As shown in
Fig. 13
, the proposed precharge process can be divided into three steps:

(1) S1 and S2 (seeFigure 1) of each phase leg are turned on at 0.2 second. Thus, these FCs are parallel to and charged together with the DClink capacitor through precharge resistors. If the FC voltage of each phase is equal to its nominal value of 25 V, the relative S1 and S2 are turned off. In the process, the charging time is affected by total capacitors and precharge resistors.

(2) The DClink capacitors continue to be charged through precharge resistors until the sum of two DCcapacitor voltages is close to the DC source voltage, i.e., 90 V. In this period, the charging process is much faster as the smaller remaining capacitors.

(3) At 1.62 seconds, the bypass contactor is turned on. Two DClink capacitors are quickly charged to their nominal value of 50 V.
Waveforms of DClink and FC voltages during the precharge process.
 B. Experimental Results in Different RL load
Fig. 14
shows the experimental waveforms of the proposed converter at a power factor of PF=0.16 and a modulation index of
m
=1. As shown in
Fig. 14
, DClink and FC voltages remain stable at their nominal values.
Figure 15
shows that the DClink and FCs voltages remain balanced at PF=1 and
m
=0.6. The experimental results and simulation results are mainly consistent. In
Figs. 14
(a) and
15
(a), some unwanted voltage glitches were caused by the switches between different vector sequences to suppress the voltagedrift phenomenon.
Experimental results when m=1 and PF=0.16 (L=141mH, R=7.18Ω): (a) line voltage u_{ab}, (b) Phase A current i_{a}, (c) DClinkcapacitor voltages u_{Cd1} and u_{Cd2}, (d) FC voltages u_{Cfa}, u_{Cfb}, and u_{Cfc}.
Experimental results when m=0.6 and PF≈1 (L=2mH，R=25Ω): (a) line voltage u_{ab}, (b) phasea current i_{a}, (c) DClinkcapacitor voltages u_{Cd1} and u_{Cd2}, (d) FC voltages u_{Cfa}, u_{Cfb}, and u_{Cfc}.
VII. CONCLUSIONS
A novel fivelevel threephase hybridclamped converter is introduced in this paper. The converter is composed of only six switches and one FC per phase. The main advantage of the converter is that it consists less components compared with other fivelevel converters, as shown in
Table I
. The proposed converter helps to improve reliability, reduce costs and conduction losses, and is attractive for lowvoltage applications. However, the converter cannot keep the voltage of DClink and FCs balanced under SPWM. Thus, a specific modulation strategy based SVM is developed to balance the voltage by injecting a commonmode voltage. Simulation and experimental results conclude that the introduced modulation strategy is capable of balancing the voltages of DClink and FCs within specified operating ranges. Based on the aforementioned analysis, the proposed converter is suitable for handling high frequency reactive power, such as the active power filter. This study further presents a startup method that charges DClink and FCs without any additional circuits. Experimental results confirm the feasibility of the precharge method.
Acknowledgements
This research is sponsored by Zhejiang Key Science and Technology Innovation Group Program (2010R50021), and National Natural Science Foundation of China under grant (51177148).
BIO
Bin Chen was born in Quzhou, Zhejiang Province, China, in 1988. He received his B.S. degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2010, where he is currently working toward a Ph.D. degree in Electrical Engineering. His present research interests are in the areas of speedsensorless induction motor drives, multilevel converters, and digitalsignalprocessorbased realtime control.
Wenxi Yao was born in Haining, Zhejiang Province, China, in 1977. He received his B.S. and Ph.D. degrees in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2000 and 2006, respectively. He is currently an Associate professor of Electrical Engineering at Zhejiang University. From 2010 to 2011, he was a visiting scholar at FREEDM, North Carolina State University. His research interests include digital control in power electrics and sensorless control of AC motor drives. He has authored and coauthored more than 50 published technical papers.
Zhengyu Lu received his B.S. degree in industrial automatic control from Ohai University, China, in 1982 and Ph.D. degree in power electronics from Zhejiang University, China, in 1987. From 1996 to 1998, he was a visiting scholar and worked as a researcher at the University of Birmingham and Imperial College, UK. He is currently a professor at Zhejiang University and is the director of China National Power Electronics Laboratory. Since 1982, he has been teaching and conducting research on power electronic devices and power converters at Zhejiang University, China. His main research interests include power converter, electrical track, vehicle electronics, electronics in FACTS application, and power electronics system integration.
Kouro S.
,
Malinowski M.
,
Gopakumar K.
,
Pou J.
,
Franquelo L.G.
,
Wu B.
,
Rodriguez J.
,
Perez M. A.
,
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