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Novel Five-Level Three-Phase Hybrid-Clamped Converter with Reduced Components
Novel Five-Level Three-Phase Hybrid-Clamped Converter with Reduced Components
Journal of Power Electronics. 2014. Nov, 14(6): 1119-1129
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : June 09, 2013
  • Accepted : October 02, 2014
  • Published : November 20, 2014
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About the Authors
Bin Chen
Department of Electrical Engineering, Zhejiang University, Hangzhou, China
Wenxi Yao
Department of Electrical Engineering, Zhejiang University, Hangzhou, China
ywxi@zju.edu.cn
Zhengyu Lu
Department of Electrical Engineering, Zhejiang University, Hangzhou, China

Abstract
This study proposes a novel five-level three-phase hybrid-clamped converter composed of only six switches and one flying capacitor (FC) per phase. The capacitor-voltage-drift phenomenon of the converter under the classical sinusoidal pulse width modulation (SPWM) strategy is comprehensively analyzed. The average current, which flows into the FC, is a function of power factor and modulation index and does not remain at zero. Thus, a specific modulation strategy based on space vector modulation (SVM) is developed to balance the voltage of DC-link and FCs by injecting a common-mode voltage. This strategy applies the five-segment method to synthesize the voltage vector, such that switching losses are reduced while optional vector sequences are increased. The best vector sequence is then selected on the basis of the minimized cost function to suppress the divergence of the capacitor voltage. This study further proposes a startup method that charges the DC-link and FCs without any additional circuits. Simulation and experimental results verify the validity of the proposed converter, modulation strategy, and precharge method.
Keywords
I. INTRODUCTION
Multilevel converters have attracted considerable attention from both the industry and the academia for their use in high-power applications, such as high-voltage direct-current (HVDC) transmission, reactive power compensation, and medium-voltage industrial drives [1] . In this voltage range, multilevel converters are preferred to overcome the voltage blocking limitations of the available semiconductor switches [2] , [3] . Multilevel converters used in low voltage have recently become a focus [4] - [7] , given that such technology can produce more levels than the conventional two-level converters in the output voltage waveforms, thus resulting in a superior harmonic spectrum and lower switching losses [8] . However, in multilevel converters, the increasing number of components containing switches, clamping diodes, and capacitors tends to increase the conduction losses and reduce the overall reliability [9] . Thus, to design a multilevel converter with reduced components remains an attractive but challenging task.
The basic concept of a multilevel converter is to synthesize a desired AC voltage through several voltage levels, which are produced by separate DC sources or large capacitors with voltage balance control. Among numerous multilevel converter topologies that have been proposed over the past decades, three classic or traditional topologies exist. These topologies are the neutral point clamped (NPC) [10] , [11] , the flying capacitors (FCs) [12] , and the cascade H-bridge (CHB) [13] . In CHB converters, several isolated DC sources are necessary to produce active power. The DC sources are mainly generated by isolation transformers, which are bulky and expensive [1] . Thus, the NPC and FC with a single DC source is preferred. In NPC, different voltage levels are provided by series DC-link capacitors. However, the NPC converter providing more than three levels requires numerous clamping diodes and encounters a voltage-drift phenomenon in some operating regions [14] - [16] . Correspondingly, the operating regions are enlarged in FC converters, in which different voltage levels are clamped by FCs in each phase. However, massive FCs are required as voltage level increases, thus increasing the cost and control complexity [17] .
According to the aforementioned drawbacks of NPC and FC, low-level converters are commercially used in industrial applications, such as the 3L-NPC and 4L-FC [18] . To improve the voltage levels with one DC source, hybrid multilevel converters are developed [19] . In hybrid multilevel converters, more voltage levels can be generated with the same number of components by adopting different intermediate-circuit capacitor voltages [9] . The NPC-HB multilevel converter, which is composed of a series connection of a main three-level NPC converter and an auxiliary floating H-bridge, has been studied in [3] , [9] , and [20] . Given the different capacitor voltages of the H-bridge, the NPC-HB converter can be a five-, seven-, or nine-level converter, which is flexible and attractive. However, eight switches are used in each phase of the NPC-HB, and four series switches should pass through the conduction path. The conduction voltage drop is relatively large if the converter is adopted in low-voltage applications. A five-level active neutral-point clamped (ANPC) converter is another attractive hybrid converter [21] - [23] that can be considered as the combination of a three-level ANPC converter and a two-level cell. Eight switches are necessary for one phase of ANPC if different blocking-voltage switches are adopted. In this case, three switches, fewer than that in NPC-HB, are on the conduction path.
Based on the principles of reducing components and conduction losses, a novel five-level hybrid converter is proposed in this study. Each phase of the proposed converter contains only six switches, and the switches on the conduction path are reduced to two. The hybrid converter is a combination of an FC cell and a three-level transistor-clamped converter (TCC), which has high efficiency in low-voltage applications [6] .
This paper is organized as follows: Section II introduces the topology and operating principles of the proposed converter. Section III presents an analysis of the voltage-drift phenomenon of the converter based on SPWM. Section IV discusses a modulation strategy based on space vector theory to balance the voltage of DC-link and FCs. Section V evaluates the performance of the introduced converter under the proposed modulation strategy in various operating conditions on the basis of simulation studies. Section VI presents the implementation of the method to precharge capacitors before the converter startup without additional circuits. In addition, the feasibility of the converter and modulation strategy is verified through an experiment.
II. CONVERTER TOPOLOGY
- A. Proposed Five-Level Hybrid-Clamped Converter
Fig. 1 shows the topology of Phase A. The hybrid converter combines the 3L-TCC and FC cell into one circuit. In the converter, S 5 and S 6 are combined into a bidirectional switch. Another type of the bidirectional switch could also be selected, as discussed in [24] . As shown in Fig. 1 , the DC bus is composed of two series capacitors, C d1 and C d2 , which is shared by three phase legs. If the DC-link voltage is assumed constant and equals 4E, where E is the voltage across the FC Cfa , then the voltage across C d1 or C d2 is 2E. The two series DC-link capacitors provide three voltage levels. Combining the function of the FC Cfa , a five-level voltage waveform can be generated at the output point. Six switches are used in one phase of the proposed converter. The voltage stresses of (S 1 , S 4 ), (S 5 , S 6 ), and (S 2 , S 3 ) are 3E, 2E, and E, respectively.
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Phase A of the proposed five-level hybrid-clamped converter.
Insulated gate bipolar transistors (IGBTs), which are mostly used in applications in which breakdown voltage should be larger than 600 V, such that the voltage drops change slightly under different voltage levels at the same rated current and technology. As explained in [5] , 1200 V IGBTs feature on-state voltages that are roughly 10% larger than that of a 600 V IGBT. Correspondingly, the switching loss energies of a 1200 V IGBT are larger by a factor of 3 to 5. In an appropriate modulation strategy, such as the method proposed in [19] , higher voltage cells could operate at lower switching times to reduce switching losses. In situations in which the breakdown voltage is smaller than 300 V, metal-oxide-semiconductor field-effect transistors (MOSFETs) could be used to reduce conduction losses further.
The numbers of the components in different five-level converter topologies are compared in Table I . The components include switches, clamping diodes, and FCs. Given that the smaller number of components tends to improve reliability and reduce conduction losses, different voltage ratings of power semiconductors are used to minimize the component numbers in low-voltage applications, in which suitable voltage level switches are available. As shown in Table I , the largest advantage of the proposed circuit is the minimal number of components used. Furthermore, the only two power semiconductors are on the conduction path(illustrated in Part B), which indicates that the voltage drop on the conduction path is relatively low, thereby enabling the proposed converter to be employed in low-voltage applications. However, the proposed converter has a number of drawbacks. For instance, the voltage of the FCs is not naturally balanced. This drawback limits the operation region of the converter, which will be analyzed in Section III.
COMPARISON OF POWER SEMICONDUCTOR AND FC IN FIVE-LEVEL CONVERTERS
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Note: different voltage ratings of power semiconductor are used to minimize the component numbers
- B. Operation Principle
The conduction paths in different voltage levels of Phase A are shown in Fig. 2 , where ia is the output current, iCfa is the current flowing into the FC Cf a , and ima is the current flowing out of the middle point M. Only two switches are on the conduction path, regardless of the output voltage. For instance, if the output voltage is 0, switches S 3 and S 4 are on the conduction path. In the proposed converter, all available paths are maximally utilized. Five conduction paths correspond to five different voltage levels. However, no redundant conduction paths can be chosen to keep the FC voltage balanced in a switching period.
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Conduction paths of the five-level hybrid-clamped converter. (a) ua=4E, Path.A; (b) ua=3E, Path.B; (c) ua=2E, Path.C; (d) ua=E, Path.D; (e) ua=0, Path.E.
In different conduction paths, the adopted switching states are listed in Table II , where state condition 1 and 0 indicate ON and OFF switch status, respectively. As shown in this table, a conduction path corresponds to a set of switching states apart from Path.C. Two sets of switching state in Path.C are designed to avoid the phenomenon in which the output voltage is clamped to unwanted levels during dead-time periods [6] , [21] when 2E voltage level is necessary. For example, assuming that the switching state V2.A is chosen when the output voltage changes between E and 2E, the output voltage will be clamped at 0 if the output current is positive during the dead-time period. The clamped voltage level of 0 should be avoided. Thus, the switching state of V2.A should be used to generate an output voltage larger than 2E. By contrast, V2.B is chosen to configure a voltage smaller than 2E.
SWITCHING STATES OF THE PROPOSED FIVE-LEVEL HYBRID-CLAMPED CONVERTER IN PHASE A
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SWITCHING STATES OF THE PROPOSED FIVE-LEVEL HYBRID-CLAMPED CONVERTER IN PHASE A
This study adopts the phase-disposition (PD) PWM [28] , [29] technique to control the proposed converter to output the expected voltage. PD-PWM is a simple method by which to relate each carrier with the gating signal of switches [1] . This technique generates relatively low total harmonic distortion [15] . PD-PWM is based on the comparison of a sinusoidal reference with four symmetrical carriers in a five-level converter. Fig.3 illustrates the sinusoidal PD-PWM waveforms of Phase A. Each phase contains three complimentary switch pairs, namely, ( S 2 ,
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), ( S 1 ,
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), and ( S 6 ,
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). For the two switches in a complementary pair, the switching states are converse. For example, if S 2 is in ON status, S 3 should remain in OFF status. As shown in Fig. 3 , only a pair of complementary switches acts in each switching cycle. With high modulation index m and under low voltage stress, S 2 and S 3 switch more times within one fundamental period, which contributes to the reduction of the switching losses.
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Sinusoidal PD-PWM waveforms of the proposed five-level hybrid-clamped converter. (a) Carrier waveforms. (b) Phase voltage. (c)-(e) gating signals.
III. VOLTAGE-DRIFT PHENOMENON IN SPWM MODULATION
In the proposed hybrid converter with single DC source, the most critical issue is the voltage balancing problem of the clamping capacitors, including DC-link capacitors and FCs. The current flowing into the clamping capacitor implies the tendency of the voltage variation. Thus, the average current could be used to illustrate the voltage-drift phenomenon in the clamping capacitors. In this section, the relationships between the average current of the clamping capacitors and the proposed converter operating index, that is, modulation index and power factor, are deduced. An analysis is conducted in sinusoidal PD-PWM, as shown in Fig. 3 .
Assuming that the output phase voltage and current are sinusoidal, we can reasonably assume that the three-phase system is symmetrical. Thus, one phase, for Phase A, could be used to analyze the voltage-drift phenomenon of the proposed converter. The voltage (1) and current (2) of Phase A can be expressed as follows:
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where θ is the phase voltage angle, Im is the amplitude of the phase current, φ is the power factor angle, and m is the modulation index. In SPWM, the value of m is between 1 and 0 to output sinusoidal voltages.
In Phase A of the converter, the output current ia flows out of the middle point M when a 2E voltage level is used to compose the wanted output voltage in PWM forms, as shown in Table II . For the FC Cfa , ia flows out of Cfa when a 3E voltage level is selected. Thus, if ia is positive, Cfa will be charged. By contrast, ia flows into Cfa when E is used. In this situation, Cfa will be discharged when ia is positive. According to the charging states of the clamping capacitors, one fundamental period of the phase voltage is divided into six regions, as shown in Fig.. To simplify the analysis, the assumption is made that the carrier frequency is significantly higher than fundamental frequency, such that the phase voltage and current can be considered as a constant in a carrier period.
In Region.1, as shown in Fig. 4 , the phase voltage angle θ covers from zero to θ0 when m >0.5, where θ0 is defined as:
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Diagram of the six regions in one fundamental period of the phase voltage.
In this region, the instantaneous phase voltage changes between 2E and 3E to make the average voltage equal to ua in a carrier period. According to the voltage-second-balance principle, the duty ratio of the higher voltage 3E in the carrier period can be deduced:
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In the duty ratio time, the phase current ia flows into the FC. In other times, the phase current flows out of the middle point m . Thus, the average current flowing into FC in Region.1 is derived as:
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Integrating the current
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, the accumulated charge on the FC in Region.1 is acquired as:
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The average current flowing out of the middle point in Region.1 is derived as:
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The output charge from the DC-link capacitor is calculated as:
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Based on similar calculations, the accumulated charge on the FC and the output charge from the middle point m in Region.2 to Region.6 are deduced as follows:
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Based on (6) and (8)-(18), when m >0.5, the average currents that flow into the FC or out of the middle point are respectively deduced as:
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Given that the average current
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in a fundamental period remains at zero, the conclusion could be drawn that the voltages across the DC-link capacitors are naturally balanced under the SPWM method. However, the average current of the FC
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is a function of the modulation index and power factor. When the converter transforms nonzero real power, that is, cos φ ≠0 , the current
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is not zero, according to (19). This condition results in the deviations in the FC voltage.
Unlike the 5L-ANPC and 5L-FC converters, the proposed five-level converter has no redundant conduction paths to balance the FC voltage. To suppress the voltage-drift phenomenon, one direct method is to add auxiliary circuits for importing or exporting expected charges in FCs. Correspondingly, another method that injects common-mode voltage into the sinusoidal reference voltage is preferred without the addition of auxiliary circuits. To avoid the influence on the linear voltage of the three-phase five-level converter, the injected common voltages are composed of third harmonic and its multi-harmonics. Based on space vector theory, an excellent and flexible common-voltage injection method called space vector modulation (SVM) is developed. In the SVM-switching strategy, redundant switches can be used to prevent voltage drifts of DC-link and FCs in the same space vector of a linear voltage. In the next section, a balancing strategy based on a five-level SVM approach is proposed and analyzed.
IV. OPTIMIZED SVM FOR VOLTAGE BALANCE
- A. Space Vector Diagram
The five-level three-phase inverter has 125(5 3 ) switching states. By applying Park’s transformation, 61 space voltage vectors comprise these switching states. These vectors form 96 triangles distributed in six sectors on the αβ coordinate, as shown in Fig. 5 . The switching states are illustrated by 0, 1, 2, 3, and 4, which indicate the phase voltage of 0, E, 2E, 3E, and 4E, respectively. For the five-level SVM algorithm, the reference voltage vector
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( uα , uβ ) must be located within a triangle formed by the three switching vectors adjacent to
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. The three adjacent switching vectors constitute the best choice in synthesizing the reference voltage vector [30] . Similar to the shadowed triangle in Fig. 5 , the reference voltage
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could be composed by vectors
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,
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, and
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in a carrier period:
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where T 1 , T 2 , and T 3 are the duty cycle of the switching vectors
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,
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, and
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, respectively.
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Space voltage vectors and switching states of a three-phase five-level converter.
To reduce the switching losses, the five-segment method is used [31] , [32] to synthesize the reference voltage vector
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. For instance, the vector
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in Fig. 5 can be constituted by three vector sequences as shown in Fig. 6 . With the five-segment method, one of the three phase voltages will stay still within a carrier period, and only four switching commutations are necessary, a reduction of one-third in comparison with the seven-segment method in [21] . Based on the number of switching states on each voltage vector, which are labeled on the top of the switching vectors, the 96 triangles can be divided into seven categories, as shown in Fig. 7 . In different categories, the numbers of optional vector sequences based on the five-segment method are listed in Table III . Apart from the advantage of reducing the typical one-third switching losses, the five-segment method also has more optional vector sequences to balance the voltage of DC-link and FCs, compared with the seven-segment method in [21] .
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Three vector sequences constitute the voltage vector in Fig. 5.
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Diagram of the triangles in seven categories of a three-phase five-level converter.
NUMBER OF VECTOR SEQUENCES IN SEVEN CATEGORY TRIANGLES
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NUMBER OF VECTOR SEQUENCES IN SEVEN CATEGORY TRIANGLES
- B. Voltage-Drift Suppression
As the vector sequences in each triangle are not unique, this part shows how to select a proper vector sequence to suppress the voltage-drift phenomenon. Similar to [15] and [33] , the positive-definite cost function based on the voltage deviations of DC-link and FCs is defined as:
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In the proposed five-level converter, assuming that the FCs of each phase and the series DC-link capacitors are equal, respectively, i.e., C fa = C fb = C fc = C f and C d1 = C d2 = Cd , Equation (23) is simplified as:
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where Δ uCfx = uCfx - E and Δ uCdi = uCdi - 2E are voltage deviations from their nominal voltage. If the DC-link and the FC are kept at their nominal values, the cost function J can be minimized to zero. The mathematical condition to minimize J is [15] :
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where iCfx is the current through the FC C fx and iCdi is the current through the DC-link capacitor Cdi . Assuming that the DC bus voltage is clamped at 4E by DC source, thus:
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Further, the relationship between i Cd1 and i Cd2 is:
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Based on Equations (26) and (27), Equation (25) is simplified as:
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Assuming that the capacitor voltages and phase currents can remain constant during one carrier period Ts , the average value of operator (28) over one Ts is deduced as:
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In practice,
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and
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are acquired through the duty cycle and their relationship with phase current in a specific output voltage, as shown in Table II . In the case shown in Fig. 6 (a),
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= 0 ,
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= ib · T 1 / Ts ,
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= - ic · ( T 1 + T 3 )/ Ts , and
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= ib · ( T 2 + T 3 )/ Ts . As shown in Table III , more than one vector sequences could be used to constitute a voltage vector. The vector sequences that minimize the function of Equation (29) would be the best vector sequences.
V. SIMULATION RESULTS
A simulation platform is developed to evaluate the performance of the five-level converter under the proposed modulation strategy. In the proposed strategy, SVM is used to inject common-mode voltages to the reference voltage to suppress the voltage-drift phenomenon. The PD-PWM technique is then employed to control the proposed converter to output the expected voltages, which contain the reference voltages and the injected common-mode voltages. In the simulation platform, the S-Function model is used to realize the control system in discrete time domain. The DC side of the converter is supplied by a constant DC source. By contrast, the AC side of the converter is connected to a three-phase symmetrical RL load. The system parameters are given in Table IV .
PARAMETERS OF THE CONVERTER IN SIMULATION
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PARAMETERS OF THE CONVERTER IN SIMULATION
- A. Limits of Operation
Similar to 5L-NPC, the strategy, which minimizes the differential of the cost function (dJ/dt) to mitigate the voltage-drift phenomenon, cannot guarantee the capacitor voltage under all possible operating conditions without auxiliary circuits. Fig. 8 shows the boundary under which the proposed modulation strategy can control and achieve balanced capacitor voltages. By injecting a common voltage, the modulation index m could expand to 1.15, as shown in Fig. 8 . This condition is an advantage of SVM for improved DC-voltage utilization. The solid line shows the boundary of the proposed converter. The boundary is depicted by simulation results at various modulation indices and load power factor values.
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Limits of the voltage balance for the proposed converter with proposed modulation strategy. A – Operating point corresponding to Figs. 10 and 14. B – Operating point corresponding to Figs. 11 and 15.
- B. Voltage Ripples of DC-Link and FCs
In specific operation conditions, the voltage ripples of DC-link and FCs are depicted in Fig. 9 . As shown in Fig. 9 (a), the voltage ripples are changed as the modulation index varies. The DC-link capacitor voltage ripple is smaller than the FC voltage ripple under the same conditions. When PF=1 and m >0.6, the voltage ripples are not described, as the voltage-drift phenomenon cannot be suppressed. If PF=0, the voltage ripples become larger when m >0.6. As shown in Fig. 9 (a), DuCfx is larger than 100 V when PF=0 and m =1. If the maximum capacitor ripple was specified to 7.5% of the DC-link voltage [34] , a larger capacitor is necessary to reduce the voltage ripples in the operation conditions. In addition, a higher output frequency is helpful to decrease the voltage ripples, as shown in Fig. 9 (b). If the output frequency is 250 Hz, Δ uCfx is about 24 V when switching frequency is maintained at 10 kHz. Combined with the performance of the proposed converter, as shown in Figs. 8 and 9 , the converter is suitable for handling high frequency reactive power. This finding is consistent with applications of the active power filter, which mainly deals with the fifth and seventh reactive harmonics.
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Voltage ripples of flying and DC-link capacitors when io=50 A: (a) modulation index varies when fo=50 Hz; (b) output frequency varies when m=1 and PF=1
- C. Simulation Results in Different RL load
Fig. 10 shows the simulation waveforms of the proposed converter at a power factor of PF=0.16 and a modulation index of m =1. Figs. 10 (a) to (d) shows the line voltage uab , phase-a current ia , DC-link capacitor voltages, and FC voltages, respectively.
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Simulation results when m=1 and PF=0.16 (L=26.7mH, R=1.36Ω): (a) line voltage uab, (b) phase current ia, (c) DC-link-capacitor voltages uCd1 and uCd2, (d) FC voltages uCfa, uCfb , and uCfc.
In this condition, the voltages of DC-link and FCs remain stable at their nominal values. Fig. 11 shows that the DC-link and FCs voltages remain balanced at PF=1 and m =0.6. The waveforms in Figs. 10 and 11 are consistent with the conclusion in Fig. 8 . For high modulation index m , the line voltage has nine distinct levels. Correspondingly, in a lower modulation index, the line voltage has smaller distinct levels, i.e., m =0.6 has seven distinct levels. Compared with Figs. 10 and 11 , the voltages of DC-link and FCs have smaller ripples when m =0.6, as the SVM strategy has more optional vector sequences to suppress the voltage deviation.
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Simulation results when m=0.6 and PF≈1 (L=100μH, R=5.09Ω): (a) line voltage uab, (b) Phase A current ia, (c) DC-link-capacitor voltages uCd1 and uCd2, (d) flying capacitor voltages uCfa, uCfb, and uCfc.
VI. EXPERIMENTAL RESULTS
A low power three-phase five-level converter has been constructed to verify the validity of the proposed converter and modulation strategy. The prototype of the experimental platform is shown in Fig. 12 . Each phase board contains a 1000 μF FC, six IGBTs and their relative gate drivers, a FC voltage sampling circuit, and a phase current sampling circuit. The DC-bus board includes two 1000 μF series capacitors, two DC-capacitor voltage sampling circuits, and a precharge circuit composed of precharge resistors and a bypass contactor. The controller is based on a DSP TMS320F28335 and a FPGA EP3C25Q240C8. In this section, the DC-link voltage is approximately 100 V supplied by a DC source, and the switching frequency is 10 kHz.
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Prototype of the proposed three-phase five-level hybrid-clamped converter.
- A. Precharge Process
A special precharge method has been developed to precharge the FCs without additional equipment. As shown in Fig. 13 , the proposed precharge process can be divided into three steps:
  • (1) S1 and S2 (seeFigure 1) of each phase leg are turned on at 0.2 second. Thus, these FCs are parallel to and charged together with the DC-link capacitor through precharge resistors. If the FC voltage of each phase is equal to its nominal value of 25 V, the relative S1 and S2 are turned off. In the process, the charging time is affected by total capacitors and precharge resistors.
  • (2) The DC-link capacitors continue to be charged through precharge resistors until the sum of two DC-capacitor voltages is close to the DC source voltage, i.e., 90 V. In this period, the charging process is much faster as the smaller remaining capacitors.
  • (3) At 1.62 seconds, the bypass contactor is turned on. Two DC-link capacitors are quickly charged to their nominal value of 50 V.
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Waveforms of DC-link and FC voltages during the precharge process.
- B. Experimental Results in Different RL load
Fig. 14 shows the experimental waveforms of the proposed converter at a power factor of PF=0.16 and a modulation index of m =1. As shown in Fig. 14 , DC-link and FC voltages remain stable at their nominal values. Figure 15 shows that the DC-link and FCs voltages remain balanced at PF=1 and m =0.6. The experimental results and simulation results are mainly consistent. In Figs. 14 (a) and 15 (a), some unwanted voltage glitches were caused by the switches between different vector sequences to suppress the voltage-drift phenomenon.
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Experimental results when m=1 and PF=0.16 (L=141mH, R=7.18Ω): (a) line voltage uab, (b) Phase A current ia, (c) DC-link-capacitor voltages uCd1 and uCd2, (d) FC voltages uCfa, uCfb, and uCfc.
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Experimental results when m=0.6 and PF≈1 (L=2mH,R=25Ω): (a) line voltage uab, (b) phase-a current ia, (c) DC-link-capacitor voltages uCd1 and uCd2, (d) FC voltages uCfa, uCfb, and uCfc.
VII. CONCLUSIONS
A novel five-level three-phase hybrid-clamped converter is introduced in this paper. The converter is composed of only six switches and one FC per phase. The main advantage of the converter is that it consists less components compared with other five-level converters, as shown in Table I . The proposed converter helps to improve reliability, reduce costs and conduction losses, and is attractive for low-voltage applications. However, the converter cannot keep the voltage of DC-link and FCs balanced under SPWM. Thus, a specific modulation strategy based SVM is developed to balance the voltage by injecting a common-mode voltage. Simulation and experimental results conclude that the introduced modulation strategy is capable of balancing the voltages of DC-link and FCs within specified operating ranges. Based on the aforementioned analysis, the proposed converter is suitable for handling high frequency reactive power, such as the active power filter. This study further presents a startup method that charges DC-link and FCs without any additional circuits. Experimental results confirm the feasibility of the precharge method.
Acknowledgements
This research is sponsored by Zhejiang Key Science and Technology Innovation Group Program (2010R50021), and National Natural Science Foundation of China under grant (51177148).
BIO
Bin Chen was born in Quzhou, Zhejiang Province, China, in 1988. He received his B.S. degree in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2010, where he is currently working toward a Ph.D. degree in Electrical Engineering. His present research interests are in the areas of speed-sensorless induction motor drives, multilevel converters, and digital-signal-processor-based real-time control.
Wenxi Yao was born in Haining, Zhejiang Province, China, in 1977. He received his B.S. and Ph.D. degrees in Electrical Engineering from Zhejiang University, Hangzhou, China, in 2000 and 2006, respectively. He is currently an Associate professor of Electrical Engineering at Zhejiang University. From 2010 to 2011, he was a visiting scholar at FREEDM, North Carolina State University. His research interests include digital control in power electrics and sensorless control of AC motor drives. He has authored and coauthored more than 50 published technical papers.
Zhengyu Lu received his B.S. degree in industrial automatic control from Ohai University, China, in 1982 and Ph.D. degree in power electronics from Zhejiang University, China, in 1987. From 1996 to 1998, he was a visiting scholar and worked as a researcher at the University of Birmingham and Imperial College, UK. He is currently a professor at Zhejiang University and is the director of China National Power Electronics Laboratory. Since 1982, he has been teaching and conducting research on power electronic devices and power converters at Zhejiang University, China. His main research interests include power converter, electrical track, vehicle electronics, electronics in FACTS application, and power electronics system integration.
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