Advanced
Optimized Space Vector Pulse-width Modulation Technique for a Five-level Cascaded H-Bridge Inverter
Optimized Space Vector Pulse-width Modulation Technique for a Five-level Cascaded H-Bridge Inverter
Journal of Power Electronics. 2014. Sep, 14(5): 937-945
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : May 15, 2014
  • Accepted : June 20, 2014
  • Published : September 28, 2014
Download
PDF
e-PUB
PubReader
PPT
Export by style
Share
Article
Author
Metrics
Cited by
TagCloud
About the Authors
Amarendra Matsa
Department of Electrical Engineering,Visvesvaraya National Institute of Technology, Nagpur, India
amarmeetsyou@gmail.com
Irfan Ahmed
Department of Electrical Engineering,Visvesvaraya National Institute of Technology, Nagpur, India
Madhuri A. Chaudhari
Department of Electrical Engineering,Visvesvaraya National Institute of Technology, Nagpur, India

Abstract
This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.
Keywords
I. INTRODUCTION
The need for a high-power control apparatus has developed in various industrial applications in recent years. Thus, several multilevel converter structures have been introduced as alternatives to high-power and medium-voltage applications. Multilevel converters not only achieve high-power ratings but also achieve the integration of distributed generation (DG) sources. Multilevel converters have three principal topologies [1] , [2] . Among which, the cascaded H-bridge (CHB) topology is the most suitable for DG sources [3] . Pulse-width modulation (PWM) techniques for multilevel converters have been studied extensively during the last few decades. A wide variety of methods, which are different in concepts and performances, have been developed to achieve one or more of the following objectives:
  • - wide linear modulation range
  • - less switching losses
  • - decreased total harmonic distortion(THD)
  • - easy implementation and less computational time[4],[5].
The space vector pulse with modulation (SVPWM) technique provides superior harmonics capacity and solves the problem of unbalanced capacitor voltages by using redundant states in the space voltage vector plane. Thus, many methods have been developed to implement SVPWM to drive voltage-source inverters [2] - [16] .SVPWM implementation generally involves identifying sectors, determining switching vectors, and selecting optimum switching sequences for inverters [6] , [7] . Blasko provided a classical SVPWM technique with an equal duration of zero-state vector V0 application, whereas V7 was modified. A factor-variable Ko that is proportional to the time of application of vector V7 was introduced. By changing Ko from zero to one, the duration of V7 application can be changed from 0% to 100% of the combined application time for zero-state vectors. A correlation between the modified space-vector and triangle-comparison methods (with added zero sequence) was established [8] . Celanovic introduced a new and computationally efficient space vector modulation (SVM) algorithm for general n-level converters. This algorithm can be implemented on nearly any commercially available digital signal processor and is suited for execution in real time; however, this method is more complex than others [9] . Seo proposed a simplified SVPWM method for a three-level inverter. This method is based on the simplification of the space vector diagram (SVD) of a three-level inverter into that of a two-level inverter [10] . Perales developed a 3D space vector algorithm for a multilevel converter to compensate for the harmonics and zero-sequence components of the system. This algorithm is useful in systems with or without neutrality, unbalanced load, and triple harmonics, as well as for generating 3D control vectors [11] . Ahmed also developed a new simplified SVPWM technique for a seven-level inverter. This technique can reduce the complexity of an SVD [12] .
The schematic structure of a five-level CHB inverter is shown in Fig. 1 (a) and its SVD is shown in Fig. 1 (b).
PPT Slide
Lager Image
(a) Five-level CHB inverter.(b) SVD of a five-level inverter.
This inverter has five possible output voltage levels for each phase. The levels, which range from +2 E (corresponding to P 2 ) to -2 E (corresponding to N 2 ), result in 5 3 = 125 possible space vectors for the inverter. The number of independent space vectors is(3 n 2 -3 n +1) = 61, where n = 5 for the five levels. ( n - 1) = 4 layers and ( n - 1) 3 = 64 triangles are found in the SVD.
This paper proposes an optimized technique for SVPWM (OSVPWM) of a five-level CHB multilevel inverter. This technique considerably reduces calculation time, complexity, and efforts involved in constructing the SVD of a five-level CHB inverter. Based on the geometric simplification of the SVD, the proposed method reduces the number of two–level hexagons that should be considered from 36 to 24 (18 outer + 6 inner) for a five-level inverter. A further OSVPWM (FOSVPWM) technique is also proposed in this paper which further reduces the number of two-level hexagons to 18.The simulation results of both techniques for a five-level CHB inverter are presented and compared with the results of the sinusoidal PWM technique (SPWM) to validate the proposed methods.
II. PROPOSED OSVPWM TECHNIQUE
The basic idea of OSVPWM is based on the concept of resolving a five-level SVD[ Fig. 1 (b)] into inner and outer two-level hexagons. The selectivity of the inner and outer regions depends on the magnitude of Vref . If Vref magnitude is less than 2 E , then the inner region is selected; otherwise, the outer region is selected as shown in Fig. 2 . The hexagons in the outer or inner region are selected based on the angle θ of the original reference voltage. When Vref is more than 2 E , the outer region hexagons are selected. Selecting a particular hexagon in the outer region depends on angle θ as shown in Table I .
PPT Slide
Lager Image
Selection of inner and outer regions.
SELECTION OF OUTER TWO-LEVEL HEXAGONS
PPT Slide
Lager Image
SELECTION OF OUTER TWO-LEVEL HEXAGONS
When an outer hexagon is selected, a new reference vector Vrefo2 is generated, such that it originates from the center of the outer two-level hexagons. The tip of this new vector coincides with the tip of Vref5 . Consider the case of hexagon I(OH1) shown in Fig. 3 . Vector Vrefo2 is related to Vref5 based on the following relations:
PPT Slide
Lager Image
PPT Slide
Lager Image
PPT Slide
Lager Image
Outer two-level hexagon reference point mapping.
where V , V and Vo2α , Vo2β are the components of Vref5 and Vrefo2 along the real and imaginary axes, respectively. The mapping of all Vrefo2 hexagons is described in Table II .
MAPPING OFVREFO2FROMVREF5
PPT Slide
Lager Image
MAPPING OF VREFO2 FROM VREF5
Vector Vrefo2 for each of the outer hexagons has a modulation index ranging from zero to unity and an angle θo2 ranging from zero to 2π. Angle θo2 is also applied to each of the outer hexagons. When the inner two-level hexagons (IH) are selected, reference vector Vref5 is mapped to the inner two-level hexagon center reference vector Vrefi2 as shown in Fig. 4 . The appropriate selection of IH depends on angle θ5 . The process of selecting an appropriate inner two-level hexagon is described in Table III . Consider the case of selecting an inner two-level hexagon1 (IH1) as shown in Fig. 5 . Reference vectors Vrefi2 and Vref5 are related as follows:
PPT Slide
Lager Image
PPT Slide
Lager Image
PPT Slide
Lager Image
Inner two-level hexagon reference point mapping.
PPT Slide
Lager Image
Outer region two-level hexagon OH1.
SELECTION OF INNER TWO-LEVEL HEXAGONS
PPT Slide
Lager Image
SELECTION OF INNER TWO-LEVEL HEXAGONS
where V , V and Vi2α , Vi2β are the components of Vref5 and Vrefi2 along the α and β axes, respectively. The computation Vrefi2 of all six inner two-level hexagons is described in Table 4 .
MAPPING OFVREFI2FROMVREF5
PPT Slide
Lager Image
MAPPING OF VREFI2 FROM VREF5
III. DWELL TIME CALCULATION AND SWITCHING SEQUENCE DESIGN
Dwell time calculation and switching sequence generation for the selected two-level hexagon can be performed in a manner similar to that in the conventional two-level SVPWM technique. Each two-level hexagon is divided into six sectors.
The sector in reference vector Vrefo2 depends on its angle θo2 . Vrefo2 can then be synthesized by the three stationary vectors of that sector. Dwell time calculation for the stationary vectors is performed based on the “volt-second-balancing” principle. The outer region two-level hexagon OH1and reference voltage Vrefo2 lie in Sector I as shown in Fig. 5 .
Vectors V 1 ( P 2 N 2 N 2 ), V 2 ( P 2 N 1 N 2 ) and P 2 N 1 N 1 , P 2 N 2 N 2 are zero voltage vectors V0 . The volt-second-balancing equation for this sector is given as follows:
PPT Slide
Lager Image
where Ts is the sampling interval; and Ta , Tb , and T0 are the respective dwell times for vectors V 1 , V 2 , and V0 .
The values of Ta , Tb , and T0 are given as follows:
PPT Slide
Lager Image
PPT Slide
Lager Image
PPT Slide
Lager Image
where mα is the modulation index defined as follows:
PPT Slide
Lager Image
After calculating dwell time intervals, an appropriate design for the switching sequence is required. The typical seven-segment switching sequence is used in this scheme. The switching sequence should be designed, such that a change from one switching state to the next involves only one leg, and a change from one sector to the next involves zero or a minimum number of switching [1] . With these constraints, the seven-segment switching sequence for vector Vrefo2 Sector I shown in Fig. 5 is given as follows:
( P 1 N 2 N 2 ), ( P 2 N 2 N 2 ),( P 2 N 1 N 2 ), ( P 2 N 1 N 1 ),( P 2 N 1 N 2 ), ( P 2 N 2 N 2 ), ( P 1 N 2 N 2 ).
Similarly, the switching sequence for Sector II is given as follows:
( P 1 N 2 N 2 ), ( P 2 N 2 N 2 ), ( P 2 N 1 N 2 ), ( P 2 N 1 N 1 ), ( P 2 N 1 N 2 ), ( P 2 N 2 N 2 ), ( P 1 N 2 N 2 ).
IV. FOSVPWM
This technique further reduces the number of two-level hexagons that should be considered. Consequently, it decreases the complexity and efforts involved in the SVPWM of a five-level inverter. A five-level SVD for this technique is initially resolved into inner and outer regions, similar to in the OSVPWM technique. Thus, the number of two-level hexagons that should be considered for the FOSVPWM of a five-level inverter is reduced to 18. The modulation index Ma for SVM is defined as the maximum value( Mα = 1) that corresponds to the radius of the largest circle that can be inscribed in the SVD. The five-level SVD with such a circle is shown in Fig. 6 .
PPT Slide
Lager Image
Five-level SVD with an inscribing circle for Mα = 1.
If only 12 OHs are considered (even for Mα = 1), then only the dark shaded portion of the SVD is left unattended. If this area is ignored, then the SVM of a five-level inverter involves only 18 two-level hexagons. Selecting the appropriate two-level hexagon depends on the magnitude and angle of reference vector Vref5 described in Table V .
SELECTION OF THE OUTER TWO-LEVEL HEXAGONS IN THE FOSVPWM TECHNIQUE
PPT Slide
Lager Image
SELECTION OF THE OUTER TWO-LEVEL HEXAGONS IN THE FOSVPWM TECHNIQUE
The decrease in complexity is achieved at the cost of a slightly increased THD of the output voltage. This increase is only for Mα > 0.75, where M α is the modulation index for the five-level SVD. If the tip of vector Vref5 lies in the dark unattended portion, then one of the OHs is selected depending on the angle θ5 of Vref5 . A new reference vector Vrefo2 is then generated, as in the case of the OSVPWM technique, with its origin located at the center of the selected two-level hexagon.
V. SIMULATION RESULTS
The proposed methods are simulated with MATLAB/SIMULINK. The simulation is conducted for a five-level CHB inverter at different values of the modulation index Mα . The results are compared with those of the conventional SPWM technique to validate the viability of the proposed techniques. The simulation parameters are shown in Table VI , and the simulation results are shown in Fig. 7 and 8 for the modulation indices Mα = 1.0 and Mα = 0.8, respectively.
PPT Slide
Lager Image
Output line voltage waveforms at Ma = 1 for SPWM, OSVPWM and FOSVPWM. (b) OSVPWM. (c) FOSVPWM.
PPT Slide
Lager Image
Output line voltage waveforms at Ma = 0.8 for SPWM, OSVPWM and FOSVPWM. (a) SPWM. (b) OSVPWM. (c) FOSVPWM.
SIMULATION PARAMETERS USED FOR FIVE-LEVEL CHB INVERTER
PPT Slide
Lager Image
SIMULATION PARAMETERS USED FOR FIVE-LEVEL CHB INVERTER
The sampling frequency for the SVM schemes is generally preferred as 6 N times the output frequency, where N is an integer. The sampling frequency for the SVM schemes is fs = 1.5 kHz, assuming a value of N = 5. For the SPWM schemes, the sampling frequency should be [(2 N + 1) × 3] times the output frequency [17] , [18]. Thus, fs = 1.65 kHz for these schemes. Table VII shows the THD of the output line voltage and the peak magnitude of the fundamental components at various Mα values.
THD AND PEAK VALUE OF FUNDAMENTAL COMPONENT (V1M) OF OUTPUT LINE VOLTAGE
PPT Slide
Lager Image
THD AND PEAK VALUE OF FUNDAMENTAL COMPONENT (V1M) OF OUTPUT LINE VOLTAGE
These results show that the proposed optimized techniques are comparable with the established SPWM schemes. The proposed techniques exhibit satisfactory performance for all values of the modulation index Mα . The THD obtained with these techniques is slightly higher than that obtained with the SPWM scheme. In addition, the fundamental components of the output voltage obtained with these schemes are higher than those obtained with the SPWM scheme. The proposed schemes also exhibit significant improvement over the SPWM scheme for low values of Ma . In particular, for Mα ≤ 0.2, the FOSVPWM scheme presents remarkable improvement in performance over the SPWM scheme. This condition is advantageous in applications wherein the inverter may sometimes be required to operate at low modulation indices.
Thus, the proposed techniques perform comparably with the previously proposed SVM techniques for multilevel inverters while considerably optimizing the control algorithm.
VI. EXPERIMENT RESULTS
An experimental study was conducted to confirm the proposed control methods. Experimental set up as shown in Fig. 9 , in which two H-bridges are connected in series per phase. An XC3S400 field-programmable gate array (FPGA) from Xilinx, Inc. (California, USA) was used to realize the proposed control schemes. The experimental system parameters are listed in Table VIII .
PPT Slide
Lager Image
Experimental setup of Five- level H-Bridge Inverter.
PPT Slide
Lager Image
Output line voltage waveforms at Ma = 1 for OSVPWM and FOSVPWM.
PPT Slide
Lager Image
Output line voltage waveforms at Ma = 0.8 for OSVPWM and FOSVPWM.
EXPERIMENTAL PARAMETERS USED FOR FIVE-LEVEL CHB INVERTER
PPT Slide
Lager Image
EXPERIMENTAL PARAMETERS USED FOR FIVE-LEVEL CHB INVERTER
VII. CONCLUSIONS
This study presents the OSVPWM technique that optimizes the SVPWM of multilevel inverters. The proposed technique is based on resolving the multilevel inverter SVD into inner and outer region two-level hexagons. This technique is general and can be applied to the SVPWM of all three principal topologies for multilevel converters at any number of levels. The advantage of applying this technique increases as the number of levels increases.
An FOSVPWM technique has also been presented for the SVM of a five-level inverter. This technique reduces the complexity and effort required for the SVPWM of a five-level inverter by nearly 50%. In particular, the OSVPWM technique reduces the five-level SVPWM to a SVPWM problem of 24 two-level hexagons. The FOSVPWM technique further reduces this number to 18.
The simulation results for both techniques are presented for a five-level CHB inverter. The results are compared with those of the SPWM technique, which proves the validity of the proposed techniques for different values of the modulation index. The experiment results are then provided for the proposed methods to verify the correctness of the real-time simulation system. The FPGA-based real-time emulation will be a popular component of real-time simulation. The application of these techniques significantly reduces the complexity and efforts involved in the SVPWM of higher level inverters.
BIO
Amarendra Matsa was born in Andhra Pradesh, India on August 23, 1984. He received his B.Tech and M.Tech degrees from Jawaharlal Nehru Technological University, Hyderabad, India in 2006 and 2009, respectively. He is currently pursuing his Ph.D. at Visvesvaraya National Institute of Technology (VNIT), Nagpur, India. His current research interests include power electronics, new control algorithm techniques for grid-integrated distributed generation, and microgrids.
Irfan Ahmed received his B.E. (Electrical Engineering) from Nagpur University, India, in 2001, and M.Tech (Power Electronics, machines, and drives) from the Indian Institute of Technology, Roorkee, India, in 2004. From 2004 to 2011, he worked as a faculty member at Anjuman College of Engineering and Technology, Nagpur, India. He is currently pursuing his Ph.D. at the Department of Electrical and Electronics Engineering, VNIT, Nagpur, India. His research interests include power electronics and its applications to power systems and drives
Madhuri A. Chaudhari was born in Maharashtra, India on January 28, 1968. She received her B.E. from Amaravati University, Amaravati, India; M.Tech from Visvesvaraya Regional College of Engineering, Nagpur University, Nagpur, India; and Ph.D. from VNIT, Nagpur, India (all in electrical engineering). She is currently an associate professor at the Department of Electrical Engineering, VNIT. Her research interests are in the areas of power electronics, FACTS, and AC–DC drives. Dr. Chaudhari is a member of the IEEE, the Institution of Engineers (India), and the Indian Society for Technical Education.
References
Wu B. 2006 High-Power Converters and AC Drives John Wiley & Sons Chap. 7
Rodriguez J. , Lai J. , Peng F. Z. 2002 “Multilevel inverters: a survey of topologies, controls, and applications,” IEEE Trans. Ind. Electron. 49 (4) 724 - 738    DOI : 10.1109/TIE.2002.801052
Pouresmaeil E. , Gomis-Bellmunt O. , Montesinos-Miracle D. , Bergas-Jane J. 2011 “Multilevel converters control for renewable energy integration to the power grid,” Energy 36 (2) 950 - 963    DOI : 10.1016/j.energy.2010.12.014
Holtz J. 1992 “Pulse-width-modulation–A survey,” IEEE Trans. Ind. Electron. 39 (5) 410 - 419    DOI : 10.1109/41.161472
Bowesand S. R. , Lai Y. S. 1997 “The relations hip between space-vector modulation and regular-sampled PWM,” IEEE Trans. Ind. Electronics 44 (5) 670 - 679    DOI : 10.1109/41.633469
Mondal S. K. , Pinto J. P. , Bose B. K. 2002 “A neural network- based space vector PWM controller for a three level voltage-fed inverter induction motor drive,” IEEE Trans. Ind. Electron. 38 (3) 660 - 669
Renge M. M. , Suryawanshi H. M. 2008 “Five-level diode clamped inverter to eliminate common mode voltage and reduce dv/dt in medium voltage rating induction motor drives,” IEEE Trans. Ind. Electron. 23 (4) 1598 - 1607
Blasko V. 1997 “Analysis of a hybrid PWM based on modifiedspace-vector and triangle-comparison methods,” IEEE Trans.Ind.Appl. 33 (3) 756 - 764    DOI : 10.1109/28.585866
Celanovic N. , Boroyevich D. 2001 “A fast space-vector modulation algorithm for multilevel three-phase converters,” IEEE Trans. Ind. Appl. 37 (2) 637 - 641    DOI : 10.1109/28.913731
Seo J. H. , Cho C. H. , Hyun D. S. 2001 “A new simplified space-vector PWM Method for three-level Inverters,” IEEE Trans.Power Electron. 16 (4) 545 - 550
Prats M. M. , Franquelo L. G. , Portillo R. , León J. I. , Galván E. , Carrasco J. M. 2003 “A 3-D space vector modulation generalized algorithm for multilevel converters,” IEEE Power Electronics Letters 1 (4) 110 - 114    DOI : 10.1109/LPEL.2004.825561
Ahmed I. , Borghate V. B. 2014 “Simplified space vector modulation technique for seven-level cascaded H-bridge inverter,” IET Power Electron. 7 (5) 604 - 613    DOI : 10.1049/iet-pel.2013.0135
Wei S. , Wu B. , Li F. , Liu C. 2003 “A general space vector PWM control algorithm for multilevel inverters,” inProc. 18th Annual IEEE APEC Vol. 1 1 562 - 568
Mohamed A. S. A. , Gopinath A. , Baiju M. R. 2009 “A simple space vector PWM generation scheme for any general n-level inverter,” IEEE Trans. Ind. Electron. 56 (5) 1649 - 1656    DOI : 10.1109/TIE.2008.2011337
Lalili D. , Lourci N. , Berkouk E. M. , Boudjema F. , Petzoldt J. , M. Y. Dali 2006 “A simplified space vector pulse width modulation algorithm for fivelevel diode clamping inverter,” in Proc. SPEEDAM 1349 - 1354
Rabinovici R. , Baimel D. , Tomasik J. , Zuckerberger A. 2010 “Series space vector modulation for multi-level cascaded H-bridge inverters,” IETPower Electron. 3 (6) 843 - 857
Houldsworth J. A. , Grant D. A. 1984 “The use of harmonic distortion to increase the output voltage of a three-phase PWM inverter,” IEEE Trans. Ind. Electron. 20 (5) 1224 - 1228