This paper presents an optimized space vector pulsewidth modulation (OSVPWM) technique for a fivelevel cascaded Hbridge (CHB) inverter. The space vector diagram of the fivelevel CHB inverter is optimized by resolving it into inner and outer twolevel space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the fivelevel CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulsewidth modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 fieldprogrammable gate array from Xilinx, Inc. The experiment results are then presented for verification.
I. INTRODUCTION
The need for a highpower control apparatus has developed in various industrial applications in recent years. Thus, several multilevel converter structures have been introduced as alternatives to highpower and mediumvoltage applications. Multilevel converters not only achieve highpower ratings but also achieve the integration of distributed generation (DG) sources. Multilevel converters have three principal topologies
[1]
,
[2]
. Among which, the cascaded Hbridge (CHB) topology is the most suitable for DG sources
[3]
. Pulsewidth modulation (PWM) techniques for multilevel converters have been studied extensively during the last few decades. A wide variety of methods, which are different in concepts and performances, have been developed to achieve one or more of the following objectives:

 wide linear modulation range

 less switching losses

 decreased total harmonic distortion(THD)

 easy implementation and less computational time[4],[5].
The space vector pulse with modulation (SVPWM) technique provides superior harmonics capacity and solves the problem of unbalanced capacitor voltages by using redundant states in the space voltage vector plane. Thus, many methods have been developed to implement SVPWM to drive voltagesource inverters
[2]

[16]
.SVPWM implementation generally involves identifying sectors, determining switching vectors, and selecting optimum switching sequences for inverters
[6]
,
[7]
. Blasko provided a classical SVPWM technique with an equal duration of zerostate vector
V_{0}
application, whereas
V_{7}
was modified. A factorvariable
K_{o}
that is proportional to the time of application of vector
V_{7}
was introduced. By changing
K_{o}
from zero to one, the duration of
V_{7}
application can be changed from 0% to 100% of the combined application time for zerostate vectors. A correlation between the modified spacevector and trianglecomparison methods (with added zero sequence) was established
[8]
. Celanovic introduced a new and computationally efficient space vector modulation (SVM) algorithm for general nlevel converters. This algorithm can be implemented on nearly any commercially available digital signal processor and is suited for execution in real time; however, this method is more complex than others
[9]
. Seo proposed a simplified SVPWM method for a threelevel inverter. This method is based on the simplification of the space vector diagram (SVD) of a threelevel inverter into that of a twolevel inverter
[10]
. Perales developed a 3D space vector algorithm for a multilevel converter to compensate for the harmonics and zerosequence components of the system. This algorithm is useful in systems with or without neutrality, unbalanced load, and triple harmonics, as well as for generating 3D control vectors
[11]
. Ahmed also developed a new simplified SVPWM technique for a sevenlevel inverter. This technique can reduce the complexity of an SVD
[12]
.
The schematic structure of a fivelevel CHB inverter is shown in
Fig. 1
(a) and its SVD is shown in
Fig. 1
(b).
(a) Fivelevel CHB inverter.(b) SVD of a fivelevel inverter.
This inverter has five possible output voltage levels for each phase. The levels, which range from +2
E
(corresponding to
P
_{2}
) to 2
E
(corresponding to
N
_{2}
), result in 5
^{3}
= 125 possible space vectors for the inverter. The number of independent space vectors is(3
n
^{2}
3
n
+1) = 61, where
n
= 5 for the five levels. (
n
 1) = 4 layers and (
n
 1)
^{3}
= 64 triangles are found in the SVD.
This paper proposes an optimized technique for SVPWM (OSVPWM) of a fivelevel CHB multilevel inverter. This technique considerably reduces calculation time, complexity, and efforts involved in constructing the SVD of a fivelevel CHB inverter. Based on the geometric simplification of the SVD, the proposed method reduces the number of two–level hexagons that should be considered from 36 to 24 (18 outer + 6 inner) for a fivelevel inverter. A further OSVPWM (FOSVPWM) technique is also proposed in this paper which further reduces the number of twolevel hexagons to 18.The simulation results of both techniques for a fivelevel CHB inverter are presented and compared with the results of the sinusoidal PWM technique (SPWM) to validate the proposed methods.
II. PROPOSED OSVPWM TECHNIQUE
The basic idea of OSVPWM is based on the concept of resolving a fivelevel SVD[
Fig. 1
(b)] into inner and outer twolevel hexagons. The selectivity of the inner and outer regions depends on the magnitude of
V_{ref}
. If
V_{ref}
magnitude is less than 2
E
, then the inner region is selected; otherwise, the outer region is selected as shown in
Fig. 2
. The hexagons in the outer or inner region are selected based on the angle θ of the original reference voltage. When
V_{ref}
is more than 2
E
, the outer region hexagons are selected. Selecting a particular hexagon in the outer region depends on angle θ as shown in
Table I
.
Selection of inner and outer regions.
SELECTION OF OUTER TWOLEVEL HEXAGONS
SELECTION OF OUTER TWOLEVEL HEXAGONS
When an outer hexagon is selected, a new reference vector
V_{refo2}
is generated, such that it originates from the center of the outer twolevel hexagons. The tip of this new vector coincides with the tip of
V_{ref5}
. Consider the case of hexagon I(OH1) shown in
Fig. 3
. Vector
V_{refo2}
is related to
V_{ref5}
based on the following relations:
Outer twolevel hexagon reference point mapping.
where
V_{5α}
,
V_{5β}
and
V_{o2α}
,
V_{o2β}
are the components of
V_{ref5}
and
V_{refo2}
along the real and imaginary axes, respectively. The mapping of all
V_{refo2}
hexagons is described in
Table II
.
MAPPING OFVREFO2FROMVREF5
MAPPING OF V_{REFO2} FROM V_{REF5}
Vector
V_{refo2}
for each of the outer hexagons has a modulation index ranging from zero to unity and an angle
θ_{o2}
ranging from zero to 2π. Angle
θ_{o2}
is also applied to each of the outer hexagons. When the inner twolevel hexagons (IH) are selected, reference vector
V_{ref5}
is mapped to the inner twolevel hexagon center reference vector
V_{refi2}
as shown in
Fig. 4
. The appropriate selection of IH depends on angle
θ_{5}
. The process of selecting an appropriate inner twolevel hexagon is described in
Table III
. Consider the case of selecting an inner twolevel hexagon1 (IH1) as shown in
Fig. 5
. Reference vectors
V_{refi2}
and
V_{ref5}
are related as follows:
Inner twolevel hexagon reference point mapping.
Outer region twolevel hexagon OH1.
SELECTION OF INNER TWOLEVEL HEXAGONS
SELECTION OF INNER TWOLEVEL HEXAGONS
where
V_{5α}
,
V_{5β}
and
V_{i2α}
,
V_{i2β}
are the components of
V_{ref5}
and
V_{refi2}
along the
α
and
β
axes, respectively. The computation
V_{refi2}
of all six inner twolevel hexagons is described in
Table 4
.
MAPPING OFVREFI2FROMVREF5
MAPPING OF V_{REFI2} FROM V_{REF5}
III. DWELL TIME CALCULATION AND SWITCHING SEQUENCE DESIGN
Dwell time calculation and switching sequence generation for the selected twolevel hexagon can be performed in a manner similar to that in the conventional twolevel SVPWM technique. Each twolevel hexagon is divided into six sectors.
The sector in reference vector
V_{refo2}
depends on its angle
θ_{o2}
.
V_{refo2}
can then be synthesized by the three stationary vectors of that sector. Dwell time calculation for the stationary vectors is performed based on the “voltsecondbalancing” principle. The outer region twolevel hexagon OH1and reference voltage
V_{refo2}
lie in Sector I as shown in
Fig. 5
.
Vectors
V
_{1}
(
P
_{2}
N
_{2}
N
_{2}
),
V
_{2}
(
P
_{2}
N
_{1}
N
_{2}
) and
P
_{2}
N
_{1}
N
_{1}
,
P
_{2}
N
_{2}
N
_{2}
are zero voltage vectors
V_{0}
. The voltsecondbalancing equation for this sector is given as follows:
where
T_{s}
is the sampling interval; and
T_{a}
,
T_{b}
, and
T_{0}
are the respective dwell times for vectors
V
_{1}
,
V
_{2}
, and
V_{0}
.
The values of
T_{a}
,
T_{b}
, and
T_{0}
are given as follows:
where
m_{α}
is the modulation index defined as follows:
After calculating dwell time intervals, an appropriate design for the switching sequence is required. The typical sevensegment switching sequence is used in this scheme. The switching sequence should be designed, such that a change from one switching state to the next involves only one leg, and a change from one sector to the next involves zero or a minimum number of switching
[1]
. With these constraints, the sevensegment switching sequence for vector
V_{refo2}
Sector I shown in
Fig. 5
is given as follows:
(
P
_{1}
N
_{2}
N
_{2}
), (
P
_{2}
N
_{2}
N
_{2}
),(
P
_{2}
N
_{1}
N
_{2}
), (
P
_{2}
N
_{1}
N
_{1}
),(
P
_{2}
N
_{1}
N
_{2}
), (
P
_{2}
N
_{2}
N
_{2}
), (
P
_{1}
N
_{2}
N
_{2}
).
Similarly, the switching sequence for Sector II is given as follows:
(
P
_{1}
N
_{2}
N
_{2}
), (
P
_{2}
N
_{2}
N
_{2}
), (
P
_{2}
N
_{1}
N
_{2}
), (
P
_{2}
N
_{1}
N
_{1}
), (
P
_{2}
N
_{1}
N
_{2}
), (
P
_{2}
N
_{2}
N
_{2}
), (
P
_{1}
N
_{2}
N
_{2}
).
IV. FOSVPWM
This technique further reduces the number of twolevel hexagons that should be considered. Consequently, it decreases the complexity and efforts involved in the SVPWM of a fivelevel inverter. A fivelevel SVD for this technique is initially resolved into inner and outer regions, similar to in the OSVPWM technique. Thus, the number of twolevel hexagons that should be considered for the FOSVPWM of a fivelevel inverter is reduced to 18. The modulation index Ma for SVM is defined as the maximum value(
M_{α}
= 1) that corresponds to the radius of the largest circle that can be inscribed in the SVD. The fivelevel SVD with such a circle is shown in
Fig. 6
.
Fivelevel SVD with an inscribing circle for M_{α} = 1.
If only 12 OHs are considered (even for
M_{α}
= 1), then only the dark shaded portion of the SVD is left unattended. If this area is ignored, then the SVM of a fivelevel inverter involves only 18 twolevel hexagons. Selecting the appropriate twolevel hexagon depends on the magnitude and angle of reference vector
V_{ref5}
described in
Table V
.
SELECTION OF THE OUTER TWOLEVEL HEXAGONS IN THE FOSVPWM TECHNIQUE
SELECTION OF THE OUTER TWOLEVEL HEXAGONS IN THE FOSVPWM TECHNIQUE
The decrease in complexity is achieved at the cost of a slightly increased THD of the output voltage. This increase is only for
M_{α}
> 0.75, where
M
_{α}
is the modulation index for the fivelevel SVD. If the tip of vector
V_{ref5}
lies in the dark unattended portion, then one of the OHs is selected depending on the angle
θ_{5}
of
V_{ref5}
. A new reference vector
V_{refo2}
is then generated, as in the case of the OSVPWM technique, with its origin located at the center of the selected twolevel hexagon.
V. SIMULATION RESULTS
The proposed methods are simulated with MATLAB/SIMULINK. The simulation is conducted for a fivelevel CHB inverter at different values of the modulation index
M_{α}
. The results are compared with those of the conventional SPWM technique to validate the viability of the proposed techniques. The simulation parameters are shown in
Table VI
, and the simulation results are shown in
Fig. 7
and 8 for the modulation indices
M_{α}
= 1.0 and
M_{α}
= 0.8, respectively.
Output line voltage waveforms at Ma = 1 for SPWM, OSVPWM and FOSVPWM. (b) OSVPWM. (c) FOSVPWM.
Output line voltage waveforms at Ma = 0.8 for SPWM, OSVPWM and FOSVPWM. (a) SPWM. (b) OSVPWM. (c) FOSVPWM.
SIMULATION PARAMETERS USED FOR FIVELEVEL CHB INVERTER
SIMULATION PARAMETERS USED FOR FIVELEVEL CHB INVERTER
The sampling frequency for the SVM schemes is generally preferred as 6
N
times the output frequency, where
N
is an integer. The sampling frequency for the SVM schemes is
f_{s}
= 1.5 kHz, assuming a value of
N
= 5. For the SPWM schemes, the sampling frequency should be [(2
N
+ 1) × 3] times the output frequency
[17]
, [18]. Thus,
f_{s}
= 1.65 kHz for these schemes.
Table VII
shows the THD of the output line voltage and the peak magnitude of the fundamental components at various
M_{α}
values.
THD AND PEAK VALUE OF FUNDAMENTAL COMPONENT (V1M) OF OUTPUT LINE VOLTAGE
THD AND PEAK VALUE OF FUNDAMENTAL COMPONENT (V1_{M}) OF OUTPUT LINE VOLTAGE
These results show that the proposed optimized techniques are comparable with the established SPWM schemes. The proposed techniques exhibit satisfactory performance for all values of the modulation index
M_{α}
. The THD obtained with these techniques is slightly higher than that obtained with the SPWM scheme. In addition, the fundamental components of the output voltage obtained with these schemes are higher than those obtained with the SPWM scheme. The proposed schemes also exhibit significant improvement over the SPWM scheme for low values of
M_{a}
. In particular, for
M_{α}
≤ 0.2, the FOSVPWM scheme presents remarkable improvement in performance over the SPWM scheme. This condition is advantageous in applications wherein the inverter may sometimes be required to operate at low modulation indices.
Thus, the proposed techniques perform comparably with the previously proposed SVM techniques for multilevel inverters while considerably optimizing the control algorithm.
VI. EXPERIMENT RESULTS
An experimental study was conducted to confirm the proposed control methods. Experimental set up as shown in
Fig. 9
, in which two Hbridges are connected in series per phase. An XC3S400 fieldprogrammable gate array (FPGA) from Xilinx, Inc. (California, USA) was used to realize the proposed control schemes. The experimental system parameters are listed in
Table VIII
.
Experimental setup of Five level HBridge Inverter.
Output line voltage waveforms at Ma = 1 for OSVPWM and FOSVPWM.
Output line voltage waveforms at Ma = 0.8 for OSVPWM and FOSVPWM.
EXPERIMENTAL PARAMETERS USED FOR FIVELEVEL CHB INVERTER
EXPERIMENTAL PARAMETERS USED FOR FIVELEVEL CHB INVERTER
VII. CONCLUSIONS
This study presents the OSVPWM technique that optimizes the SVPWM of multilevel inverters. The proposed technique is based on resolving the multilevel inverter SVD into inner and outer region twolevel hexagons. This technique is general and can be applied to the SVPWM of all three principal topologies for multilevel converters at any number of levels. The advantage of applying this technique increases as the number of levels increases.
An FOSVPWM technique has also been presented for the SVM of a fivelevel inverter. This technique reduces the complexity and effort required for the SVPWM of a fivelevel inverter by nearly 50%. In particular, the OSVPWM technique reduces the fivelevel SVPWM to a SVPWM problem of 24 twolevel hexagons. The FOSVPWM technique further reduces this number to 18.
The simulation results for both techniques are presented for a fivelevel CHB inverter. The results are compared with those of the SPWM technique, which proves the validity of the proposed techniques for different values of the modulation index. The experiment results are then provided for the proposed methods to verify the correctness of the realtime simulation system. The FPGAbased realtime emulation will be a popular component of realtime simulation. The application of these techniques significantly reduces the complexity and efforts involved in the SVPWM of higher level inverters.
BIO
Amarendra Matsa was born in Andhra Pradesh, India on August 23, 1984. He received his B.Tech and M.Tech degrees from Jawaharlal Nehru Technological University, Hyderabad, India in 2006 and 2009, respectively. He is currently pursuing his Ph.D. at Visvesvaraya National Institute of Technology (VNIT), Nagpur, India. His current research interests include power electronics, new control algorithm techniques for gridintegrated distributed generation, and microgrids.
Irfan Ahmed received his B.E. (Electrical Engineering) from Nagpur University, India, in 2001, and M.Tech (Power Electronics, machines, and drives) from the Indian Institute of Technology, Roorkee, India, in 2004. From 2004 to 2011, he worked as a faculty member at Anjuman College of Engineering and Technology, Nagpur, India. He is currently pursuing his Ph.D. at the Department of Electrical and Electronics Engineering, VNIT, Nagpur, India. His research interests include power electronics and its applications to power systems and drives
Madhuri A. Chaudhari was born in Maharashtra, India on January 28, 1968. She received her B.E. from Amaravati University, Amaravati, India; M.Tech from Visvesvaraya Regional College of Engineering, Nagpur University, Nagpur, India; and Ph.D. from VNIT, Nagpur, India (all in electrical engineering). She is currently an associate professor at the Department of Electrical Engineering, VNIT. Her research interests are in the areas of power electronics, FACTS, and AC–DC drives. Dr. Chaudhari is a member of the IEEE, the Institution of Engineers (India), and the Indian Society for Technical Education.
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