Phaselocked loops (PLL) based on the synchronous reference frame (SRFPLL) have recently become the most widelyused for grid synchronization in three phase gridconnected inverters. However, it is difficult to study their performance since they are nonlinear systems. To estimate the performances of a SRFPLL, a canonical smallsignal linearized model has been developed in this paper. Based on the proposed model, several significant specifications of a SRFPLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth, and steadystate error have been investigated. Finally, a noise model of a SRFPLL has been put forward to analyze the noise rejection ability by computing the SNR (signaltonoise ratio) of a SRFPLL. Several simulation and experimental results have been provided to verify and validate the obtained conclusions. Although the proposed model and analysis method are based on a SRFPLL, they are also suitable for analyzing other types of PLLs.
Ⅰ. INTRODUCTION
A gridconnected inverter perfectly matches the philosophy of a phaselocked loop (PLL), since it should operate in harmony with the utility voltage. It should phaselock its internal oscillator to the positive sequence voltage at the fundamental frequency in three phase systems to produce an amplitude and phasecoherent utility voltage that is applied to control gridconnected inverters or microgrid inverters, such as distributed generation and storage systems, flexible ac transmission systems (FACTS), power line conditioners and uninterruptible power supplies (UPS)
[1]
,
[2]
. Regardless of the detection approach used, it should work as quickly and accurately as possible, even if the utility voltage is distorted and unbalanced.
There are three main detection approaches in the literature. They are the zerocross phase detection method, the stationary reference frame phase detection method, and the synchronous reference frame phase detection method
[3]
. A conversional gridconnected inverter offers a low degree of control and is synchronized to the utility by detecting the zerocrossing of the utility voltage. This assumes that the magnitude of the utility is well known and that the frequency is kept constant. This technique suffers from some drawbacks, such as inaccuracy and the detection of multiple zerocrossings in the case of a distorted grid voltage. To overcome these drawbacks, some modified methods based on comparators circuits with dynamic hysteresis
[4]
, curvefilters
[5]
or predictive digital filtering algorithms
[6]
have been proposed. Since these methods employ a comparator as phase detector (PD) for detecting changes in the polarity of the grid voltage, the phase sensitivity should be
U_{g}/π
for a single phase system, and
3U_{g}/π
for three phase voltages, where
U_{g}
is the phase magnitude of the utility voltage. A PI controller is used as a loop filter. More importantly, it has a smallsignal linearized model that is identical to that of the conventional SRFPLL.
The most popular and essential technique is a threephase locked loop based on the synchronous reference frame
[7]
. This is often referred as the conventional SRFPLL
[8]
. Since a PLL contains a phase detector, it is a nonlinear system, which is difficult for one to predict the electrical properties. Based on the operational principle of the conventional SRFPLL, a canonical smallsignal linearized model has been developed in Section Ⅱ.
Based on this model, several significant specifications of the SRFPLL, such as the capture time, capture rang, bandwidth, the product of capture time and bandwidth have been investigated in Section Ⅲ. Then, the steadystate errors under various operation conditions, such as phase step, frequency step, amplitude step, amplitude ramp and so on, have also been discussed. These various operation conditions correspond to some practical cases, such as the phase jump of the utility voltage, lowvoltage ridethrough, and microgrid inverters working in the island condition by employing the frequency droop control.
In Section Ⅳ, a noise model of the SRFPLL has been put forward to estimate its performance in the presence of noise. By applying the proposed noise model, the noise rejection ability by computing the SNR of the SRFPLL has been investigated. Several simulation and experimental results have been provided to verify and validate the obtained conclusions.
Although the proposed model and analysis method comes from the SRFPLL, they are also suitable for analyzing other types of PLLs.
Ⅱ. CONVENTIONAL SRFPLL AND ITS SMALL–SIGNAL LINEARIZED MODEL
Fig. 1
shows the general structure of the conventional SRFPLL. It can be seen that this structure needs a coordinate transformation form
a,b,c
→
dq
, and the lock is realized by setting the reference
U_{q}
^{*}
to zero. A regulator, usually a
PI
, is used to control this variable, and the output of this regulator is the grid frequency. After the integration of the grid frequency, the utility voltage angle is obtained, which is fed back into the
αβ
→
dq
transformation module to transform it into the synchronous rotating reference frame
[8]
. If the utility voltage is unbalanced, such as the presence of an asymmetrical fault or distortion, it contains a positivesequence and negativesequence as well as high order harmonics. It is well known that the fundamental component of the positivesequence is uniquely useful and the other components will affect the performance of the SRFPLL. Therefore, a noise source
U_{N}
is added which represents all of the harmonics except for the fundamental component of the positivesequence.
General structure of conventional SRFPLL.
If the utility voltage is balanced and nondistortion, the coordinate transformation form can be expressed as:
In the steady state, the input voltage of the
PI
controller,
u_{q}
, is equal to zero, and
Substituting this condition into Eq. (1) yields:
It can be observed from Eq. (2) that the d component represents the amplitude of the three phase voltage
v_{a}
,
v_{b}
, and
v_{c}
, and its phase angle can be detected by the output of the PLL,
if the utility voltage is balanced and nondistortion.
 A. Operational Principle of the SRFPLL and the Proposed SmallSignal Linearized Model
The
q
component
u_{q}
in Eq. (2) is used to form a PLL, referred as a simplified model of the SRFPLL, as shown
Fig. 2
. It consists of phase detector (
PD
), a
PI
controller and
VCO
. The operational principle of the PLL is as follows: according to the phase difference
the
PD
produces the voltage
u_{q}
. It is sent to the
PI
controller to suppress its highfrequency component, thus a DC output voltage uf is developed. This voltage adjusts the frequency
to tend toward the incoming frequency ω, where
Until
and
u_{q}
=0, the PLL reaches the steady state and maintains the output frequency and phase angle.
Simplified model of SRFPLL.
It should be noted that the PD is a nonlinear device due to its sinusoidal function. However, if the phase error,
θ_{e}
is very small, less than π/6, the output of the PD can be approximated by:
where
Therefore, when the PLL is locked or tends to lock, a smallsignal linearized model of the PD can be given by:
Thus, a smallsignal linearized model of the SRFPLL is proposed, as depicted in
Fig. 3
.
Smallsignal linearized model of SRFPLL.
Based on the proposed smallsignal linearized model of the SRFPLL, some typical transfer functions of the SRFPLL can be derived as follows.
The openloop transfer function of the SRFPLL is
The closedloop transfer function of the SRFPLL is
The inputtoerror transfer function of the SRFPLL is
The noisetoerror transfer function the SRFPLL is
 B. Stability Consideration
The openloop transfer function, Eq. (5), can be rewritten as:
where
The substitution of
s
=
jω
into Eq. (9) yields the frequency repose.
Fig. 4
illustrates a Bode plot of the magnitude frequency response of
T(s)
.
Magnitude frequency response of T(s).
In
Fig. 4
, let the crossover frequency
f_{c}
be
f_{z}
so that the phase margin is about 45 degrees. Using the identity
f_{c}
=
f_{z}
yields:
The substitution of
U
^{+}
=466.62 and
f_{c}
=2.7kHz yields
k_{p}
=28.277 and
k_{i}
=3.73*10
^{3}
. The simulation results are demonstrated in
Fig. 5
. It can be seen that the crossover frequency is about 2.71kHz and that the phase margin is about 53 degree to ensure stability and a fast dynamic response.
The simulation results of the frequency response T(s), the parameters are: U+=466.62, fc=2.7kHz, kp=28.277 and ki=3.73*103.
Ⅲ. PERFORMANCE ANALYSIS OF THE SRFPLL
The performance of the SRFPLL is estimated in this section, including the capture time, the capture range, and the steadystate error.
 A. Capture Time of SRFPLL
The normalized transfer function of (6) can be rewritten as:
where
ω_{n}
^{2}
=
U
^{+}
k_{i}
,
By ignoring the LHP (left half plane) zero in Eq. (11), it can be approximated by a standard second order transfer function
The dynamic analysis of a standard secondorder system has been studied in many textbooks. The following approximated formulas are present in reference
[9]
. The settling time
t_{s}
can be calculated by the formula in
[10]
,
where
τ
= 1/
ςω_{n}
.
It is noted that the settling time is usually called the capture time in a PLL.
According to the parameters
k_{i}
=3.73×10
^{3}
and
k_{p}
=28.277 in Section Ⅱ, the damping factor, natural frequency and capture time can be calculated, yielding
ω_{n}
=1.139×10
^{4}
rad/s, ς=0.5 and
t_{s}
=0.8ms, respectively.
The bandwidth of the PLL is:
For
ς
= 0.7 , the
ω
_{3dB}
is:
According to Eq. (12), Eq. (13) and Eq. (14), an important formula can be derived that the product of the capture time
t_{s}
and the bandwidth ω
_{3dB}
is constant, and the value of the product is
ω
_{3dB}
t_{s}
≈ 2.3 under the condition of
ς
=0.7 and a 1% steadystate error for the step response. In other words, the capture time
t_{s}
is inversely proportional to the bandwidth
ω
_{3dB}
.
Experimental results are shown in
Fig. 6
. In
Fig. 6
(a),
CH1
,
CH2
and
CH3
are the threephase utility voltages, and
CH4
is a control signal. The phase of the utility voltage jumps forward 180 degree while the control signal
CH4
has a step change at a triggering time point. In
Fig. 6
(b),
CH1
is the estimated output phase
of the SRFPLL, and
CH2
is the control signal. The vicinity waveforms of
Fig. 6
(b) at the triggering time point are enlarged as illustrated in
Fig. 6
(c) to measure the capture time,
t_{s}
≈1ms. The steadystate error
θ_{e}
is denoted by
CH1
shown in
Fig. 6
(d).
Experimental waveforms of SRFPLL when phase jumps. (a) Threephase utility voltage. (b) Estimated phase of SRFPLL. (c) Enlarged waveform of (b), (d) steadystate error.
Note that the capture time displays a considerable error between the theoretical result
t_{s}
=0.8ms from Eq. (12) and the experimental result
t_{s}
=1ms. Therefore, the expression result from Eq. (12) should be taken only as a guide rather than precise formula. This formula provides a rough estimate of the time response of the system since the time taken by the coordinate transformation in the SRFPLL and the influence of the ignored zero
of Eq. (11) are not yet considered in this formula
[11]
. This should be checked, usually by simulation, in order to verify whether the time specification has been properly met or not.
 B. Capture Range of SRFPLL
Another significant parameter of the PLL, called the capture range Δ
ω_{H}
, is the frequency range at which a PLL is able to keep statically phaselocked. This parameter can be calculated by:
where F(0) is the DC gain of the controller in
Fig. 3
.
If a PI controller is selected, the capture range Δ
ω_{H}
is infinite because PI controller has an infinite DC gain. Therefore, the capture range Δ
ω_{H}
is only limited by the maximum value of the integrator output. An infinite capture rang implies that the PLL has no ability to reject any noise since it can lock all of the frequency signals. Therefore, a PI controller is not a good choice to suppress the noise present in a PLL.
 C. Steadystate Error of the SRFPLL
In this section it is investigated how the PLL responds under various conditions: phase step, frequency step, frequency ramp, and magnitude step as well as magnitude ramp.
In practice, when a PLL is used for synchronization with the grid voltage in a gridconnected inverter, and a set of microgrid inverters working in the island condition by employing the frequency droop control strategy
[12]
. The phase step, frequency step and ramp of the PCC voltage are always encountered. Moreover, the magnitude step and ramp always occur when the inverter is controlled to ride through the grid fault
[13]
.
1) Case 1, Steadystate error in the case of variations in the phase and frequency of utility voltage:
By applying Eq. (7), the steadystate error of the SRFPLL can be expressed as:
If a phase step is applied to the utility voltage as a reference signal, then θ(s)=1/s and:
This conclusion has already been proved in
Fig. 6
(d).
Similarly, since θ(s)=ω(s)/s, the steady state error formula of the frequency variation applied to a reference input gives:
If a frequency step of the utility voltage is used as an input, then
ω(s)
=
1/s
and:
If a frequency ramp of the utility voltage acts on the input, then ω(s)=1/s
^{2}
and:
The openloop transfer function of (5) shows that this PLL is a type Ⅱ system, with two poles at the origin. This means that it is able to track the utility voltage phase step, frequency step and phase ramp (change slowly in a constant slop) without any steadystate errors.
Moreover, the normalized closedloop transfer function from
ω
to
shown in
Fig. 3
, can be written as:
Compared with the expression of
H_{θ}
, as shown in Eq. (11), a pole at the origin is added in
H_{ω}
. A diagram of the poles and zeros location of the closedloop transfer function
H_{ω}
is illustrated in
Fig. 7
.
Diagrams of the poles and zeros location of the closedloop transfer function H_{ω} .
As show in
Fig. 7
, the dominant pole is at the origin, rather than the pair of complex poles,
p_{1}
and
p_{2}
. Thus, the system presents firstorder system features so that its dynamic performance is not as good as the pervious closed system defined by Eq. (12). Experimental results are shown in
Fig. 8
. In
Fig. 8
(a),
CH1
,
CH2
and
CH3
are threephase utility voltages, and
CH4
is a control signal. A frequency jump of the utility voltage occurs from 50Hz to 60Hz, while the control signal of
CH4
has a step change at a triggering time point. In
Fig. 8
(b),
CH1
shows a steadystate error for the SRFPLL. It can be observed that its steadystate error is zero, but the capture time
t_{s}
is about 25ms.
Experimental waveforms of SRFPLL when frequency jumps. (a) Utility voltage. (b) Waveform of steadystate error.
In addition, a constant steady state error should exist in a conventional SRFPLL when it is used in a set of microgrid inverters working in the isolation island condition by adopting the frequency droop control strategy.
2) Case 2, steadystate error analysis of the magnitude variation of the utility voltage applied to an input signal:
When the magnitude of the utility voltage fluctuates, and the phase is kept constant, the equivalent model is shown in
Fig. 9
. There are two parts in this model. One is the linear timevarying part, and the other is the linear timeinvariant part. The system performance of the magnitude variation is analyzed in the Bode diagram shown in
Fig. 10
. The nonlinear system is analyzed by using the method of describing function.
The equivalent model when the magnitude of the utility voltage fluctuates, and phase is kept constant.
The Bode diagram when the amplitude of the utility voltage fluctuates.
When the magnitude of the utility voltage is normal, k
_{t}
is equal to k
_{t1}
. When the magnitude of the utility voltage drops at time=t
_{2}
, the gain k
_{t}
is equal to k
_{t2}
, and the amplitude frequency response curve moves downward. However, the phase frequency response curve remains unchanged.
In summary, as shown in
Fig. 10
, when the magnitude of the utility voltage drops, the gaincrossover frequency and phase margin decrease, but the system remains stable for the PI controller. Variations in the magnitude have no effect on the steadystate error.
Experimental results are shown in
Fig. 11
and
Fig. 12
. In
Fig. 11
(a),
Ch1
,
Ch2
and
CH3
, are threephase utility voltages, and CH4 is a control signal. The amplitude of the utility voltage drops from 466V to 233V while the control signal steps. As shown in
Fig. 11
(b),
CH1
displays the steadystate error for the SRFPLL, and
CH2
is a control signal. It can be seen that the magnitude step has no effect on the steadystate error.
Experimental waveforms of SRFPLL when a amplitude step of the utility voltage is applied. (a) Utility voltage. (b) Waveform of steadystate error.
Experimental waveforms of SRFPLL a amplitude ramp of utility voltage is applied. (a) Utility voltage. (b) Waveform of steadystate error.
As shown in
Fig. 12
(a), the amplitude ramp of the utility voltage is applied, and
Fig. 12
(b) shows that the amplitude ramp has no effect on the steadystate error.
It can be seen from the above analysis that if the amplitude of the utility voltage fluctuates, the conventional SRFPLL has no steadystate error. It only decreases the crossover frequency and phase margin of the system.
The performance of the conventional SRFPLL has been summarized and listed in
Table I
.
THE PERFORMANCE OF CONVENTIONAL SRFPLL
THE PERFORMANCE OF CONVENTIONAL SRFPLL
Ⅳ. PERFORMANCE IN THE PRESENCE OF NOISE
Noise is an extremely important issue when a PLL is employed to detect the fundamental component of the positivesequence voltage in the control systems of gridconnected inverters or microgrid inverters.
 A. Noise Model of SRFPLL
If the utility is unbalanced and its output voltage contains some high order harmonics, such as the 3
^{rd}
, 5
^{th}
, 7
^{th}
…, then the voltage vector expression in the
dq
plane in Eq.(1) may be modified as follows:
The formula of (22) can be rewritten in the following compact form:
where
Assuming that the positivesequence component is locked in the steady state, and then the formula of (22) becomes:
The first term of Eq. (24) is the fundamental component of the positivevoltage, the summation term is the high order harmonic components and the third is the negativevoltage component.
The
q
component of Eq. (24) can be expressed as:
Hence, the noise source is represented by
U_{N}
, as illustrated in
Fig. 1
.
The smallsignal linearized model of the SRFPLL, shown in
Fig. 3
, can be modified to achieve the noise model of the SRFPLL, shown in
Fig. 13
. Here,
k_{o}
is the sensitivity of the voltagecontrolled frequency oscillator (VCO), and it is equal to 1.
Noise model of SRFPLL.
 B. Noise Performance
By applying the Mason formula to the block diagram of the noise model shown in
Fig. 13
, the inputtooutput transfer function H
_{N}
(s) is given by:
where
If a PI controller is used, and the parameters are:
U
^{+}
=466.62,
k_{p}
=28.277 and
k_{i}
=3.73*10
^{3}
, frequency response of
H_{N}(s)
is depicted in
Fig. 14
.
Frequency response of the noise transfer function H_{N}(s), the parameters are: U^{+}=466.62, f_{c}=2.7kHz, k_{p}=28.277 and k_{i}=3.73*10^{3}.
The following conclusions can be drawn form
Fig. 14
. The frequency response of
H_{N}(s)
exhibits a highpass characteristic with a cutoff frequency
The cutoff frequency
f_{c}
is smaller than the grid frequency
f_{o}
. In other words, according to Eq. (25), the all components of
U_{N}
can pass through the controller directly without any attenuation and reach to the input terminal of the VCO. Therefore, the SRFPLL does not have the ability to reject noise.
Usually, a lowpass filter is included in the loop to alleviate noise as shown in
Fig. 15
. Since 1/
T_{L}
≪ 2
ω
_{0}
is satisfied, and the noise cannot reach the terminal of the VCO, the SRFPLL has the ability to reject noise.
Smallsignal linearized model of SRFPLL with lowpass filter.
The openloop transfer function
T(s)
is modified as:
The zero of the PI controller
ω
_{z}
should be selected to be lower than
ω_{p}
, and the amplitude frequency response of
T(s)
can be plotted, as shown in
Fig. 16
. The phase margin is determined by the middlefrequencyband of (
ω_{p}

ω
_{z}
). Usually, let
ω_{p}
/
ω
_{z}
≈ 510 so that the phase margin is about 3060 degrees, and the crossover frequency is equal to
ω_{p}
/3.
The bode diagram of the openloop transfer function T(s) of SRFPLL with low pass filter.
A lowpass filter is added into the loop to alleviate noise. However, the above analysis indicated that the crossover frequency is rather low, and the fast dynamic response is not satisfied.
Fig. 17
shows a simulation result using MATLAB with the following parameters:
ω_{p}
=314rad/s,
ω
_{z}
= 40rad/s, and
ω_{p}
/
ω
_{z}
= 7.8. The simulation result demonstrates that the crossover frequency is only 18Hz, and phase margin is about 50 degrees.
Frequency response of the openloop transfer function T(s) of SRFPLL with low pass filter.
The experimental results are shown in
Fig. 18
. In
Fig. 18
(a),
CH1
,
CH2
and
CH3
, are threephase utility voltage, and
CH4
is a control signal. A phase step of 180 degrees is applied, and a 3
^{th}
harmonic component with a value of five percent is injected into the grid. As shown in
Fig. 18
(b),
CH1
and
CH2
represent the input and output signals of the lowpass filter. This shows that the harmonic component is eliminated with the lowpass filter, but the capture time
t_{s}
is about 50ms. In sum, the ability to suppress noise and the dynamic response are mutually contradictory for the SRFPLL.
Experimental waveform of SRFPLL with low pass filter when phase step of the threephase voltage is applied. (a) Utility voltage. (b) Waveform of steadystate error.
 C. SNR (signaltonoise ratio) of the SRFPLL
Based on the noise model of the SRFPLL shown in
Fig. 13
and Eq. (26), the input noise voltage of the VCO is given by:
Eq. (25) shows that the noise contains two parts: unbalance noise and high harmonic noise. For gridconnected inverters, unbalance noise is dominant. However, the high order harmonic noises should be considered for microgrid inverters.
1) Case 1, SNR for unbalance noise:
For gridconnected inverters, unbalanced noise is dominant. Therefore, Eq. (28) is employed to compute the unbalance noise response, such as:
It can be seen from
Fig. 14
that the amplitude is 4.88dB, and the phase is 14 degree at f=100Hz. If the noise voltage is
U_{N}
(
t
)=
U_{N}
sin(2
ωt
), the input voltage of the VCO is:
The output of the VCO is a constant with value of 50Hz under ideal conditions. If the utility voltage is unbalanced, the output frequency of the VCO is given by:
Eq. (31) indicates that the output frequency of the PLL becomes a frequency modulation signal instead of a constant frequency, as shown in
Fig. 19
.
Estimating frequency waveforms of the PLL by affecting the unbalance noise.
The signalnoiseratio is defined as:
For example, when the parameters are:
U_{N}
= 0.3
U
^{+}
, the SNR is only
SNR_{UB}
= 2.14
dB
.
It is obvious that the SNR of the SRFPLL is so low that the output frequency of the SRFPLL is seriously distorted.
2) Case 2, SNR for high harmonic noise:
The grid voltage may be distorted in the case of microgrids working in the island condition or in weak grids with a high grid impedance because their gridvvoltage is prone to notable distorted by harmonics, switching notches and noise. Therefore, the highorder harmonic noise needs to be considered in this case.
If the noise voltage is defined as:
The voltage of the input terminal of the VCO is:
The output frequency of the VCO is given by:
The signalnoiseratio is defined as:
Therefore, the output frequency of the PLL is 100π plus the even harmonic components if the utility voltage is distorted.
Ⅴ. CONCLUSIONS
It is difficult to investigate the electric characteristics of PLLs because they are nonlinear systems. This results from the coordinate transformation in the control block. In this paper, a canonical small–signal linearized model of the SRFPLL has been developed to study the following issues: (1) the phaselocked process and operational principle; (2) the determination of the controller parameters; (3) the performance under various conditions.
By adopting the canonical small–signal linearized model, the following conclusions are obtained:
(1) The SRFPLL with a PI controller is a normalized secondorder system, and several formulas have been supplied in this paper to calculate its significant specifications such as the capture time, the capture rang, the bandwidth, the product of capture time and bandwidth as well as the parameters of the PI controller.
(2) It is revealed by analysis and experiment results that the steadystate error of the SRFPLL is zero under the conditions of phase step, frequency step, amplitude step and ramp. However, the SRFPLL has a constant error in case of a frequency ramp.
Noise analysis is also an extremely important issue for the PLL used in the control of gridconnected power inverters or macro grid inverters. In the performance analysis in the presence of noise, the following results and conclusions can be achieved:
(1) A noise model of the SRFPLL has been proposed to investigate the performance of the SRFPLL in the presence of noise.
(2) The SRFPLL is incapable of rejecting noise. However, a lowpass filter in the loop can attenuate the noise at the cost of increasing the capture time.
(3)Two categories of the SNR have also been calculated.
In summary, this paper presents a detailed derivation of smallsignal analysis methods to study the SRFPLL. Valuable conclusion can be achieved with this method. These conclusions are verified and validated by simulation and experimental results.
Moreover, the conventional SRFPLL can be commonly used as an essential block in some advanced PLLs, such as DDSRFPLL
[14]
, IPTPLL
[15]
, PQPLL
[15]
, DSCPLL
[16]
,
[17]
, DSOAFPLL
[18]
, FRFPLL
[19]
and SSIPLL
[20]
. They have a smallsignal linearized model that is identical to that of the conventional SRFPLL. As a result, the proposed model and analysis method are suitable for the other typical PLLs.
Acknowledgements
Great supports were given by Natural Science Foundation of China (No. 51277004) and The Importation and Development of HighCaliber Talents Project of Beijing Municipal Institutions (IDHT20130501).
BIO
Peng Mao received his M.S. degree (with honors) from the School of Information Engineering, North China University of Technology, Beijing, China, in 2009, and his Ph.D. degree in Power Quality Improvements for Grid Connected PV Inverters from the School of Information and Electronics, Beijing Institute of Technology, Beijing, China. His work focused on the control of grid connected PV inverters. He is currently involved in the real time performance analysis of grid connected PV inverters under faulty conditions. His current research interests include inverter control for renewable energy and drive applications, power quality issues, and nonlinear control.
Mao Zhang received his M.S. degree from the University of Central Lancashire, Preston, UK, in 2011, and his Ph.D. degree in Photovoltaic Array Improvements for Grid Connected PV Inverters from the School of Information and Electronics, Beijing Institute of Technology, Beijing, China. His current research include the design, analysis, and characterization of power semiconductor devices, resonant power conversion and inverters.
Weiping Zhang was born in Xi’an, China in 1957. He received his B.S. degree from Northeast University, Shenyang, China, in 1982, his M.S. degree from the Beijing Institute of Technology, Beijing, China, in 1987, and his Ph.D. degree from Zhe Jiang University, Hangzhou, China, in 1998. He is currently a Professor at the North China University of Technology, Beijing, China. He holds nine Chinese patents, and has authored or coauthored more than 30 journal articles published in refereed journals. His current research interests include highintensity discharge lamp ballasts, resonant converters, electromagnetic compatibility, power electronic integration and renewable energy.
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