A digital controller with a lowpower approach for pointofload synchronous buck converters is discussed and compared with its analog counterpart to confirm its feasibility for system integration. The trimode digital controller IC in 0.35 μm CMOS process is presented to demonstrate solutions that include a PID, quarter PID, and robust RST compensators. These compensators address the steadystate, standby, and transient modes according to the system operating point. An idletone free condition for Σ–Δ DPWM reduces the inherent tone noise under DCexcitation. Compared with that of the traditional approach, this condition generates a quasipure modulation signal. Experimental results verify the closedloop performances and confirm the powersaving mechanism of the proposed controller.
I. INTRODUCTION
Drivers, power switches, passive components, and controllers are the building blocks of lowpower DC–DC converters. Integrating these building blocks into a single chip has become possible with the development of modern semiconductor technologies. This trend has facilitated the emergence of power supply onchip (PwrSoC), the application of which covers the typical operations of batterypowered embedded systems. Some PwrSoCs require high switching frequency at multiMHz to maintain a relatively small size of onchip and accompanying passive components. Meanwhile, this componentreduce the additional losses caused by the increase in switching frequency to ensure low power consumption .
Two solutions can be used to implement a controller in PwrSoC. Digital control is less sensitive to external perturbations, such as process, voltage and, temperature variations, than analog control . The former enables effective but complex control strategies to improve dynamic performance. Moreover, the digital controller design cycle can be accelerated by using available electronic design automation (EDA) tools. The verified digital controller code at the register transfer level (RTL) is an intellectual property (IP) core that can be reused in different technologies. Therefore, digital control is becoming a potential alternative for its analog counterpart
[1]

[8]
.
Scaling semiconductor technologies improves controller power efficiency from the digital designer viewpoint in creating the PwrSoC prototype. Therefore, the power consumption of a digital controller must be compared with that of analog controllers to evaluate the feasibility for application to PwrSoC. This study proposes a poweraware digital controller devoted to PwrSoC. On the basis of the experimental results from a 0.35 μm test chip that underwent a CMOS process, we illustrate a power assessment model with suggested feasible applications.
Schematic diagram of synchronous DC–DC voltage regulator under digital control.
Fig. 1
shows a typical digitally controlled synchronous DC–DC voltage regulator. The feedback loop is composed of an analogtodigital converter (ADC), a digital control law, and a digital pulse width modulator (DPWM). ADC is traditionally implemented through windowedbased techniques
[9]
,
[10]
, which are not within the scope of this paper. Another issue is generating highfrequency, highresolution DPWM signals to satisfy the accuracy requirement for the converter output, to ensure low system clock frequency, and to achieve reasonable power consumption
[11]
.
The performance of dedicated compensators is critical to conversion efficiency. An ideal compensator operates well in both static and transient states, as well as performs with a relatively simple physical implementation. Most existing digital controllers are designed by using linear PID control
[9]
,
[12]
,
[13]
. Implementing linear compensators in a field programmable gate array (FPGA) or application specific integrated circuit (ASIC), notably the voltagemode PID controller, is beneficial for hardware resources. However, performance generally depends on operating conditions; the presence of parasitic elements, timevarying loads, and variable supply voltages can degrade control performance. Robust RST control has been proven efficient against load, reference, and quantization variation
[14]
. R – S – T refers to each polynomial to be deduced by the design procedure. Based on an offline tuning polynomial algorithm, RST control outperforms the PID controller but requires more hardware resources and consequently has higher power consumption.
This study proposes a trimode controller that achieves a tradeoff between dynamic response and power consumption. For high dynamic performance, RST control is applied in the transient mode, PID control is applied in the steadystate mode, and PID compensator is applied in the standby mode. The appropriate parameters are tuned to ensure that the clock frequency is below the switching frequency.
With sufficient resolution achieved by using the noiseshaping concept, an effective DPWM solution is achieved through a Σ–Δ modulator over several switching periods. Compared with delayline methods, this solution is achieved without sacrificing hardware resources
[9]
,
[15]
,
[16]
. However, slow convergence occurs because of lowfrequency periodic behavior in the lower order Σ–Δ DPWM This behavior is also known as idletone, which produces lowfrequency noise in the power stage
[9]
. An idletone detection function is presented to detect the idletone sensitive binary word
d_{c}
[
n
] (refer to
Fig. 1
). The results of preverification ensure an idletone free Σ–Δ DPWM.
An IC controller implements the proposed trimode control strategy for buck converter with the use of a topmanagement finite state machine. Flexibility is achieved by integrating PID and robust RST control to reject load current variations. The proposed DPWM is also integrated onto the chip. The experimental results show that the trimode compensator with idletone free DPWM demonstrates the effective power consumption model of the digital controller. This model can estimate digital controller power consumption and even determine the effect on PwrSoC power efficiency for a given output power as switching frequency is increased.
This paper is organized as follows: Section 2 provides details on the proposed trimode digital control. Section 3 describes an idletone free Σ–Δ DPWM. Section 4 discusses the experimental results on the IC controller. Section 5 concludes the study.
II. TRIMODE DIGITAL CONTROL
PwrSoC requires a highperformance digital compensator with low power consumption. Therefore, a trimode controller is proposed to minimize power consumption during controller operation in the steadystate and standby modes. This controller also achieves efficient dynamic response when external load features are transient. PID control and robust RST control are adopted to realize trimode control.
 A. PID Control
A discretetime PID controller can be written as
where
d
[
n
] is the PWM output discrete value;
e
[
n
] is the error signal discrete value between reference voltage
V_{ref}
and regulated output
V_{o}
;
d
[
n  i
] and
e
[
n  i
] are respectively the PWM output and error values at
i
^{th}
cycles prior to the current cycle; and
a
_{1}
,
a
_{2}
,
b
_{0}
,
b
_{1}
, and
b
_{2}
are control parameters determined by a pole assignment method.
 B. Robust RST Control
Compared with PID control, robust RST control enables the consideration of different dynamics for reference tracking and disturbance rejection. An RST controller achieves significant output disturbance rejection while maintaining satisfactory robustness. The structure of an RSTcontrolled buck converter system is presented in
Fig. 2
.
If In transfer function
,
B
(
z
) and
A
(
z
) are polynomials. This function describes the discrete time switchedmode power supply (SMPS) model. Thus, the sensitivity function can be expressed as
The same denominator in (2) can determine closedloop poles. Knowledge of acceptable disturbances leads to designing RST control in terms of pole and zero assignments. Some fixed parts can be specified for polynomials
S(z)
and
R(z)
. For example, a pole for
z
=1 in
S(z)
is needed for static error elimination to ensure output accuracy. Closedloop poles are chosen to filter effects in certain frequency regions or improve robustness of the closedloop system. For output disturbance at pulsation
ω_{c}
(output filter corner frequency), efficient disturbance attenuation is achieved when
S_{yy}
gain is reduced. However, we observed that a large attenuation of
S_{yy}
at
ω_{c}
results in a large area of
S_{yy}
over zero value, which increases the maximum value of
S_{yy}
. Given that the maximum value of
S_{yy}
is inversely proportional to the modulus margin Δ
M
, large output noise rejection degrades robustness.
Fig. 3
describes the aforementioned sensitivity functions of a robust RST controller. The gain of
S_{yy}
at
ω_{c}
(15 KHz) is 41 dB.
The robust RST control can be written as:
where
d
[
n
] ,
w
[
n
] , and
y
[
n
] are PWM output discrete value, reference voltage
V_{ref}
, and regulated output
V_{o}
;
d
[
n  i
] ,
w
[
n  i
] , and
y
[
n  i
] are corresponding values at the
i
^{th}
cycles prior to the current cycle; and
t
_{0}
,
t
_{1}
,
t
_{2}
,
t
_{3}
,
r
_{0}
,
r
_{1}
,
r
_{2}
,
s
_{1}
, and
s
_{2}
are optimized control parameters.
Block diagram of an RST scheme.
Sensitivity function of a robust RST controller.
 C. Comparative study of PID Control and RST Control
A fixedpoint simulation is performed in Matlab by using a nonideal buck converter model written in Sfunction. All circuit parameters have the same values as the values on the test board. Default switching frequency is 2MHz
f_{s}
= , filter inductor is
L
= 4.7μH , filter capacitor is
C
= 22μF , and nominal load is
R_{L}
= 5Ω .
Fig. 4
presents the outputtooutput sensitivity function in the frequency domain for RST control and PID control to quantify control dynamics, robustness, and output noise (load variation) rejection properties.
The gain of
S_{yy}
at corner frequency 13KHz
f_{c}
= determines output disturbance rejection in the SMPS test vehicle used in the experiment. Low
S_{yy}
gain (13 KHz) equates to efficient output disturbance attenuation. Moreover, the maximum value of
S_{yy}
corresponds to the inverse value of modulus margin Δ
M
; Δ
M
is the minimum distance of the openloop transfer function with respect to the critical locus (1) in the Nyquist plan.
The modulus margin quantifies robustness with respect to modeling uncertainties.
Fig. 4
shows that
S_{yy}
gain at 13 KHz for RST control is 41 dB, whereas that for PID control is 20 dB. PID and RST exhibit similar robustness (Δ
M_{RST}
=0.88, Δ
M_{PID}
=0.87).
S_{yy} sensitivity function for RST control and PID control.
Simulation of RST control and PID control in a load transient from 0.3 A to 0.45 A.
Based on the aforementioned testbench, a closedloop fixedpoint simulation is performed to compare the performances of the two compensators.
Fig. 5
shows the simulation performance results of RST control and PID control in a load transient (0.3 A to 0.45 A) to ensure continuous conduction mode (CCM) operation. Load transient response of RST control is superior to that of PID control; RST control offers shorter rise time and produces smaller undershoot.
 D. TriMode Compensator Operation
A comparative study shows that RST control exhibits better dynamic behavior against load variation than PID control under similar robustness with respect to modeling uncertainties. However, RST control requires a complex implementation of extra combinational cells across the datapath according to (1) and (3). The primary task of a compensator is to maintain a stable output voltage in an acceptable error range when the buck converter operates in steadystate (i.e., the external load is stable). Thus , a simple control law, such as PID control, is preferable for control performance. Moreover, using PID control during steadystate satisfies performance specification and relaxes the tight algorithm computation requirement, further reducing power consumption.
Many portable devices are in idle state (i.e., standby mode). Thus, quarter PID control is proposed. Quarter PID control and PID control have the same structure when applied under normal operations, but quarter PID control is clocked at a quarter of the switching frequency. That is, quarter PID control updates its computation every four periods.
The proposed trimode compensator in
Fig. 6
consists of a mode arbitration logic that switches among three modes: robust RST control for the transient mode, PID control for the steadystate mode, and quarter PID control for the standby mode. The trimode compensator depends on an external activity signal
m
, which is normally obtained by a sensor to select an appropriate mode. Digital functions inside any lowpowered system can issue such a signal. For example, the activity signal in a mobile phone is set to
m
=0 when in standby mode and
m
=1 when in normal operation. Change among the three states is performed through mode arbitration logic. The block function detects the activity signal state and selects the corresponding control mode. The trimode control (
Fig. 7
) is designed to eliminate potential stability problems related to dynamic mode switching between different control modes. The mode change procedure is detailed in
Fig. 8
. Tuning times Δ
t
_{1}
and Δ
t
_{2}
in RST control can be adjusted to satisfy practical application needs during the transient state. These two tuning times can be implemented using two ladders of Dflipflops arbitrated by activity signal
m
(
Fig. 6
). For example, constant tuning time
t
_{tune1}
is set for Δ
t
_{1}
and
t
_{tune2}
for Δ
t
_{2}
. Voltage error
e
[
n
] obtained from reference voltage
V_{ref}
[
n
] and regulated output
V_{o}
[
n
] is normalized in the discretetime format; the maximum allowed voltage error is set as threshold
e_{th}
. In the experimental testbench,
e_{th}
is set to 15 mV (1% of the nominal output voltage).
Fig. 6
shows that
e_{th}
is compared with current error signal
e
[
n
] .
Fig. 7
and
8
shows that logicglue ensures correct functions and timing sequences to enable the two controls. A frequency divider provides a quarter in the system clock of PID control in standby mode. Detailed operation of the trimode compensator is described as follows:
Block diagram of trimode controller.
Stateswitch diagram of mode arbitration block.
Mode change procedure of trimode controller.
1) After initialization of SMPS, the compensator is assumed to be in standby mode and quarter PID is used to regulate output voltage; the compensator is kept in this state until output variation is larger than error threshold (i.e.,
e
[
n
] >
e_{th}
(normalization) or an activity signal
m
=1 is detected). Then, the compensator switches to procedure 2;
2) The compensator switches to transient mode using the RST control law to regulate output voltage of SMPS. This control mode is maintained long enough ( Δ
t
_{1}
>
t
_{tune1}
) to achieve
e
[
n
] <
e_{th}
; SMPS then enters a steadystate mode;
3) The compensator selects PID control in steadystate mode to regulate output voltage. This state is maintained until output variation is larger than error threshold (i.e.,
e
[
n
] >
e_{th}
or an activity signal
m
=0 is detected);
4) RST control is selected again for regulating unloading in the transient mode. This control mode is held long enough ( Δ
t
_{2}
>
t
_{tune2}
) until
e
[
n
] <
e_{th}
is achieved. Unloading is then finished, and SMPS once again reaches steadystate mode;
5) The controller stays in an unloaded situation after the transient mode and is set in standby mode; then, the controller is back to procedure 1 to wait for the next operation cycle.
Compared with the dualmode controller designed with a simple hysteretic logic method, the proposed controller offers a more flexible selection to reduce the energy consumption of the control algorithm with three modes. With the trimode controller, quarter PID control updates the whole controllaw computation undersampled mode at 1／(4·
f_{s}
) frequency. This feature reduces energy consumption relative to standalone PID and RST controllers.
 E. Stability During Mode Change
According to (1) and (3), current period control output
d
[
n
] is derived on the basis of the state variables in previous cycles. For example, PID controller requires state variables from at least two cycles prior to the current period. If no operation overlap in the time domain is found, then the controller generates a large offset in the first period after mode change. A prepostoperation in transient mode is proposed during mode change to overcome this difficulty.
Fig. 8
shows that robust RST control is next to any adjacent control. For example, RST control operation can manually extend to quarter PID control interval when the mode changes from standby to transient. This extension should be long enough to set up a stable closedloop RST control response. Hence, RST control can be regarded as preoperation. By contrast, RST control extends to PID interval to perform postoperation when the mode changes from transient to steadystate. In the second situation, several periods during the mode change are sacrificed to avoid potential instability. Therefore, two overlaps requiring only small modifications to hardware configuration are suggested (
Fig. 6
):
1) Extend tuning time Δ
t
_{1}
and Δ
t
_{2}
to Δ
T
_{1}
and Δ
T
_{2}
respectively, according to the experimental results satisfying the stability criterion during mode change;
2) Permit two controls to operate simultaneously;
3) Add another arbitrary module to select the Mux output in the used controllers block (
Fig. 6
) following the timing sequence discussed above.
The trimode controller offers a flexible selection with the three modes for saving power consumption. With the trimode controller, quarter PID control updates the whole controllaw computation in standby mode at a switching frequency of
f_{s}
／4 . This feature reduces power consumption, compared with standalone PID or RST controllers.
III. SPURTONE FREE CONDITION FOR Σ–Δ DPWM
The proposed trimode controller output must be converted to a PWM pattern for further use. This section proposes an effective guideline to design a Σ–Δ DPWM, achieving efficient performance and maintaining acceptable power consumption.
The errorfeedback model of Σ–Δ modulator is preferable if DPWM is the design target. The corresponding transfer function is given by:
where
D
(
z
) is the input signal. The error
E
(
z
) is the difference between range limited input and quantization block
V
(
z
) output.
E
(
z
) is then compared with input voltage by using the delay module
H_{e}
(
z
) ; and
STF
and
NTF
are the signal transfer function and noise transfer function, respectively. The delay module is easily set to achieve different orders of noiseshaping effects. For example,
H_{e}
=
z
^{1}
assures a firstorder noiseshaping effect, whereas
H_{e}
=
z
^{1}
(2+
z
^{1}
) assures a secondorder noiseshaping effect.
Power converter output regulated by Σ–Δ DPWM of different orders.
A fixedpoint simulation model is used to interpret the higher order DPWM advantage; the same parameters as illustrated in Section 2.3 are used. For example, input binary word in decimal format is 1025 using an 11bit DPWM with 5bit Σ–Δ modulator.
Fig. 9
shows power converter output regulated by a Σ–Δ DPWM with corresponding orders, as well as by an ideal 11bit DPWM. Compared with higher order Σ–Δ DPWM, regulated power converter output with firstorder DPWM exhibits obvious periodic oscillation. This phenomenon is reduced by the second and thirdorder modulators. Therefore, corresponding oscillation amplitude is reduced with increased Σ–Δ order.
With consideration of the filter response in the power stage, the total noise power of each input binary word is defined as the accumulation of power differences between target modulators and references within half of the switching frequency. Thus, an ideal 11bit DPWM is simulated to provide a reference.
Fig. 10
shows the simulation results of inband quantization noise power versus input binary word.
Fig. 10
(a) shows three floors exhibiting two types of inband noise. The central floor is an effective input binary word range floor, constant and symmetrical to the central binary word (1024 in this case). All input under this floor achieves better noiseshaping effects than input on other floors. The other two floors are placed at two ends of the binary word sweep range; hence, they are referred to as “side floors.” These floors exhibit weaker noiseshaping effects than the central floor. The following reasons explain the phenomenon:
1) Small enough or large enough input binary words are prone to introducing saturation into the modulator, which results in repeated lowfrequency patterns that appear in converter output;
2) Compared with Σ–Δ a digitaltoanalog converter, imperfect lowpass filter in the power stage (secondorder for buck converter) deteriorates postanalog filter performance and introduces more serious inband noise, especially in the side floors;
3) Inband noise has higher amplitude in firstorder DPWM than in secondorder DPWM, which accounts for the pattern scattering effect.
Fig. 10
(b) enlarges the central floor around the central input binary word (from 1015 to 1065), showing that noise peak power always occurs at:
where
n
is input bit number,
m
is output bit number,
I
∈
Z
^{+}
and
q_{th}
≤
I
≤2
^{m}

q_{th}
.
q_{th}
is threshold absolute value in the central floor.
Fig. 10
shows a confidence interval obtained from the testbench. The example requires one side floor length to be at least 12.5% of the total length of input binary word range (
q_{th}
≥ 8 ).
The minimum noiseshaping effect can be achieved for all modulators with different orders, provided that input binary word is maintained at
I
· 2
^{nm}
. All modulators generate the same output pattern without the sensitive periodic sequence. For example, modulated output of all modulators with different orders for input binary word 992 is the same output sequence as {31, 31, ... 31}.
Based on the above analysis, a recommended Σ–Δ DPWM design guideline is given as follows:
1) reduce the use of the Σ–Δ modulator to generate higher frequency periodical sequences that are likely to be eliminated by the power filter;
2) A higher order modulator is always preferable to attenuate the idletone effect using inherent intensive scatter operations;
3) The estimation in (5) should be performed offline to determine idletone sensitive binary words. Corresponding regulated output should not fall into the set of sensitive output.
We use a secondorder 5bit Σ–Δ DPWM to achieve a satisfactory tradeoff between the required system clock and output signal integrity. Nominal DC–DC converter output voltage (1.5V) is normalized as:
which satisfies the proposed guideline.
(a) Inband quantization noise power versus input binary word of firstorder and secondorder modulators in the buck converter, (b) periodic noise peak around a specific input.
IV. EXPERIMENTAL RESULTS AND POWER CONSUMPTION ANALYSIS
 A. Experimental Results
The proposed trimode digital controller is fabricated in a 0.35 μm CMOS process.
Fig. 11
shows the chip die photo. The whole chip occupies 4.58 mm × 2.42 mm; RST compensator takes 1.28 mm × 1.31 mm, PID compensator (with embedded DPWM) takes 1.24 mm × 1.27 mm, and standalone DPWM takes 0.47 mm × 0.49 mm.
Table I
summarizes the testbench specification. A Xilinx XC3S500E FPGA board is used as a motherboard to provide necessary control signals and implement the offchip mode arbitration function.
Die photo of proposed controller.
DESIGN SPECIFICATION OF THE TESTBENCH
DESIGN SPECIFICATION OF THE TESTBENCH
Output voltage of trimode controller at 2 MHz under load transient from 0.3 A to 0.45 A to keep in CCM operation (50 mV/div, 40 μs/div, AC coupling).
Fig. 12
shows the response using the trimode controller under the load perturbation scheme in
Fig. 8
.
Fig. 12
describes step 1 to step 3 in Section 2.4 when load current changes from 0.3 A to 0.45 A.
t
_{tune1}
and
t
_{tune2}
are both set to 40 μs to ensure sufficient transient response time according to the dynamic performance of the RST controller.
e_{th}
is set to
. According to
Fig. 12
, the trimode controller exhibits better dynamic response (153 μs and 200 μs, respectively) than the standalone PID controller; however, although the trimode controller takes a longer response time than the standalone RST controller. Maximum output voltage ripple is 1.8 mV. Power consumption of the trimode controller is anticipated to be lower than the standalone RST controller or the fullspeed standalone PID controller; this issue is discussed in the next section.
 B. Power Consumption Analysis of Proposed Controller
The aforementioned test illustrates the acceptable static and dynamic performances of the proposed trimode controller with the idletone free DPWM. Power consumption is another important assessment parameter influencing overall converter efficiency. The same testbench is used to perform an experiment illustrating actual power consumption.
t
_{tune1}
and
t
_{tune2}
are maintained at 40 μs. A parameter
λ_{m}
represents the time ratio of nonstandby operation mode, that is, the total time of transient mode and steadystate mode.
Fig. 13
shows the experimental power consumption of the proposed trimode controller with time ratio
λ_{m}
being 0.3, 0.5, and 0.7. The standalone PID controller and the RST controller are also shown for comparison purposes. We take
λ_{m}
=0.5 as an example, which is half the operation time before it falls in standby mode. The power consumption of the trimode controller is only 64.5% of that of the PID controller and 34.2% of that of the RST controller at switching frequency of 2 MHz. That is, the power consumption is 32.15 mW/MHz with a supply voltage
V_{dd}
=3.3 V and output voltage
V_{o}
=1.5 V.
λ_{m}
=0.3 and
λ_{m}
=0.7 result in a power consumption of 24.56 mW/MHz and 42.83 mW/MHz, respectively.
Power consumption of proposed trimode controller compared with standalone PID and RST controllers under SMPS switching frequency.
Anticipated output power versus switching frequency of a buck converter; the trimode controller controls the buck converter with switching frequency from 10 kHz to 10 MHz.
If the power consumption of 24.56 mW/MHz corresponding to
λ_{m}
=0.3 is taken as an example, an SMPS output power range can be evaluated when a given efficiency is targeted. Output power is ideally given by
where
P_{out}
is the estimated output power,
P_{loss}
is the total amount of dissipated power consumption (including power loss from controllers, drivers, and power switches), and
η
is the normalized power efficiency. According to the conclusion of
[17]
, we assume that digital controller power loss does not account for more than 8% of the total power loss (i.e.,
P_{loss}
=307 mW/MHz).
Fig. 14
shows the estimated SMPS output power
P_{out}
with respect to switching frequency and different global power efficiency targets (
η
=95%, 90%, 85%, and 80%).
V. CONCLUSIONS
This study introduces a fully digital IC controller for a lowpower, highswitchingfrequency buck converter. This controller takes advantage of a proposed idletone free Σ–Δ DPWM and trimode compensator. The improved DPWM effectively reduces generating idletone. An offline parameter calculation guarantees that no hardware resources are required in ASIC. The proposed trimode controller addresses transient, steadystate, and standby modes by considering power consumption and dynamic performance. The experimental results verify the efficiency of this systemlevel power saving strategy. Power consumption is only 24.56 mW/MHz when the time ratio of nonstandby operation mode is 0.3. The IC prototype is accurate and flexible, achieving high power efficiency for lowtomedium power applications.
Acknowledgements
This study is supported by the “Program projects of Beijing Municipal Education Commission (SQKM201411417006)” and “The Importation and Development of HighCaliber Talents Project of Beijing Municipal Institutions (IDHT 201304074).”
BIO
Limei Xiu was born in China in 1983. She received her B.S. and M.S. degrees from the School of Electronic and Information Engineering of Beijing Jiaotong University, Beijing, China, in 2006 and 2008, respectively. She is currently a Ph.D. student in Beijing Institute of Technology and a lecturer in the College of Information Technology, Beijing Union University, Beijing, China. Her current research interests include power electronics and control, as well as lowpower mixedsignal IC design.
Weiping Zhang was born in China in 1957. He received his B.S., M.S., and Ph.D. degrees in 1982, 1987, and 1998, respectively. From 2000 to 2001, he was a visiting professor in University of Virginia in the United States and the National Center for Power Electronics. He is currently a professor in North China University of Technology. His current research interests include electronic ballast for highintensity discharge lamps, resonant converter, and piezoelectric transformer converter.
Bo Li was born in China in 1982. He received his Ph.D. degree in Engineering from the Institute National des Sciences Appliquees de Lyon (INSA Lyon), Lyon, France, in 2012. Since 2012, he has been an Assistant Researcher with the Institute of Microelectronics of Chinese Academy of Sciences (IMECAS). His current research interests include digital control techniques applied to highfrequency switchedmode power supply and antiradiation mixedsignal IC design.
Yuansheng Liu was born in China in 1973. He received his B.S. and M.S. degrees from the School of Electronic and Information Engineering of Beijing Jiaotong University, Beijing, China, in 1996 and 2003, respectively. From 1996 to 2008, he was a teacher in Beijing Jiaotong University. He is currently an Assistant Professor with the College of Information Technology, Beijing Union University, Beijing, China. His current research interests include digitalsignalprocessingbased control applications.
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