This study presents an input filter resonance mitigation method for an AC–DC matrix converter. This method combines the advantages of the onecycle control strategy and the active damping technique. Unnecessary sensors are removed, and system cost is reduced by employing the gridside input currents as feedback to damp out LC resonance. A model that includes the proposed method and the input filter is established with consideration of the delay caused by the actual controller. A zeropole map is employed to analyze model stability and to investigate virtual resistor parameter design principles. Based on a double closedloop control scheme, the onecycle control strategy does not require any complex modulation index control. Thus, this strategy can be more easily implemented than traditional space vectorbased methods. Experimental results demonstrate the veracity of theoretical analysis and the feasibility of the proposed approach.
I. INTRODUCTION
The AC–DC matrix converter (AC–DC MC) is a novel and generalized power converter topology derived from a threephase matrix converter (MC). AC–DC MC has the following significant advantages
[1]
,
[2]
:

1) compact design and high reliability because of the absence of bulky energy storage components

2) generation of DC output voltage with arbitrary amplitude and polarity

3) sinusoidal input current with controllable input power factor

4) operation in all four torquespeed plane quadrants because of regenerative capability
These desirable characteristics make the AC–DC MC an ideal future solution for AC–DC power conversion applications.
An inductor–capacitor filter is always required at the input side of AC–DC MC. The filter capacitor reduces the highfrequency current harmonics caused by the switching operation and the inductive nature of the ACline. The filter inductor suppresses the loworder harmonics from the power source. However, the LC filter, which has no energy storage, causes instability during operation and even results in severe system failure
[3]
,
[4]
. The inherent resonance figure of the slightly damped LC filter mainly causes this issue. Resonance is easily excited by the harmonic pollution in the power source or the harmonic components in the input currents drawn by the AC–DC MC itself. The resonance problem has traditionally been considered at the design stage, in which the appropriate filter parameters are selected to tune the resonance frequency away from the potential harmonic frequency. However, this method limits performance because resonance frequency is related to source inductance, which usually varies with power source conditions. Adding a physical damping resistor into the filter to mitigate resonance is another classical, straightforward, and widely implemented method
[5]
. However, this resistor results in additional power loss, especially in highpower applications.
The active damping (AD) method improves input current quality and enhances system stability without changing the power converter topology or affecting its efficiency. The AD method simulates a fictitious damping resistor connected in parallel with the filter capacitor. The harmonic current results are then forced through this resistor from the resonance flow to suppress the resonance. In
[6]

[9]
, the authors used capacitor voltages as feedback to determine the harmonic current and successfully mitigate resonance in threephase current source rectifiers (CSRs). In
[10]
, the feedback signal changed to inductor current to remove additional capacitor voltage sensors. The classical space vector modulation (SVM) strategy controls the CSRs in most of these schemes. To synthesize the harmonic current, a new modulation index is obtained as an input current function that is normalized to output current. These procedures include complex space vector angle and modulation ratio calculations, which increase the software complexity. Therefore, developing an appropriate modulation and control strategy is key to the easy implementation of the AD method in practical applications.
A variety of pulse–width–modulation (PWM) switching techniques has been developed for AC–DC MC on the basis of two different approaches.
The first approach is the direct transfer function method proposed by Donald and Thomas
[1]
. This method requires the controller to perform cumbersome calculations per switching period to define all six elements in the transfer matrix. This method increases complexity while reducing practicability and reliability. Consequently, this method is preferred for theoretical analysis rather than realtime implementation.
The second approach is the SVM strategy
[11]
,
[12]
, which is similar to that used by CSRs. This method is a wellknown and wellestablished modulation strategy because of its high performance, relative simplicity, and inherent capability to achieve full control of both output voltage and input power factor. Nevertheless, this method is inappropriate for the AD strategy as aforementioned.
Aside from linear techniques, modern control algorithms have recently been reported for the current and torque control of AC and DC machines by using MC or AC–DC MC; these control algorithms include predictive current control (PCC)
[13]
,
[14]
, predictive torque control
[14]
, and sliding mode variable structure control
[16]
. In
[13]
, a PCC method with active damping was proposed for MC to reduce software complexity because PCC control does not use modulation index variables. However, this method is highly sensitive to parameters and load variations. Moreover, the unfixed switching frequency makes the design of input and output filters difficult.
We introduce a new nonlinear control strategy called onecycle control (OCC)
[17]
into the AC–DC MC system. Compared with traditional modulation approaches, the OCC control strategy features fast dynamic response, excellent power source perturbation rejection, strong robustness, and automatic switching error correction. Similar to the PCC method, this strategy also discards explicit modulation index control. These characteristics imply that the proposed control scheme exhibits a simple circuit, high performance, low cost, high stability, and easy implementation.
This paper is organized as follows: Section II investigates the inductor current feedback AD method and its stability with consideration of the time delay caused by the actual controller. Section III explains the modification to the OCC controller to include AD. Section IV discusses the damping resistance selection principles. Section V presents the experimental results. Section VI draws in the conclusions.
II. ACTIVE DAMPING APPROACH FOR AC–DC MC
 A. Active Damping Approach
Power topology of AC–DC MC.
Fig. 1
shows the converter topology of AC–DC MC, which consists of a threephase voltage source indicated as
u
_{s}
, a switching matrix composed of six bidirectional switches S
_{1}
to S
_{6}
, an input LC filter, and an output inductive load. Assuming that the AD method is not included, the virtual resistive damper
R
_{d}
in
Fig. 1
is temporarily neglected. The input filter is modeled as
where
L
_{i}
and
C
_{i}
represent the filter capacitor and filter inductor, respectively;
u
_{s}
=[
u
_{a}
u
_{b}
u
_{c}
]
^{T}
and
i
_{s}
=[
i
_{a}
i
_{b}
i
_{c}
]
^{T}
represent the gridside voltage vector and current vector, respectively; and
u
_{i}
=[
u
_{ia}
u
_{ib}
u
_{ic}
]
^{T}
and
i
_{i}
=[
i
_{ia}
i
_{ib}
i
_{ic}
]
^{T}
represent the inputside voltage vector and current vector, respectively. If
u
_{s}
and
i
_{i}
are taken as input variables and
u
_{i}
and
i
_{s}
as output variables, then (1) and (2) can be transformed into the Laplace domain as
From (3) and (4), the LC filter may amplify the harmonic components in the voltage source
u
_{s}
or in the input current
i
_{i}
, which results in severe oscillations in
u
_{i}
and
i
_{s}
when the LC filter is tuned to one of the harmonics.
The AD approach emulates a virtual damping resistor
R
_{d}
in parallel with the filter capacitor
C
_{i}
, as shown in
Fig. 1
. When
R
_{d}
is considered, Equation (2) should be modified as
The damping resistance
R
_{d}
does not physically exist in practical circuits. Therefore, the converter extracts the
R
_{d}
current indicated by
i
_{R}
in (5).
R
_{d}
is proportional to the capacitor voltage.
Active damping aims to mitigate the system harmonics rather than the fundamental component. Thus, only harmonic capacitor voltage should be considered when calculating the damping current
i
_{R}
. Therefore, input voltage is transformed into the
dq
reference frame. In this frame, the fundamental component of the capacitor voltage vector
is the DC component, which can be easily deleted by a digital DCblocker
[18]
or a highpass filter
[19]
. Remaining AC components correspond to all harmonics present in
where
is the digital DCblocker transfer function in the Laplace domain,
a
is the parameter, and
T
_{s}
is the sampling period.
Once the input voltage harmonics in Laplace domain
have been obtained, harmonic damping currents
are determined by combining (6) and (7), as indicated by
From (9), three voltage sensors have to be set up in the practical circuit to feedback the instantaneous value of input voltage
u
_{i}
. These sensors are redundant because other algorithms do not use input voltage information.
Two sets of sensors are essential for AC–DC MC input side: one is gridside current sensor
i
_{s}
, used for overcurrent protection, and the other is gridside voltage sensor
u
_{s}
, used for overvoltage protection and voltagebased commutation. So as to reduce the system cost and enhance the reliability,
u
_{s}
and
i
_{s}
are utilized to estimate input voltage
u
_{i}
.
According to (1), we can write
Substituting (10) into (9), we obtain
where
ω
_{i}
is the power source angular frequency, and
is the digital derivation transfer function.
From (11), the current throughout of
R
_{d}
is determined as a linear combination of three individual fractions.
The resulting output of the first fraction is proportional to the power source harmonics. The practical source voltages are always slightly harmonicpolluted, thus causing a few AC components in
to pass the digital DCblocker. However, the magnitudes of these components are small in the lowfrequency stage, such that their influence on
is negligible.
The damping current gain 1/
R
_{d}
, filter inductor
L
_{i}
, digital DCblocker dynamic, digital deviation dynamic, and gridside current in
dq
reference frame comprise the second part of (11). After digital deviation, the remaining part of
contains only AC components. The effect of the DCblocker on these signals is negligible. Therefore, the transfer function of this fraction is simplified to
where the digital DCblocker dynamic is omitted.
The third fraction contains crosscoupling terms related to the AC signals in
. The gain margin of this fraction is smaller compared with the second fraction.
The second fraction is dominant in (11) in the final results. Therefore, the other two fractions were ignored to reduce calculation difficulty. The resulting simplified algorithm scheme is shown in
Fig. 2
.
Algorithm scheme of the AD strategy.
 B. Stability Analysis of the Proposed Active Damping Method
In practical implementation, the controller realized by a digital signal processor (DSP) needs a finite calculation time for signal sampling, damping current
calculation, and modulation strategy implementation. These processes cause time delay, which reduces the gain and phase margins, deteriorates the performance, and affects control loop stability. The total control and modulation delay is approximated from the effective switching frequency. Time delay is equivalent to one switching period for the OCC control technique used. Half of the time is used for analog–digital sampling, whereas the other half is used to execute the AD method and OCC algorithm.
Model of the AD closedloop control system.
Stability analysis with different R_{d} values: (a) Bode map and (b) zeropole map.
The smallsignal model of the closedloop AD system is approximated by using filter impedance, the dynamic of the AD method, and total time delay, as shown in
Fig. 3
.
The Bode and zeropole maps of the closedloop control system are plotted in
Fig. 4
with different AD resistance
R
_{d}
values. For example, a filter resonance frequency of 805 Hz (
L
_{i}
=3mH,
C
_{i}
=13uF) and a switching frequency of 12 kHz is used.
Fig. 4
(a) shows that the crest in the frequency response curve becomes flat when AD resistance decreases. Therefore, a small resistance value equates to a desirable effect in mitigating resonance and reducing filter sensitivity to resonance frequency. However, the AD loop gain margin is inversely proportional to damping resistance. When damping resistance is smaller than the minimum value, the gain margin becomes extremely high and the system becomes unstable. The minimum damping resistance value for filter parameters used in this study (i.e.,
L
_{i}
=3 mH and
C
_{i}
=13 μF) is 12 Ω.
III. ONECYCLE CONTROL STRATEGY FOR AC–DC MC
 A. Principle of Onecycle Control Strategy
The OCC control strategy aims to adjust the duty ratio of the switching device and force the controlled variable to follow the control reference during one switching cycle. The topology of a simplified DC–DC chopper illustrated in
Fig. 5
a explains the basic operational principle of the OCC controller
[12]
,
[17]
.
Operational principle of the OCC control strategy: (a) topology of a simplified DC–DC chopper and (b) waveforms of input voltage, switching function, and output voltage.
In
Fig. 5
,
u
_{i}
(
t
) and
u
_{o}
(
t
) represent the input and output voltages of the DC–DC chopper. Let us assume that switching device
Q
is turned on during time interval
t
_{on}
and turned off during time interval
t
_{off}
, where
t
_{on}
+
t
_{off}
=
T
_{s}
. Switching function
S
(
t
) is as follows:
If the forward voltage drop of switching device
Q
is neglected and the switching frequency
f
_{s}
= 1/
T
_{s}
is assumed to be higher than input voltage
u
_{i}
(
t
), then the resulting output voltage
u
_{o}
(
t
) is a PWM pulse sequence with the same frequency and duty ratio as the switching function
S
(
t
) and the same envelop as input voltage
u
_{i}
(
t
). This condition is illustrated in
Fig. 5
b. Thus, the average value of
u
_{o}
(
t
) in one switching period can be obtained by
Nonlinear modulation is applied to switching device
Q
to force the integration of
u
_{o}
(
t
) in one switching period is equal to the integration of analog control reference
in one switching period
Substituting (15) into (14), we obtain
This technique to modulate and control switching device
Q
according to (16) is the onecycle control strategy. From (17), we conclude that the influence of input voltage
u
_{i}
(
t
) on output
u
_{o}
(
t
) is fully rejected and
u
_{o}
(
t
) is instantaneously controlled within one switching cycle. In other words, the OCC technique turns the original nonlinear switch device into a linear transferring path.
 B. Proposed Onecycle Control Strategy with Active Damping for AC–DC MC
Two control objectives are considered for the AC–DC MC: (1) voltage control on the output side of the converter and (2) unity displacement power factor operation on the input side of the converter. Based on the assumption that gridside voltage
u
_{s}
is purely sinusoidal and neglects power loss in switching devices and transmission lines, the following active power balance equation must be satisfied:
From (18), output voltage
U
_{o}
is related to input
d
axis current
because gridside
d
axis voltage
is a constant value (in this case). Thus, the first control objective is realized by adjusting
and the second control objective is obtained by minimizing input
q
axis current
.
The resulting control scheme is illustrated in
Fig. 6
. A PI controller realizes voltage regulation. The output is the main reference of input
d
axis current
, while the main reference of input
q
axis current
is 0 because of the demanded unity input power factor. The AD method is included in the proposed scheme through adding damping current
to
and
. Thus, the new input current reference is expressed as:
Control scheme of OCC strategy for AC–DC MC with AD.
The demanded phase currents in
abc
coordinates are obtained by applying this transformation equation:
According to the zerocrossing point of each demanded phase current, each input current cycle is evenly divided into six sectors to realize OCC control (
Fig. 7
).
Demanded phase currents and corresponding sectors.
Sector number
N
is determined by:
where
The input phase, whose current direction is opposite the other two phases, is the dominant phase in each sector. The other two input phases are auxiliary phases; the products of the absolute values of their corresponding demanded phase currents and switching period
T
_{s}
are current references indicated by
in
Fig. 6
. The OCC controller instantaneously compares the current references with the integrated output current to determine duty ratios. Resulting switching signals
S
_{α}
,
S
_{β}
, and
S
_{0}
are distributed to proper bidirectional switches in accordance with the sector number.
Without loss of generality, assuming demanded input currents are in sector 1, DC output polarity is positive and output inductor is large enough to guarantee continuous and constant output current. In this example, the dominant phase is input phase
α
and current references
are
respectively. The bidirectional switch S
_{1}
is kept on in the entire region to provide a path for the output current flowing from the power source to the DC load. Switches S
_{3}
and S
_{5}
are kept off to avoid input short circuit; and S
_{2}
, S
_{4}
, and S
_{6}
in the lower bridge arm are turned on successively at following a switching frequency sequence (
Fig. 8
).
Switching sequence and integrator waveform in sector I.
1) At the beginning of each switching period, S
_{6}
is switched on, whereas S
_{2}
and S
_{4}
are switched off to enable the output current
I
_{o}
to flow back to input phase
c
. The resulting equivalent circuit is shown in
Fig. 9
(a). The OCC controller integrates the output current and compares the result of
i
_{inte}
to the current reference
in this example, until the two values equal each other at time instance
t
_{α}
.
2) S
_{4}
is switched on, whereas S
_{6}
is switched off to commutate the load current from input phase
c
to input phase
b
, as shown in
Fig. 9
(b). The integrator is reset to zero at the same time and repeat the first integration procedure with current reference changed to
. Consequently, integration result
i
_{inte}
reaches current reference
at time instance
t
_{β}
.
Equivalent circuit of AC–DC MC in sector I.
3) Finally, only S
_{2}
is switched on in the lower bridge arm. The yielding equivalent circuit is illustrated in
Fig. 9
(c). Doing so totally disconnects the input and output sides, such that no power is transmitted from the source to the DC load. All three input currents, as well as the integrator, remains at zero from
t
_{β}
to the end of the switching cycle. S
_{1}
and S
_{2}
provide a freewheeling path for the output current to avoid a detrimental open circuit in the inductive load.
Hence, the average values of the input currents
i
_{ib}
and
i
_{ic}
in one switching cycle are respectively given by (23) and (24).
Based on the assumption that input threephase system is well balanced, the third input current
i
_{ia}
can be obtained by
From (23) to (25), input currents are controlled for reference tracking. Therefore, output voltage is effectively regulated, input power factor is unified, and the AD method is realized without any complex modulation index control. Moreover, only input currents with small absolute values are switched at high frequency; switches connected to the input phase with maximum current absolute value are kept on and off in the entire sector. Consequently, switching losses are greatly reduced.
Similarly, deriving current references and the switching signal distribution principle at the positive output voltage in other sectors can be derived in the same manner as shown in
Table I
.
CURRENT REFERENCES AND THE SWITCHING SIGNAL DISTRIBUTION PRINCIPLE OF THE OCC CONTROL STRATEGY WHEN OUTPUT VOLTAGE IS POSITIVE
CURRENT REFERENCES AND THE SWITCHING SIGNAL DISTRIBUTION PRINCIPLE OF THE OCC CONTROL STRATEGY WHEN OUTPUT VOLTAGE IS POSITIVE
IV. SELECTION OF ACTIVE DAMPING RESISTANCE
Effect of the saturation phenomenon.
A small value of AD resistance
R
_{d}
minimizes resonance peak as long as it is larger than the minimum value required for stability. However, limitations of the demanded phase currents also constrain
R
_{d}
choice. When output current approaches zero, large damping current
results from a small
R
_{d}
causes the demanded phase current
to exceed the maximum output current realizable value. In this situation, the required damping current is no longer realizable because of demanded phase current saturation. The saturation phenomenon also occurs when AC–DC MC produces maximum output voltage
U
_{o_max}
.
Fig. 10
shows an example of the saturation phenomenon, in which
is the maximum input current in the
d
axis and can be obtained as
Normally, damping current
contains only AC components and does not have any average value in the
d
 or
q
axis. Thus, introducing the AD method does not influence input active and reactive power. However, the damping current obtains a negative bias in the
d
axis under the aforementioned saturation conditions (
Fig. 9
). This deteriorates the input current waveform and causes undesirable interaction with the output voltage because of the distorted damping current.
Damping resistance greater than the minimum value required for stability should be considered to avoid the saturation phenomenon and allow for reasonable gain and phase margins. For the system in this study,
L
_{i}
=3 mH,
C
_{i}
=13 μF, and resonance frequency is 805 Hz; the recommended AD resistance is 25 Ω.
V. EXPERIMENTAL VERIFICATION
Fig. 11
shows the configuration of an experimental prototype built for hardware verification. The implementation setup consists of a control broad containing Texas Instruments TMS320F2812 DSP and a Xilinx XC9572XL complex programmable logic device (CPLD), an analog broad containing voltage and current sensors, and a power circuit realized by insulated gate bipolar transistors (IGBT).
Experimental configuration.
The power supply phase voltage is 60 V/50 Hz; output load is
R
=25 Ω; input filter parameters are
L
_{i}
=3 mH, and
C
_{i}
=13 μF; output inductor is 5 mH; switching frequency is 12 kHz; demanded output voltage
is 80 V, and damping resistance is 25 Ω.
ISR program flow chart of timer 2.
Experimental waveform of gridside input current and its FFT: (a) gridside phase current and voltage; (b) FFT of i_{a} without the AD method; and (c) FFT of i_{a} with the AD method.
The DSP carries out the proposed control strategy by timer 1 and timer 2 in the event manager A module. Timing periods of the two timers are set to 1/12000s and 1/120000s, respectively. The interrupt service routine (ISR) of timer 1 is programmed to calculate demanded phase current
according to measurements of practical input and output voltages and currents, as well as to determine the sector number and current references
. Timer 2 samples and integrates the output current to realize the OCC control of the input current.
Fig. 12
shows a program flow chart for this process. The obtained sector number
N
and switching signals
S
_{α}
,
S
_{β}
, and
S
_{0}
are outputted to CPLD for pulse distribution. CPLD also carries out the 4step commutation strategy [21]. The experimental results are shown in
Fig. 13
to
Fig. 15
.
Experimental results when demanded output voltage changes from 50V to 100V: (a) gridside phase current and voltage and (b) output current and voltage.
The system experimental results with and without AD control are given in
Fig. 13
. When AD control is disabled, the gridside current is highly distorted because of the input filter resonance frequency.
Fig. 13
(b) shows that the waveform contains 15
^{th}
and 17
^{th}
harmonics with magnitudes as high as 10% and 17% of the fundamental. When AD control is activated, the gridside current improves. This condition is reflected in the resulting sinusoidal waveform and its FFT spectrum, where oscillation is significantly suppressed and the THD value is reduced from 18.75% to 5.23%.
Experimental results when load resistor changes from 15 Ω to 25 Ω: (a) gridside phase current and voltage and (b) output current and voltage.
Fig. 14
and
Fig. 15
provide the dynamic response of the OCCcontrolled AC–DC matrix converter that always includes the AD method.
Fig. 14
shows that load resistance remains at 25 Ω and demanded output voltage
changes from 50 V to 100 V. Error between the reference and actual output voltage causes the demanded input phase current
to change. Practical input currents can track their references in one switching cycle with the OCC control. Therefore, the dynamic performance of AC – DC MC relies mainly on the PI controllerbased output voltage regulator. The experimental results show that output voltage reaches a new stable state in approximately 0.03 s.
Fig. 15
shows load resistance sharply changing from 15 Ω to 25 Ω, whereas output voltage reference keeps constant. Load changes accurately and immediately cause practical output voltage changes because of the AC–DC MC current source instinct; this disturbance is similar when demanded output voltage is changed.
Fig. 15
also shows that gridside and output currents reach their stable values smoothly in less than 0.01 s, whereas output voltage remains constant without any large oscillations in the transient process.
VI. CONCLUSIONS
Our research proposes a novel control scheme for AC–DC MC by taking advantage of the onecycle control strategy and the AD technique to mitigate input filter resonance. We developed the principle of the AD method and discussed the guidelines for selecting the damping resistance value. The AD method suppresses LC resonances caused by the power source or by the converter itself. Therefore, gridside current waveform quality is significantly improved. The OCC control strategy significantly simplifies AD method implementation because of its flexibility and the absence of complex and explicit modulation index control in the proposed scheme. Our experimental results verify these advantages, strengthening the attractiveness of AC–DC MC for future power converter applications.
BIO
Xiao Liu was born in Jinan, China, in 1985. He received his M.S. degree in Electrical Engineering and Automation from Shanghai Normal University, Shanghai, China, in 2010 and his Ph.D. degree in Power Electronics and Electric Drive from Shandong University, Jinan, China, in 2014. He is now a training lecturer at the State Grid of China Technology College, Jinan, China. His current research interests cover power electronics and control, which include ACDC matrix converter, DSPbased control applications, and renewable energy.
Qingfan Zhang was born in Jining, Shandong, China, in 1949. He is a Professor and Ph.D. supervisor in the School of Control Science and Engineering, Shandong University. He has been engaged in research and education in the areas of power electronics, electronic circuit design, and control systems.
Dianli Hou was born in Liaocheng, Shandong, China, in 1975. He received hid M.S. degree in Circuit and System from Nanjing University of Science and Technology, Nanjing, China, in 2004. Since 2010, he has been studying at Shandong University for his Ph.D. degree while serving as a teacher in the Department of Electronic and Electrical Engineering, Ludong University. He has been engaged in research and education in the areas of power electronics, electronic circuit design, and control systems.
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