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Interleaved ZVS DC/DC Converter with Balanced Input Capacitor Voltages for High-voltage Applications
Interleaved ZVS DC/DC Converter with Balanced Input Capacitor Voltages for High-voltage Applications
Journal of Power Electronics. 2014. Jul, 14(4): 661-670
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : February 18, 2014
  • Accepted : May 22, 2014
  • Published : July 28, 2014
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About the Authors
Bor-Ren Lin
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan
linbr@yuntech.edu.tw
Huann-Keng Chiang
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan
Shang-Lun Wang
Department of Electrical Engineering, National Yunlin University of Science and Technology, Yunlin, Taiwan

Abstract
A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulse-width modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For high-voltage applications, each circuit module includes two half-bridge legs that are connected in series to reduce switch voltage rating to V in /2. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for high-load-current applications, two center-tapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two half-bridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.
Keywords
I. INTRODUCTION
High-voltage converters have been studied and proposed for railway electrical systems [1] , ship electric power distribution systems [2] , and three-level medium power converters [3] - [5] . Three-level or multilevel converters/inverters [3] - [5] with clamped diodes, capacitors, or series H-bridge circuits have been proposed to reduce the voltage rating of power devices. To achieve compact size, high power density, and high circuit efficiency in modern power products, power switches with high switching frequency and low voltage rating can be adopted in medium-power converters. Thus, three-level converters can use MOSFETs to limit the voltage stress of power switches to V in /2. Compared with two-level converters, three-level converters have more circuit components and higher cost. However, power switches are operated in hard switching mode if converters have high switching frequency. This condition reduces circuit efficiency. Therefore, three-level converters with soft switching techniques [6] - [13] were developed to reduce the switching losses. Thus, all power switches can be switched on at zero current switching (ZCS) or zero voltage switching (ZVS) within the desired load range. The leakage inductance or external inductance of the transformer and the output capacitance of power switches are resonant at the transition interval. The drain-to-source voltage of MOSFETs can be decreased to zero voltage before MOSFETs are switched on. Therefore, if MOSFETs are switched on under ZVS, circuit efficiency is improved to achieve high switching frequency.
This study presents an interleaved soft switching DC/DC converter for high-voltage and medium-power applications. This converter is characterized by low switching loss, ZVS turn-on, and low voltage rating of MOSFETs. Two circuit modules are adopted, and the interleaved PWM scheme is used to share load current and reduce the ripple currents at input and output capacitors. Thus, the size of the input and output capacitors is reduced. In each circuit module, two input capacitors and two half-bridge converters are connected in series at the high voltage side to limit the voltage rating of MOSFETs to Vin /2. Therefore, power MOSFETs with 500 V voltage rating can be used in DC converters with 800 V input voltage. Two balance capacitors are connected in series between the AC sides of two half-bridge legs to balance two input split capacitor voltages automatically in each switching style. The primary windings of two transformers are connected in series to balance the secondary winding currents. Thus, power can be equally transferred to output load through two center-tapped rectifiers. Asymmetric PWM is adopted to generate the appropriate signals and regulate output voltage. MOSFETs can be switched on at ZVS within the desired load range on the basis of the resonant behavior of the MOSFET output capacitance and the transformer leakage inductance. The operation principle, circuit analysis, and design example of the proposed converter are discussed in detail. To verify the performance of the proposed converter, experiments are conducted with the use of a 1.8 kW prototype .
II. CIRCUIT CONFIGURATION
For a general single-phase AC/DC converter, the conventional half-bridge and full-bridge circuit topologies are adopted in the second stage DC/DC converter to regulate output voltage. The voltage stress of the power switches in these circuit topologies is set at DC input bus voltage V in . Power MOSFETs with 600 V voltage stress are normally adopted for half-bridge and full-bridge converters and are used after single-phase power factor correction (PFC). For three-phase AC/DC converters with PFC function, 900 V voltage stress MOSFETs or 1200 V IGBTs are adopted in the second stage DC/DC converter. The two half-bridge converters shown in Fig. 1 are connected in series at the high voltage side to reduce the voltage rating of power switches to V in /2. Meanwhile, these converters are connected in parallel at the low-voltage side to reduce the current rating of passive and active components. The main drawback of this circuit topology is that the two input split capacitor voltages can be unbalanced and thus result in unbalanced output inductor currents.
The circuit configuration of the proposed converter is shown in Fig. 2 . The DC bus voltage after three-phase PFC is normally within the range of 750 V to 800 V. Two input split capacitor voltages V Cdc1 and V Cdc2 can be automatically balanced by the clamped capacitors C c1 C c4 . The proposed DC/DC converter has two circuit modules that share the load current. The interleaved PWM with a 90-degree phase shift is adopted to generate the appropriate switching signals and regulate output voltage. Thus, the ripple currents at the input and output capacitors can be reduced. Each circuit module in the proposed converter has two half-bridge converters in series. For circuit module 1, the first half-bridge converter includes C dc1 , S 1 , S 2 , L r1 , T 1 , T 2 , C r1 , C r2 , C c1 , D 1 , D 2 , L o1 , and Co . The second half-bridge converter includes the components C dc2 , S 3 , S 4 , L r1 , T 1 , T 2 , C r3 , C r4 , C c2 , D 3 , D 4 , L o2 , and Co . V in and Vo are the input and output DC bus voltages, respectively. Co is the output capacitance, and Ro is the load resistance. C c1 C c4 are the DC blocking capacitances. C r1 C r8 are the output capacitances of MOSFETs S 1 S 8 , respectively. L r1 and L r2 are the resonant inductances, L m1 L m4 are the magnetizing inductances and L o1 L o4 are the output inductances of transformers T 1 T 4 , respectively. D 1 D 8 are the rectifier diodes. The asymmetric PWM scheme is used to control MOSFETs S 1 S 8 . S 1 and S 3 have the same PWM signals, whereas S 2 and S 4 have the same PWM waveforms. However, S 1 and S 2 complement each other with dead time to enable the ZVS operation. The gate signals of S 5 S 8 are phase-shifted by one-fourth of the switching period with respect to the gate signals of S 1 S 4 . Therefore, the inductor currents i Lr1 and i Lr2 are interleaved. C dc1 and C dc2 are input capacitors that split the input voltage ( V Cdc1 = V Cdc2 = V in /2). C c1 and C c2 are connected in series between AC terminals a and b to balance V Cdc1 and V Cdc2 automatically. For example, the voltage across C c1 and C c2 is equal to V Cdc1 if S 1 and S 3 are conducting while S 2 and S 4 are in the off-state. Meanwhile, the voltage across C c1 and C c2 is equal to V Cdc2 if S 1 and S 3 are in the off-state while S 2 and S 4 are conducting. Based on the on/off states of S 1 S 8 , two split capacitor voltages V Cdc1 = V Cdc2 = V in /2 and the voltage stress of S 1 S 8 are equal to V in /2. In the proposed converter, the primary windings of transformers T 1 and T 2 are connected in series to balance i Lo1 and i Lo2 automatically. In the same manner, the output inductor currents i Lo3 and i Lo4 are also balanced. If power is delivered through two balanced circuit modules, then the current rating of each output inductor is equal to Io /4.
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Circuit configuration of two series half-bridge converter for high-input-voltage and high-current applications.
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Circuit configuration of the proposed interleaved ZVS converter.
III. OPERATION PRINCIPLE
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Key waveforms in a switching cycle (a) circuit module 1 (b) the proposed converter.
The main PWM waveforms of circuit module 1 in the proposed converter are given in Fig. 3 (a). The duty cycle of S 1 and S 3 is δ , and that of S 2 and S 4 is 1- δ . The circuit modules are controlled by an interleaved PWM scheme. The gate signals of S 5 S 8 are phase-shifted by Ts /4 with respect to the gate signals of S 1 S 4 , respectively. Fig. 3 (b) shows the main waveforms of the proposed interleaved DC/DC converter. The following assumptions about the proposed converter are made to simplify the system analysis:
  • 1) TransformersT1–T4have the same magnetizing inductanceLmand turns ration;
  • 2) Power switchesS1–S8and rectifier diodesD1–D8are ideal;
  • 3) Resonant capacitancesCr1=..=Cr8=Cr;
  • 4) DC blocking capacitancesCc1=Cc2=Cc3=Cc4=Cc;
  • 5) Input split capacitancesCdc1=Cdc2;
  • 6) Output inductancesLo1=Lo2=Lo3=Lo4=Lo; and
  • 7)Cois sufficiently large to be considered as constant output voltageVo.
Circuit modules 1 and 2 exhibit the same behavior. Thus, only circuit module 1 is discussed to simplify the circuit analysis. Based on the on/off states of S 1 S 4 and D 1 D 4 , eight operating modes exist in circuit module 1 during one switching cycle. Fig. 4 shows the equivalent circuits of eight operation modes in a switching cycle. S 1 , S 3 , and D 1 D 4 are already conducting before time t 0 .
Mode 1 [t0≤t1]: At t 0 , i D2 = i D4 =0. Given that L m1 = L m2 >> Lr , the magnetizing inductor voltages v Lm1 and v Lm2 are approximately v Cc2 /2 or ( V in /2- v Cc1 )/2. The inductor currents i Lo1 and i Lo2 are increasing in this mode. Power is transferred from input voltage to output load in this time interval. At t 1 , S 1 and S 3 are both off.
Mode 2 [t1≤t2]: At t 1 , S 1 and S 3 are switched off. Given that iLr ( t 1 )>0, C r1 and C r3 are charged linearly, whereas C r2 and C r4 are discharged linearly. At t 2 , v Cr2 and v Cr3 are equal to v Cc1 and v Cc2 , respectively.
Mode 3 [t2≤t3]: At t 2 , v Cr2 = v Cc1 and v Cr3 = v Cc2 . The primary and secondary winding voltages of T 1 and T 2 are zero voltage, such that diodes D 1 D 4 are all conducting. In this mode, v Lo1 = v Lo2 =- Vo , i Lo1 and i Lo2 are decreased linearly, i D1 and i D3 decrease, i D2 and i D4 increase, C r1 and C r3 are continuously charged, whereas C r2 and C r4 are discharged. If the energy stored in L r1 is greater than that stored in C r1 C r4 , then C r2 and C r4 can be discharged to zero voltage. At t 3 , C r2 and C r4 are also discharged to zero voltage. The time interval in modes 2 and 3 are given by
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The dead time td between S 1 and S 2 must be greater than the time interval Δ t 13 to achieve ZVS turn-on for S 2 and S 4 .
Mode 4 [ t 3 t < t 4 ]: At t 3 , v Cr2 = v Cr4 =0. Given that i Lr1 ( t 3 )>0, the anti-parallel diodes of S 2 and S 4 are conducting. Therefore, S 2 and S 4 can be switched on at this moment to achieve ZVS. Given that D 1 D 4 are still in the commutation state, the inductor voltage v Lr1 =-( V in /2- v Cc2 )=- v Cc1 , and i Lr1 is decreasing. At t 4 , i D1 and i D3 are decreasing to zero. The current variation of L r1 is Δ i Lr1 = Io /(2 n ) . The time interval in this mode is given by
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Operation modes of circuit module 1 in a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.
Given that S 2 , S 4 , and D 1 D 4 are conducting, the duty loss in mode 4 is expressed as
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Mode 5 [ t 4 t < t 5 ]: At t 4 , i D1 = i D3 =0. In this mode, the inductor current i Lr1 decreases. Given that the duty ratio of S 1 and S 3 is less than 0.5, the average voltages of C c1 and C c2 are smaller and larger than V in /4, respectively. Currents i Lo1 and i Lo2 decrease with the slope of [ v Cc1 /2 n - Vo ]/ Lo . Power is transferred from input voltage to output load in this time interval. At time t 5 , S 2 and S 4 are switched off.
Mode 6 [ t 5 t < t 6 ]: At time t 5 , power switches S 2 and S 4 are switched off. Given that i Lr1 ( t 5 ) is negative, C r2 and C r4 are charged, whereas C r1 and C r3 are discharged. At time t 6 , v Cr2 and v Cr3 are equal to v Cc1 and v Cc2 , respectively.
Mode 7 [ t 6 t < t 7 ]: At time t 6 , v Cr2 = v Cc1 and v Cr3 = v Cc2 . The primary and secondary winding voltages of T 1 and T 2 are equal to zero voltage, such that D 1 D 4 are conducting, and v Lo1 = v Lo2 =- Vo . i Lo1 and i Lo2 decrease, i D1 and i D3 increase, whereas i D2 and i D4 decrease. C r1 and C r3 are continuously discharged, whereas C r2 and C r4 are charged linearly. If the energy stored in L r1 is greater than the energy stored in C r1 C r4 , then C r1 and C r3 can be discharged to zero voltage. At time t 7 , C r1 and C r3 are discharged to zero voltage. The time interval in modes 6 and 7 is given by
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The dead time td between S 1 and S 2 must be greater than the time interval Δ t 57 to achieve ZVS turn-on for S 1 and S 3 .
Mode 8 [ t 7 t < t 0 + Ts ]: At t 7 , v Cr1 = v Cr3 =0. Given that i Lr1 ( t 7 )<0, the anti-parallel diodes of S 1 and S 3 are conducting. S 1 and S 3 can be switched on at this moment to achieve ZVS. Given that D 1 D 4 are all also conducting, the inductor voltage v Lr1 =( V in /2- v Cc1 )= v Cc2 and i Lr1 are increasing. At t 0 + Ts , i D2 = i D4 =0. The current variation on L r1 is Δ iLr = Io /(2 n ) , and the time interval in this mode is expressed as
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The duty loss in mode 8 is given by
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The circuit operations of the proposed converter in a switching cycle are finally completed.
IV. CIRCUIT CHARACTERISTICS
Given that C r1 C r8 << C c1 C c4 , the charge and discharge times of C r1 C r8 at turn-on and turn-off can be neglected. Only modes 1, 4, 5, and 8 are considered in circuit module 1 to derive the voltage conversion ratio of the proposed converter. From the volt-second balance on ( L r1 , L m1 , and L m2 ) and ( L r2 , L m3 , and L m4 ), the average capacitor voltages V Cc1 V Cc4 are expressed as
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where δ is the duty cycle of S 1 , S 3 , S 5 , and S 7 . We apply the volt-second balance to L o1 L o4 in steady state. The voltage conversion ratio of the proposed converter is derived from
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where Vf is the voltage drop on diodes D 1 D 8 . Based on (3) and (6)–(8), the output voltage can be rewritten as
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The average output inductor currents under steady state are expressed as I Lo1 = I Lo2 = I Lo3 = I Lo4 = Io /4. The ripple currents on output inductors are given by
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Given that i Cc1,av = i Cc2,av = i Cc3,av = i Cc4,av =0, the average magnetizing currents I Lm1 - I Lm4 are approximately equal to (1-2 δ ) Io /(4 n ). The ripple currents on inductances L m1 L m4 can be expressed as
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The maximum and minimum magnetizing currents of L m1 L m4 are given by
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The output inductances of L o1 - L o4 can be obtained as
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The maximum and minimum output inductor currents are expressed as
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The average currents on rectifier diodes D 1 D 8 are expressed as I D1 = I D3 = I D5 = I D7 = δIo /4 and I D2 = I D4 = I D6 = I D8 =(1- δ ) Io /4. The voltage stress of D 1 , D 3 , D 5 , and D 7 is δV in / n In the same manner, the voltage stress of rectifier diodes D 2 , D 4 , D 6 , and D 8 is (1- δ ) V in / n . The root-mean-square ( rms ) values of switching currents i S1,rms i S4,rms are approximately given by
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The voltage stresses of S 1 S 4 are equal to V in /2. At time t 1 , the inductor current i Lr1 is approximated as
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In the same manner, the inductor current i Lr1 at t 5 is approximated as
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If the energy stored in inductor L r1 at t 1 is greater than that in capacitors C r1 C r4 , then C r2 and C r4 can be discharged to zero voltage. The ZVS condition of S 2 and S 4 is expressed as
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If the energy stored in L r1 at t 5 is greater than that in capacitors C r1 C r4 , then capacitors C r1 and C r3 can be discharged to zero voltage. The ZVS condition of S 1 and S 3 is given by
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In the same manner, the ZVS condition of S 5 and S 7 is given by
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The ZVS condition of S 6 and S 8 is shown in (24).
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From (21)–(24), the necessary inductances L r1 and L r1 to achieve ZVS turn-on of S 1 S 8 are derived as
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V. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
The proposed converter design is presented in this section. A laboratory prototype with 1.8 k W rated power was built to test the proposed converter. The electrical specifications of the converter are Vin =750 V to 800 V, Vo =24 V, Io =75 A, and fs =100 kHz. The maximum duty cycle of S 1 is assumed as 0.45 at Vin =750 V and full load. The maximum duty cycle loss in modes 4 and 8 is assumed to be 15% under a full load with a duty cycle δ =0.5.
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Step 1: Resonant inductance
From (26), the resonant inductance of Lr can be derived as
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In the prototype circuit, the selected inductances are L r1 = L r2 =14 μH .
Step 2: Turns ratio of T 1 T 4
If the voltage drop Vf on diodes D 1 D 8 is neglected, the turns ratio of T 1 T 4 is given by
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The TDK EER-40C magnetic cores with primary and secondary winding turns of np =45 turns and ns =15 turns, respectively, are adopted for transformers T 1 T 4 . The magnetizing inductance of T 1 T 4 is 350 μH.
Step 3: Power switches S 1 - S 8
From (17) and (18), the rms currents and voltage stresses of S 1 S 8 are given by
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IRFP460 MOSFETs with VDS =500 V, ID,rms =20 A, RDS,on =0.27 Ω, and Coss =480 pF at 25 V are used for S 1 S 8 .
Step 4: Power diodes D 1 - D 8 and capacitances
The average currents and voltage stresses of D 1 D 8 are expressed as
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The KCU30A30 fast recovery diodes with VRRM =300 V and IF =30 A are used as the rectifier diodes D 1 D 8 . The selected DC blocking capacitances and the output capacitance are C c1 = C c2 = C c3 = C c4 =0.2 μF, C dc1 = C dc2 =470 μF, and Co =4400 μF.
Step 5: Output filter inductances L o1 L o4
The ripple current on L o1 - L o4 is set to 10% of the rated inductor current. From (10), L o1 L o4 can be obtained from
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where L o1 L o4 are set as 16 μH in the prototype circuit.
Step 6: ZVS conditions of S 1 and S 2
The output capacitance of IRFP460 MOSFETs is 480 pF at 25 V. The equivalent output capacitance Cr at Vin =800 V is given by
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From (21) and (22), the minimum inductor current i Lr1 ( t 1 ) and i Lr1 ( t 5 ) to achieve ZVS turn-on for S 1 S 4 is obtained from
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If the ripple currents on the primary and secondary sides in (19) and (20) can be neglected, the minimum load current to achieve ZVS turn-on for ( S 1 and S 3 ) and ( S 2 and S 4 ) are approximated in (39) and (40), respectively.
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From (39) and (40), S 1 , S 3 , S 5 , and S 7 can be switched on under ZVS from 25 A load (approximately 33% load) to 75 A load (100% load). Meanwhile, S 2 , S 4 , S 6 , and S 8 can be turned on under ZVS from 19.7 A load (approximately 26% load) to 75 A load (100% load).
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Photograph of the experimental setup.
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Measured PWM waveforms of gate voltages at full load and (a) Vin=750V (b) Vin=800V.
Experiments based on a laboratory prototype, with the circuit parameters derived in the previous section, are presented in this section to verify the effectiveness of the proposed converter. A photograph of the experimental setup is shown in Fig. 5 . Fig. 6 shows the measured PWM waveforms of S 1 S 8 at full load under different input voltages. The PWM signals of S 5 S 8 were phase-shifted by half of the switching cycle with respect to PWM signals of S 1 S 4 , respectively. Fig. 7 gives the measured gate voltage, drain voltage, and drain current of switches S 1 and S 2 at V in =800 V and 26%, 50%, and 100% load conditions. S 1 is switched on at hard switching under 26% load and at zero voltage switching under 50% and 100% load condition. However, S 2 is switched on under ZVS from 26% load to full load. From the test results in Fig. 7 , we can expect that S 4 , S 6 , and S 8 are also switched on under ZVS from 26% load to full load. Fig. 8 gives the measured voltage waveforms v Cdc1 , v Cdc2 , and v Cc1 + v Cc2 at full load. Three capacitor voltages v Cdc1 , v Cdc2 and v Cc1 + v Cc2 are balanced. Fig. 9 shows the measured waveforms of v S1,gs , v S5,gs , i Lr1 , and i Lr2 at full load. When S 1 is conducting, i Lr1 increases. Meanwhile, i Lr1 decreases if S 1 switched off. i Lr1 and i Lr2 are phase-shifted by half of a switching cycle. Fig. 10 gives the measured waveforms of i D1 , i D2 , i D 5 , i D 6 , and i Lo1 i Lo4 at full load. Fig. 11 shows the output currents i Lo1 + i Lo2 and i Lo3 + i Lo4 of the two circuit modules at full load. The output currents of the two circuit modules balance each other. Fig. 12 shows the measured circuit efficiencies at different load conditions. Based on the load current and the voltage drop on rectifier diodes, the conduction losses on rectifier diodes, MOSFETs, and power semiconductors can be estimated to be approximately 5% to 6%, 1% to 2%, and 6% to 8% of the rated power, respectively. Other power losses are related to the core and copper losses on inductors and transformers, the necessary passive snubber across the rectifier diodes, and some switching losses, such as turn-off losses on MOSFETs and switching losses on rectifier diodes. The rectifier diodes can be replaced by synchronous rectifiers to increase circuit efficiency by approximately 2% to 4%. Low loss MOSFETs and cores can also be adopted to increase circuit efficiency.
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Measured PWM waveforms of gate voltage, drain voltage, and drain current: (a) S1 under 26% load, (b) S2 under 26% load, (c) S1 under 50% load, (d) S2 under 50% load, (e) S1 under 100% load, and (f) S2 under 100% load.
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Measured voltage waveforms vCdc1, vCdc2 and vCc1+vCc2 at full load and 800 V input voltage.
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Measured waveforms of vS1,gs, vS5,gs, iLr1 and iLr2 at full load.
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Measured waveforms of iD1, iD2, iD5, iD6 and iLo1-iLo4 at 100% load.
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Measured waveforms of iLo1+iLo2, iLo3+iLo4 and iLo1+iLo2+iLo3+iLo4 at 100% load.
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Measured circuit efficiencies at different load conditions.
VI. CONCLUSIONS
A new parallel DC/DC converter for applications with high input voltage and high load current is presented. The proposed converter is characterized by 1) ZVS turn-on for all switches from 33% load to 100% load, 2) Vin /2 voltage stress of power switches, and 3) low ripple currents at input and output sides when using the interleaved PWM scheme. Two half-bridge converters are connected in series to reduce the voltage stress of power switches at V in /2. Thus, MOSFETs with 500 V voltage stress are used for 800 V input voltage applications. Two series capacitors connected at the AC terminals of two half-bridge converters are used to balance two input capacitor voltages automatically. A PWM scheme is used to generate PWM signals and regulate output voltage, such that power switches can be switched on under ZVS within the desired load range. System analysis, operation mode, circuit characteristics, and design of the proposed converter are discussed in detail. Finally, experiments with the 1.8 kW prototype are conducted to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 102-2221-E-224 -022 -MY3.
BIO
Bor-Ren Lin received his B.S.E.E. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and his M.S. and Ph.D. degrees in Electrical Engineering from the University of Missouri-Columbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings–Power Electronics and the Journal of Power Electronics. His main research interests include power-factor correction, multilevel converters, active power filters, and soft-switching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College of the National Yunlin University of Science and Technology. He received the Best Paper Awards in the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEE–Power Electronics and Drive Systems 2009 Conference, and the 2014 IEEE-International Conference Industrial Technology.
Huann-Keng Chiang received his M.S. and Ph.D. degrees in Electrical Engineering from the National Cheng Kung University, Taiwan, in 1987 and 1990, respectively.
He is a Professor in the Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan. His research interests include automatic control, digital control, grey theory, and motor servo control.
Shang-Lun Wang is currently working toward his M.S. in Electrical Engineering in the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies, and soft switching converters.
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