A new DC/DC converter with zero voltage switching is proposed for applications with high input voltage and high load current. The proposed converter has two circuit modules that share load current and power rating. Interleaved pulsewidth modulation (PWM) is adopted to generate switch control signals. Thus, ripple currents are reduced at the input and output sides. For highvoltage applications, each circuit module includes two halfbridge legs that are connected in series to reduce switch voltage rating to
V
_{in}
/2. These legs are controlled with the use of asymmetric PWM. To reduce the current rating of rectifier diodes and share load current for highloadcurrent applications, two centertapped rectifiers are adopted in each circuit module. The primary windings of two transformers are connected in series at the high voltage side to balance output inductor currents. Two series capacitors are adopted at the AC terminals of the two halfbridge legs to balance the two input capacitor voltages. The resonant behavior of the inductance and capacitance at the transition interval enable MOSFETs to be switched on under zero voltage switching. The circuit configuration, system characteristics, and design are discussed in detail. Experiments based on a laboratory prototype are conducted to verify the effectiveness of the proposed converter.
I. INTRODUCTION
Highvoltage converters have been studied and proposed for railway electrical systems
[1]
, ship electric power distribution systems
[2]
, and threelevel medium power converters
[3]

[5]
. Threelevel or multilevel converters/inverters
[3]

[5]
with clamped diodes, capacitors, or series Hbridge circuits have been proposed to reduce the voltage rating of power devices. To achieve compact size, high power density, and high circuit efficiency in modern power products, power switches with high switching frequency and low voltage rating can be adopted in mediumpower converters. Thus, threelevel converters can use MOSFETs to limit the voltage stress of power switches to
V
_{in}
/2. Compared with twolevel converters, threelevel converters have more circuit components and higher cost. However, power switches are operated in hard switching mode if converters have high switching frequency. This condition reduces circuit efficiency. Therefore, threelevel converters with soft switching techniques
[6]

[13]
were developed to reduce the switching losses. Thus, all power switches can be switched on at zero current switching (ZCS) or zero voltage switching (ZVS) within the desired load range. The leakage inductance or external inductance of the transformer and the output capacitance of power switches are resonant at the transition interval. The draintosource voltage of MOSFETs can be decreased to zero voltage before MOSFETs are switched on. Therefore, if MOSFETs are switched on under ZVS, circuit efficiency is improved to achieve high switching frequency.
This study presents an interleaved soft switching DC/DC converter for highvoltage and mediumpower applications. This converter is characterized by low switching loss, ZVS turnon, and low voltage rating of MOSFETs. Two circuit modules are adopted, and the interleaved PWM scheme is used to share load current and reduce the ripple currents at input and output capacitors. Thus, the size of the input and output capacitors is reduced. In each circuit module, two input capacitors and two halfbridge converters are connected in series at the high voltage side to limit the voltage rating of MOSFETs to
V_{in}
/2. Therefore, power MOSFETs with 500 V voltage rating can be used in DC converters with 800 V input voltage. Two balance capacitors are connected in series between the AC sides of two halfbridge legs to balance two input split capacitor voltages automatically in each switching style. The primary windings of two transformers are connected in series to balance the secondary winding currents. Thus, power can be equally transferred to output load through two centertapped rectifiers. Asymmetric PWM is adopted to generate the appropriate signals and regulate output voltage. MOSFETs can be switched on at ZVS within the desired load range on the basis of the resonant behavior of the MOSFET output capacitance and the transformer leakage inductance. The operation principle, circuit analysis, and design example of the proposed converter are discussed in detail. To verify the performance of the proposed converter, experiments are conducted with the use of a 1.8 kW prototype .
II. CIRCUIT CONFIGURATION
For a general singlephase AC/DC converter, the conventional halfbridge and fullbridge circuit topologies are adopted in the second stage DC/DC converter to regulate output voltage. The voltage stress of the power switches in these circuit topologies is set at DC input bus voltage
V
_{in}
. Power MOSFETs with 600 V voltage stress are normally adopted for halfbridge and fullbridge converters and are used after singlephase power factor correction (PFC). For threephase AC/DC converters with PFC function, 900 V voltage stress MOSFETs or 1200 V IGBTs are adopted in the second stage DC/DC converter. The two halfbridge converters shown in
Fig. 1
are connected in series at the high voltage side to reduce the voltage rating of power switches to
V
_{in}
/2. Meanwhile, these converters are connected in parallel at the lowvoltage side to reduce the current rating of passive and active components. The main drawback of this circuit topology is that the two input split capacitor voltages can be unbalanced and thus result in unbalanced output inductor currents.
The circuit configuration of the proposed converter is shown in
Fig. 2
. The DC bus voltage after threephase PFC is normally within the range of 750 V to 800 V. Two input split capacitor voltages
V
_{Cdc1}
and
V
_{Cdc2}
can be automatically balanced by the clamped capacitors
C
_{c1}
–
C
_{c4}
. The proposed DC/DC converter has two circuit modules that share the load current. The interleaved PWM with a 90degree phase shift is adopted to generate the appropriate switching signals and regulate output voltage. Thus, the ripple currents at the input and output capacitors can be reduced. Each circuit module in the proposed converter has two halfbridge converters in series. For circuit module 1, the first halfbridge converter includes
C
_{dc1}
,
S
_{1}
,
S
_{2}
,
L
_{r1}
,
T
_{1}
,
T
_{2}
,
C
_{r1}
,
C
_{r2}
,
C
_{c1}
,
D
_{1}
,
D
_{2}
,
L
_{o1}
, and
C_{o}
. The second halfbridge converter includes the components
C
_{dc2}
,
S
_{3}
,
S
_{4}
,
L
_{r1}
,
T
_{1}
,
T
_{2}
,
C
_{r3}
,
C
_{r4}
,
C
_{c2}
,
D
_{3}
,
D
_{4}
,
L
_{o2}
, and
C_{o}
.
V
_{in}
and
V_{o}
are the input and output DC bus voltages, respectively.
C_{o}
is the output capacitance, and
R_{o}
is the load resistance.
C
_{c1}
–
C
_{c4}
are the DC blocking capacitances.
C
_{r1}
–
C
_{r8}
are the output capacitances of MOSFETs
S
_{1}
–
S
_{8}
, respectively.
L
_{r1}
and
L
_{r2}
are the resonant inductances,
L
_{m1}
–
L
_{m4}
are the magnetizing inductances and
L
_{o1}
–
L
_{o4}
are the output inductances of transformers
T
_{1}
–
T
_{4}
, respectively.
D
_{1}
–
D
_{8}
are the rectifier diodes. The asymmetric PWM scheme is used to control MOSFETs
S
_{1}
–
S
_{8}
.
S
_{1}
and
S
_{3}
have the same PWM signals, whereas
S
_{2}
and
S
_{4}
have the same PWM waveforms. However,
S
_{1}
and
S
_{2}
complement each other with dead time to enable the ZVS operation. The gate signals of
S
_{5}
–
S
_{8}
are phaseshifted by onefourth of the switching period with respect to the gate signals of
S
_{1}
–
S
_{4}
. Therefore, the inductor currents
i
_{Lr1}
and
i
_{Lr2}
are interleaved.
C
_{dc1}
and
C
_{dc2}
are input capacitors that split the input voltage (
V
_{Cdc1}
=
V
_{Cdc2}
=
V
_{in}
/2).
C
_{c1}
and
C
_{c2}
are connected in series between AC terminals
a
and
b
to balance
V
_{Cdc1}
and
V
_{Cdc2}
automatically. For example, the voltage across
C
_{c1}
and
C
_{c2}
is equal to
V
_{Cdc1}
if
S
_{1}
and
S
_{3}
are conducting while
S
_{2}
and
S
_{4}
are in the offstate. Meanwhile, the voltage across
C
_{c1}
and
C
_{c2}
is equal to
V
_{Cdc2}
if
S
_{1}
and
S
_{3}
are in the offstate while
S
_{2}
and
S
_{4}
are conducting. Based on the on/off states of
S
_{1}
–
S
_{8}
, two split capacitor voltages
V
_{Cdc1}
=
V
_{Cdc2}
=
V
_{in}
/2 and the voltage stress of
S
_{1}
–
S
_{8}
are equal to
V
_{in}
/2. In the proposed converter, the primary windings of transformers
T
_{1}
and
T
_{2}
are connected in series to balance
i
_{Lo1}
and
i
_{Lo2}
automatically. In the same manner, the output inductor currents
i
_{Lo3}
and
i
_{Lo4}
are also balanced. If power is delivered through two balanced circuit modules, then the current rating of each output inductor is equal to
I_{o}
/4.
Circuit configuration of two series halfbridge converter for highinputvoltage and highcurrent applications.
Circuit configuration of the proposed interleaved ZVS converter.
III. OPERATION PRINCIPLE
Key waveforms in a switching cycle (a) circuit module 1 (b) the proposed converter.
The main PWM waveforms of circuit module 1 in the proposed converter are given in
Fig. 3
(a). The duty cycle of
S
_{1}
and
S
_{3}
is
δ
, and that of
S
_{2}
and
S
_{4}
is 1
δ
. The circuit modules are controlled by an interleaved PWM scheme. The gate signals of
S
_{5}
–
S
_{8}
are phaseshifted by
T_{s}
/4 with respect to the gate signals of
S
_{1}
–
S
_{4}
, respectively.
Fig. 3
(b) shows the main waveforms of the proposed interleaved DC/DC converter. The following assumptions about the proposed converter are made to simplify the system analysis:

1) TransformersT1–T4have the same magnetizing inductanceLmand turns ration;

2) Power switchesS1–S8and rectifier diodesD1–D8are ideal;

3) Resonant capacitancesCr1=..=Cr8=Cr;

4) DC blocking capacitancesCc1=Cc2=Cc3=Cc4=Cc;

5) Input split capacitancesCdc1=Cdc2;

6) Output inductancesLo1=Lo2=Lo3=Lo4=Lo; and

7)Cois sufficiently large to be considered as constant output voltageVo.
Circuit modules 1 and 2 exhibit the same behavior. Thus, only circuit module 1 is discussed to simplify the circuit analysis. Based on the on/off states of
S
_{1}
–
S
_{4}
and
D
_{1}
–
D
_{4}
, eight operating modes exist in circuit module 1 during one switching cycle.
Fig. 4
shows the equivalent circuits of eight operation modes in a switching cycle.
S
_{1}
,
S
_{3}
, and
D
_{1}
–
D
_{4}
are already conducting before time
t
_{0}
.
Mode 1 [t_{0}≤t1]:
At
t
_{0}
,
i
_{D2}
=
i
_{D4}
=0. Given that
L
_{m1}
=
L
_{m2}
>>
L_{r}
, the magnetizing inductor voltages
v
_{Lm1}
and
v
_{Lm2}
are approximately
v
_{Cc2}
/2 or (
V
_{in}
/2
v
_{Cc1}
)/2. The inductor currents
i
_{Lo1}
and
i
_{Lo2}
are increasing in this mode. Power is transferred from input voltage to output load in this time interval. At
t
_{1}
,
S
_{1}
and
S
_{3}
are both off.
Mode 2 [t_{1}≤t2]:
At
t
_{1}
,
S
_{1}
and
S
_{3}
are switched off. Given that
i_{Lr}
(
t
_{1}
)>0,
C
_{r1}
and
C
_{r3}
are charged linearly, whereas
C
_{r2}
and
C
_{r4}
are discharged linearly. At
t
_{2}
,
v
_{Cr2}
and
v
_{Cr3}
are equal to
v
_{Cc1}
and
v
_{Cc2}
, respectively.
Mode 3 [t_{2}≤t3]:
At
t
_{2}
,
v
_{Cr2}
=
v
_{Cc1}
and
v
_{Cr3}
=
v
_{Cc2}
. The primary and secondary winding voltages of
T
_{1}
and
T
_{2}
are zero voltage, such that diodes
D
_{1}
–
D
_{4}
are all conducting. In this mode,
v
_{Lo1}
=
v
_{Lo2}
=
V_{o}
,
i
_{Lo1}
and
i
_{Lo2}
are decreased linearly,
i
_{D1}
and
i
_{D3}
decrease,
i
_{D2}
and
i
_{D4}
increase,
C
_{r1}
and
C
_{r3}
are continuously charged, whereas
C
_{r2}
and
C
_{r4}
are discharged. If the energy stored in
L
_{r1}
is greater than that stored in
C
_{r1}
–
C
_{r4}
, then
C
_{r2}
and
C
_{r4}
can be discharged to zero voltage. At
t
_{3}
,
C
_{r2}
and
C
_{r4}
are also discharged to zero voltage. The time interval in modes 2 and 3 are given by
The dead time
t_{d}
between
S
_{1}
and
S
_{2}
must be greater than the time interval Δ
t
_{13}
to achieve ZVS turnon for
S
_{2}
and
S
_{4}
.
Mode
4 [
t
_{3}
≤
t
<
t
_{4}
]: At
t
_{3}
,
v
_{Cr2}
=
v
_{Cr4}
=0. Given that
i
_{Lr1}
(
t
_{3}
)>0, the antiparallel diodes of
S
_{2}
and
S
_{4}
are conducting. Therefore,
S
_{2}
and
S
_{4}
can be switched on at this moment to achieve ZVS. Given that
D
_{1}
–
D
_{4}
are still in the commutation state, the inductor voltage
v
_{Lr1}
=(
V
_{in}
/2
v
_{Cc2}
)=
v
_{Cc1}
, and
i
_{Lr1}
is decreasing. At
t
_{4}
,
i
_{D1}
and
i
_{D3}
are decreasing to zero. The current variation of
L
_{r1}
is Δ
i
_{Lr1}
=
I_{o}
/(2
n
) . The time interval in this mode is given by
Operation modes of circuit module 1 in a switching cycle. (a) Mode 1. (b) Mode 2. (c) Mode 3. (d) Mode 4. (e) Mode 5. (f) Mode 6. (g) Mode 7. (h) Mode 8.
Given that
S
_{2}
,
S
_{4}
, and
D
_{1}
–
D
_{4}
are conducting, the duty loss in mode 4 is expressed as
Mode
5 [
t
_{4}
≤
t
<
t
_{5}
]: At
t
_{4}
,
i
_{D1}
=
i
_{D3}
=0. In this mode, the inductor current
i
_{Lr1}
decreases. Given that the duty ratio of
S
_{1}
and
S
_{3}
is less than 0.5, the average voltages of
C
_{c1}
and
C
_{c2}
are smaller and larger than
V
_{in}
/4, respectively. Currents
i
_{Lo1}
and
i
_{Lo2}
decrease with the slope of [
v
_{Cc1}
/2
n

V_{o}
]/
L_{o}
. Power is transferred from input voltage to output load in this time interval. At time
t
_{5}
,
S
_{2}
and
S
_{4}
are switched off.
Mode
6 [
t
_{5}
≤
t
<
t
_{6}
]: At time
t
_{5}
, power switches
S
_{2}
and
S
_{4}
are switched off. Given that
i
_{Lr1}
(
t
_{5}
) is negative,
C
_{r2}
and
C
_{r4}
are charged, whereas
C
_{r1}
and
C
_{r3}
are discharged. At time
t
_{6}
,
v
_{Cr2}
and
v
_{Cr3}
are equal to
v
_{Cc1}
and
v
_{Cc2}
, respectively.
Mode
7 [
t
_{6}
≤
t
<
t
_{7}
]: At time
t
_{6}
,
v
_{Cr2}
=
v
_{Cc1}
and
v
_{Cr3}
=
v
_{Cc2}
. The primary and secondary winding voltages of
T
_{1}
and
T
_{2}
are equal to zero voltage, such that
D
_{1}
–
D
_{4}
are conducting, and
v
_{Lo1}
=
v
_{Lo2}
=
V_{o}
.
i
_{Lo1}
and
i
_{Lo2}
decrease,
i
_{D1}
and
i
_{D3}
increase, whereas
i
_{D2}
and
i
_{D4}
decrease.
C
_{r1}
and
C
_{r3}
are continuously discharged, whereas
C
_{r2}
and
C
_{r4}
are charged linearly. If the energy stored in
L
_{r1}
is greater than the energy stored in
C
_{r1}
–
C
_{r4}
, then
C
_{r1}
and
C
_{r3}
can be discharged to zero voltage. At time
t
_{7}
,
C
_{r1}
and
C
_{r3}
are discharged to zero voltage. The time interval in modes 6 and 7 is given by
The dead time
t_{d}
between
S
_{1}
and
S
_{2}
must be greater than the time interval Δ
t
_{57}
to achieve ZVS turnon for
S
_{1}
and
S
_{3}
.
Mode
8 [
t
_{7}
≤
t
<
t
_{0}
+
T_{s}
]: At
t
_{7}
,
v
_{Cr1}
=
v
_{Cr3}
=0. Given that
i
_{Lr1}
(
t
_{7}
)<0, the antiparallel diodes of
S
_{1}
and
S
_{3}
are conducting.
S
_{1}
and
S
_{3}
can be switched on at this moment to achieve ZVS. Given that
D
_{1}
–
D
_{4}
are all also conducting, the inductor voltage
v
_{Lr1}
=(
V
_{in}
/2
v
_{Cc1}
)=
v
_{Cc2}
and
i
_{Lr1}
are increasing. At
t
_{0}
+
T_{s}
,
i
_{D2}
=
i
_{D4}
=0. The current variation on
L
_{r1}
is Δ
i_{Lr}
=
I_{o}
/(2
n
) , and the time interval in this mode is expressed as
The duty loss in mode 8 is given by
The circuit operations of the proposed converter in a switching cycle are finally completed.
IV. CIRCUIT CHARACTERISTICS
Given that
C
_{r1}
–
C
_{r8}
<<
C
_{c1}
–
C
_{c4}
, the charge and discharge times of
C
_{r1}
–
C
_{r8}
at turnon and turnoff can be neglected. Only modes 1, 4, 5, and 8 are considered in circuit module 1 to derive the voltage conversion ratio of the proposed converter. From the voltsecond balance on (
L
_{r1}
,
L
_{m1}
, and
L
_{m2}
) and (
L
_{r2}
,
L
_{m3}
, and
L
_{m4}
), the average capacitor voltages
V
_{Cc1}
–
V
_{Cc4}
are expressed as
where
δ
is the duty cycle of
S
_{1}
,
S
_{3}
,
S
_{5}
, and
S
_{7}
. We apply the voltsecond balance to
L
_{o1}
–
L
_{o4}
in steady state. The voltage conversion ratio of the proposed converter is derived from
where
V_{f}
is the voltage drop on diodes
D
_{1}
–
D
_{8}
. Based on (3) and (6)–(8), the output voltage can be rewritten as
The average output inductor currents under steady state are expressed as
I
_{Lo1}
=
I
_{Lo2}
=
I
_{Lo3}
=
I
_{Lo4}
=
I_{o}
/4. The ripple currents on output inductors are given by
Given that
i
_{Cc1,av}
=
i
_{Cc2,av}
=
i
_{Cc3,av}
=
i
_{Cc4,av}
=0, the average magnetizing currents
I
_{Lm1}

I
_{Lm4}
are approximately equal to (12
δ
)
I_{o}
/(4
n
). The ripple currents on inductances
L
_{m1}
–
L
_{m4}
can be expressed as
The maximum and minimum magnetizing currents of
L
_{m1}
–
L
_{m4}
are given by
The output inductances of
L
_{o1}

L
_{o4}
can be obtained as
The maximum and minimum output inductor currents are expressed as
The average currents on rectifier diodes
D
_{1}
–
D
_{8}
are expressed as
I
_{D1}
=
I
_{D3}
=
I
_{D5}
=
I
_{D7}
=
δI_{o}
/4 and
I
_{D2}
=
I
_{D4}
=
I
_{D6}
=
I
_{D8}
=(1
δ
)
I_{o}
/4. The voltage stress of
D
_{1}
,
D
_{3}
,
D
_{5}
, and
D
_{7}
is
δV
_{in}
/
n
In the same manner, the voltage stress of rectifier diodes
D
_{2}
,
D
_{4}
,
D
_{6}
, and
D
_{8}
is (1
δ
)
V
_{in}
/
n
. The rootmeansquare (
rms
) values of switching currents
i
_{S1,rms}
–
i
_{S4,rms}
are approximately given by
The voltage stresses of
S
_{1}
–
S
_{4}
are equal to
V
_{in}
/2. At time
t
_{1}
, the inductor current
i
_{Lr1}
is approximated as
In the same manner, the inductor current
i
_{Lr1}
at
t
_{5}
is approximated as
If the energy stored in inductor
L
_{r1}
at
t
_{1}
is greater than that in capacitors
C
_{r1}
–
C
_{r4}
, then
C
_{r2}
and
C
_{r4}
can be discharged to zero voltage. The ZVS condition of
S
_{2}
and
S
_{4}
is expressed as
If the energy stored in
L
_{r1}
at
t
_{5}
is greater than that in capacitors
C
_{r1}
–
C
_{r4}
, then capacitors
C
_{r1}
and
C
_{r3}
can be discharged to zero voltage. The ZVS condition of
S
_{1}
and
S
_{3}
is given by
In the same manner, the ZVS condition of
S
_{5}
and
S
_{7}
is given by
The ZVS condition of
S
_{6}
and
S
_{8}
is shown in (24).
From (21)–(24), the necessary inductances
L
_{r1}
and
L
_{r1}
to achieve ZVS turnon of
S
_{1}
–
S
_{8}
are derived as
V. DESIGN EXAMPLE AND EXPERIMENTAL RESULTS
The proposed converter design is presented in this section. A laboratory prototype with 1.8
k
W rated power was built to test the proposed converter. The electrical specifications of the converter are
V_{in}
=750 V to 800 V,
V_{o}
=24 V,
I_{o}
=75 A, and
f_{s}
=100 kHz. The maximum duty cycle of
S
_{1}
is assumed as 0.45 at
V_{in}
=750 V and full load. The maximum duty cycle loss in modes 4 and 8 is assumed to be 15% under a full load with a duty cycle
δ
=0.5.
Step 1:
Resonant inductance
From (26), the resonant inductance of
L_{r}
can be derived as
In the prototype circuit, the selected inductances are
L
_{r1}
=
L
_{r2}
=14
μH
.
Step 2:
Turns ratio of
T
_{1}
–
T
_{4}
If the voltage drop
V_{f}
on diodes
D
_{1}
–
D
_{8}
is neglected, the turns ratio of
T
_{1}
–
T
_{4}
is given by
The TDK EER40C magnetic cores with primary and secondary winding turns of
n_{p}
=45 turns and
n_{s}
=15 turns, respectively, are adopted for transformers
T
_{1}
–
T
_{4}
. The magnetizing inductance of
T
_{1}
–
T
_{4}
is 350 μH.
Step 3:
Power switches
S
_{1}

S
_{8}
From (17) and (18), the
rms
currents and voltage stresses of
S
_{1}
–
S
_{8}
are given by
IRFP460 MOSFETs with
V_{DS}
=500 V,
I_{D,rms}
=20 A,
R_{DS,on}
=0.27 Ω, and
C_{oss}
=480 pF at 25 V are used for
S
_{1}
–
S
_{8}
.
Step 4:
Power diodes
D
_{1}

D
_{8}
and capacitances
The average currents and voltage stresses of
D
_{1}
–
D
_{8}
are expressed as
The KCU30A30 fast recovery diodes with
V_{RRM}
=300 V and
I_{F}
=30 A are used as the rectifier diodes
D
_{1}
–
D
_{8}
. The selected DC blocking capacitances and the output capacitance are
C
_{c1}
=
C
_{c2}
=
C
_{c3}
=
C
_{c4}
=0.2 μF,
C
_{dc1}
=
C
_{dc2}
=470 μF, and
C_{o}
=4400 μF.
Step 5:
Output filter inductances
L
_{o1}
–
L
_{o4}
The ripple current on
L
_{o1}

L
_{o4}
is set to 10% of the rated inductor current. From (10),
L
_{o1}
–
L
_{o4}
can be obtained from
where
L
_{o1}
–
L
_{o4}
are set as 16 μH in the prototype circuit.
Step 6:
ZVS conditions of
S
_{1}
and
S
_{2}
The output capacitance of IRFP460 MOSFETs is 480 pF at 25 V. The equivalent output capacitance
C_{r}
at
V_{in}
=800 V is given by
From (21) and (22), the minimum inductor current
i
_{Lr1}
(
t
_{1}
) and
i
_{Lr1}
(
t
_{5}
) to achieve ZVS turnon for
S
_{1}
–
S
_{4}
is obtained from
If the ripple currents on the primary and secondary sides in (19) and (20) can be neglected, the minimum load current to achieve ZVS turnon for (
S
_{1}
and
S
_{3}
) and (
S
_{2}
and
S
_{4}
) are approximated in (39) and (40), respectively.
From (39) and (40),
S
_{1}
,
S
_{3}
,
S
_{5}
, and
S
_{7}
can be switched on under ZVS from 25 A load (approximately 33% load) to 75 A load (100% load). Meanwhile,
S
_{2}
,
S
_{4}
,
S
_{6}
, and
S
_{8}
can be turned on under ZVS from 19.7 A load (approximately 26% load) to 75 A load (100% load).
Photograph of the experimental setup.
Measured PWM waveforms of gate voltages at full load and (a) V_{in}=750V (b) V_{in}=800V.
Experiments based on a laboratory prototype, with the circuit parameters derived in the previous section, are presented in this section to verify the effectiveness of the proposed converter. A photograph of the experimental setup is shown in
Fig. 5
.
Fig. 6
shows the measured PWM waveforms of
S
_{1}
–
S
_{8}
at full load under different input voltages. The PWM signals of
S
_{5}
–
S
_{8}
were phaseshifted by half of the switching cycle with respect to PWM signals of
S
_{1}
–
S
_{4}
, respectively.
Fig. 7
gives the measured gate voltage, drain voltage, and drain current of switches
S
_{1}
and
S
_{2}
at
V
_{in}
=800 V and 26%, 50%, and 100% load conditions.
S
_{1}
is switched on at hard switching under 26% load and at zero voltage switching under 50% and 100% load condition. However,
S
_{2}
is switched on under ZVS from 26% load to full load. From the test results in
Fig. 7
, we can expect that
S
_{4}
,
S
_{6}
, and
S
_{8}
are also switched on under ZVS from 26% load to full load.
Fig. 8
gives the measured voltage waveforms
v
_{Cdc1}
,
v
_{Cdc2}
, and
v
_{Cc1}
+
v
_{Cc2}
at full load. Three capacitor voltages
v
_{Cdc1}
,
v
_{Cdc2}
and
v
_{Cc1}
+
v
_{Cc2}
are balanced.
Fig. 9
shows the measured waveforms of
v
_{S1,gs}
,
v
_{S5,gs}
,
i
_{Lr1}
, and
i
_{Lr2}
at full load. When
S
_{1}
is conducting,
i
_{Lr1}
increases. Meanwhile,
i
_{Lr1}
decreases if
S
_{1}
switched off.
i
_{Lr1}
and
i
_{Lr2}
are phaseshifted by half of a switching cycle.
Fig. 10
gives the measured waveforms of
i
_{D1}
,
i
_{D2}
, i
D
_{5}
, i
D
_{6}
, and
i
_{Lo1}
–
i
_{Lo4}
at full load.
Fig. 11
shows the output currents
i
_{Lo1}
+
i
_{Lo2}
and
i
_{Lo3}
+
i
_{Lo4}
of the two circuit modules at full load. The output currents of the two circuit modules balance each other.
Fig. 12
shows the measured circuit efficiencies at different load conditions. Based on the load current and the voltage drop on rectifier diodes, the conduction losses on rectifier diodes, MOSFETs, and power semiconductors can be estimated to be approximately 5% to 6%, 1% to 2%, and 6% to 8% of the rated power, respectively. Other power losses are related to the core and copper losses on inductors and transformers, the necessary passive snubber across the rectifier diodes, and some switching losses, such as turnoff losses on MOSFETs and switching losses on rectifier diodes. The rectifier diodes can be replaced by synchronous rectifiers to increase circuit efficiency by approximately 2% to 4%. Low loss MOSFETs and cores can also be adopted to increase circuit efficiency.
Measured PWM waveforms of gate voltage, drain voltage, and drain current: (a) S_{1} under 26% load, (b) S_{2} under 26% load, (c) S_{1} under 50% load, (d) S_{2} under 50% load, (e) S_{1} under 100% load, and (f) S_{2} under 100% load.
Measured voltage waveforms v_{Cdc1}, v_{Cdc2} and v_{Cc1}+v_{Cc2} at full load and 800 V input voltage.
Measured waveforms of v_{S1,gs}, v_{S5,gs}, i_{Lr1} and i_{Lr2} at full load.
Measured waveforms of i_{D1}, i_{D2}, iD_{5}, iD_{6} and i_{Lo1}i_{Lo4} at 100% load.
Measured waveforms of i_{Lo1}+i_{Lo2}, i_{Lo3}+i_{Lo4} and i_{Lo1}+i_{Lo2}+i_{Lo3}+i_{Lo4} at 100% load.
Measured circuit efficiencies at different load conditions.
VI. CONCLUSIONS
A new parallel DC/DC converter for applications with high input voltage and high load current is presented. The proposed converter is characterized by 1) ZVS turnon for all switches from 33% load to 100% load, 2)
V_{in}
/2 voltage stress of power switches, and 3) low ripple currents at input and output sides when using the interleaved PWM scheme. Two halfbridge converters are connected in series to reduce the voltage stress of power switches at
V
_{in}
/2. Thus, MOSFETs with 500 V voltage stress are used for 800 V input voltage applications. Two series capacitors connected at the AC terminals of two halfbridge converters are used to balance two input capacitor voltages automatically. A PWM scheme is used to generate PWM signals and regulate output voltage, such that power switches can be switched on under ZVS within the desired load range. System analysis, operation mode, circuit characteristics, and design of the proposed converter are discussed in detail. Finally, experiments with the 1.8 kW prototype are conducted to verify the effectiveness of the proposed converter.
Acknowledgements
This project is partly supported by the National Science Council of Taiwan under Grant NSC 1022221E224 022 MY3.
BIO
BorRen Lin received his B.S.E.E. degree in Electronic Engineering from the National Taiwan University of Science and Technology, Taipei, Taiwan, in 1988 and his M.S. and Ph.D. degrees in Electrical Engineering from the University of MissouriColumbia, USA, in 1990 and 1993, respectively. From 1991 to 1993, he was a Research Assistant with the Power Electronic Research Center, University of Missouri. Since 1993, he has been with the Department of Electrical Engineering, National Yunlin University of Science and Technology, Douliou, Taiwan, where he is currently a Distinguished Professor. He is an Associate Editor of the Institution of Engineering and Technology Proceedings–Power Electronics and the Journal of Power Electronics. His main research interests include powerfactor correction, multilevel converters, active power filters, and softswitching converters. He has authored more than 200 published technical journal papers in the area of power electronics. Dr. Lin is an Associate Editor of the IEEE Transactions on Industrial Electronics. He was the recipient of the Research Excellence Awards in 2004, 2005, 2007, and 2011 from the Engineering College of the National Yunlin University of Science and Technology. He received the Best Paper Awards in the 2007 and 2011 IEEE Conference on Industrial Electronics and Applications, Taiwan Power Electronics 2007 Conference, the IEEE–Power Electronics and Drive Systems 2009 Conference, and the 2014 IEEEInternational Conference Industrial Technology.
HuannKeng Chiang received his M.S. and Ph.D. degrees in Electrical Engineering from the National Cheng Kung University, Taiwan, in 1987 and 1990, respectively.
He is a Professor in the Department of Electrical Engineering, National Yunlin University of Science and Technology, Taiwan. His research interests include automatic control, digital control, grey theory, and motor servo control.
ShangLun Wang is currently working toward his M.S. in Electrical Engineering in the National Yunlin University of Science and Technology, Yunlin, Taiwan, ROC. His research interests include the design and analysis of power factor correction techniques, switching mode power supplies, and soft switching converters.
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