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Non-isolated Bidirectional Soft-switching SEPIC/ZETA Converter with Reduced Ripple Currents
Non-isolated Bidirectional Soft-switching SEPIC/ZETA Converter with Reduced Ripple Currents
Journal of Power Electronics. 2014. Jul, 14(4): 649-660
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : December 14, 2013
  • Accepted : May 21, 2014
  • Published : July 28, 2014
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About the Authors
Min-Sup Song
Central R&D Institute, Samsung Electro-Mechanics, Suwon, Korea
minsup.song@samsung.com
Young-Dong Son
Central R&D Institute, Samsung Electro-Mechanics, Suwon, Korea
Kwang-Hyun Lee
Central R&D Institute, Samsung Electro-Mechanics, Suwon, Korea

Abstract
A novel non-isolated bidirectional soft-switching SEPIC/ZETA converter with reduced ripple currents is proposed and characterized in this study. Two auxiliary switches and an inductor are added to the original bidirectional SEPIC/ZETA components to form a new direct power delivery path between input and output. The proposed converter can be operated in the forward SEPIC and reverse ZETA modes with reduced ripple currents and increased voltage gains attributed to the optimized selection of duty ratios. All switches in the proposed converter can be operated at zero-current-switching turn-on and/or turn-off through soft current commutation. Therefore, the switching and conduction losses of the proposed converter are considerably reduced compared with those of conventional bidirectional SEPIC/ZETA converters. The operation principles and characteristics of the proposed converter are analyzed in detail and verified by the simulation and experimental results.
Keywords
I. INTRODUCTION
Bidirectional DC–DC converters can manipulate bilateral power flow between two DC sources by using only a single-circuit structure. Therefore, the weight, volume, and cost of the overall system can be reduced by simplifying circuit composition [1] . These desirable features increased the use of bidirectional DC–DC converters in battery chargers/dischargers, fuel cell hybrid power systems, DC uninterruptible power supplies, and energy regenerative systems in automotive applications [2] - [9] .
Non-isolated converters are simpler and more efficient than isolated converters and are thus preferred for use when galvanic isolation is unnecessary. The literature has reported on several non-isolated bidirectional DC–DC converters, such as bidirectional boost/buck-derived [10] - [13] , Cuk [14] , SEPIC/ZETA [15] , multilevel [16] , [17] , and coupled-inductor type converters [18] , [19] . Multiphase interleaved converters are often adopted to decrease voltage ripple and filter size by reducing the inductor current ripple components [20] - [22] . These converters can enhance circuit performance but may increase overall circuit system complexity. Control reliability may also deteriorate with increased interleaving phases.
Without using any interleaved techniques, unidirectional SEPIC and ZETA converters featuring reduced ripple currents have been proposed in [23] , [24] . The converters consist of the original SEPIC or ZETA components in addition to an auxiliary diode and switch to form a new direct power delivery path between input and output. Inductor ripple currents and switching voltages of the main switch and diode can be reduced by shortening the duration of the original SEPIC or ZETA operation while extending the duration of the direct power link operation. However, these converters still possess hard-switching properties, and diodes particularly suffer from severe reverse recovery problem.
A new non-isolated bidirectional soft switching SEPIC/ZETA converter with reduced ripple currents is proposed to overcome these hard-switching problems. A small inductor is added to the auxiliary power delivery path, and diodes are replaced by active switches for bidirectional power flow control, as shown in the modified SEPIC topology in Fig. 1 (a). With the use of a single-circuit structure, SEPIC and ZETA operations are implemented in the forward and reverse directions, respectively. Similar to the features of original bidirectional SEPIC/ZETA converters, both step-up and step-down operations are available regardless of power conversion directions. A similar operation can be performed in the bilateral direction because of the duality between SEPIC and ZETA converters [23] [25] . Through the use of constant frequency pulse-width modulation control, the proposed converter behaves in a manner similar to that of the original bidirectional SEPIC/ZETA converter when auxiliary switches are fully turned off. The converter can reduce inductor current ripples without employing interleaved methods. Thus, the DC resistive losses of inductors and capacitors, as well as the conduction and switching losses of switches, are reduced. The current rating of switches can be also reduced. Switches are operated at zero-current-switching (ZCS) turn-on and turn-off through soft current commutation between switches. Synchronous rectification and zero-voltage-switching (ZVS) are also achieved for synchronous rectifiers. Consequently, the overall power conversion efficiency of the proposed converter can be considerably increased compared with that of the original non-isolated bidirectional SEPIC/ZETA converter.
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Unidirectional (a) SEPIC and (b) ZETA converters with reduced ripple currents.
II. OPERATION ANALYSIS OF THE PROPOSED CONVERTER
- A. Circuit Structure
The proposed converter can be divided into two parts, as shown in Fig. 2 . The first part is the original non-isolated bidirectional SEPIC/ZETA converter consisting of inductors L 1 and L 2 , capacitors Cin , Cs , and Co , and switches S 1 and S 2 . The second part is an additional circuit consisting of switches S 3 and S 4 , as well as an inductor La . The additional circuit provides a new direct power delivery path between input and output. SEPIC and ZETA operations are implemented in the forward and reverse directions, respectively.
In SEPIC operation, S 1 acts as the main switch, S 2 is the synchronous rectifier, whereas S 3 and S 4 are the auxiliary switches. In ZETA operation, S 1 conducts for the synchronous rectifier, S 2 is the main switch, whereas and S 3 and S 4 are the auxiliary switches. La induces the soft current transition between switches.
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Circuit structure of the proposed converter.
- B. Mode Analysis
In the proposed converter, La is considerably smaller than L 1 and L 2 . Therefore, following basic operation analysis ignores the effect of La and treats the proposed converter as a conventional hard-switching converter to simplify the analysis. The proposed converter has three distinct operation modes in SEPIC and ZETA operations during each switching cycle. The operation waveforms for the forward SEPIC mode are shown in Fig. 3 .
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SEPIC operation waveforms of the proposed converter in (a) step-up and (b) step-down operations.
Mode 1 [t0–t1]: From t 0 to t 1 , only S 1 conducts while the other switches are idle. The average inductor voltage is zero at steady state. Thus, the voltage of Cs is equal to the input voltage Vin [26] . Voltages across L 1 ( v L1 ) and L 2 ( v L2 ) are both equal to Vin . Currents through L 1 ( i L1 ) and L 2 ( i L2 ) increase with slopes of Vin / L 1 and Vin / L 2 , respectively. The current flowing through S 1 ( i S1 ) is the sum of i L1 and i L2 . The drain-source voltages of S 1 ( v S1 ) and S 2 ( v S2 ) are 0 V and Vin + Vo , respectively, where Vo is output voltage. At the beginning of this mode, the capacitor charging current flows from the Vo terminal to S 1 through the output capacitor of S 3 and the body diode of S 4 . Therefore, the drain-source voltages of S 3 ( v S3 ) and S 4 ( v S4 ) become Vo and 0 V, respectively. S 4 should then be switched off after t 0 to satisfy the continuity of inductor currents.
Mode 2 [t1–t2]: From t 1 to t 2 , only S 2 conducts and the other switches are idle. The source voltage of S 2 is Vo . Thus, v L1 and v L2 are both – Vo . i L1 and i L2 decrease with slopes of – Vo / L 1 and – Vo / L 2 , respectively. The current through S 2 ( i S2 ) is the sum of i L1 and i L2 . At the beginning of this mode, the voltage difference between the drain voltage of S 1 ( Vin + Vo ) and the Vo terminal induces capacitor charging current to flow through the auxiliary current path. Assuming that output capacitances of S 3 and S 4 are the same, the voltage difference equally charges the output capacitors of S 3 and S 4 through Vin /2. Simultaneously, v S3 , which was Vo in the former Mode 1, also equally charges the output capacitors of S 3 and S 4 . Given the charging polarities, the overall v S3 and v S4 respectively become (– Vin + Vo )/2 and ( Vin + Vo )/2 in the step-up operation and 0 V and Vin in the step-down operation.
S 2 can be switched on after t 1 and switched off before t 2 . Thus, synchronous rectification and ZVS can be achieved.
Mode 3 [t2–t0']: Between t 2 and t 0 ' , S 3 and S 4 conduct, whereas S 1 and S 2 do not conduct. This mode is added to the conventional SEPIC/ZETA converter to provide an additional power delivery path between input and output. This path enhances the performance of the proposed converter. As v S1 is Vo , v S2 becomes Vin . Therefore, both v L1 and v L2 are Vin Vo , and both v S3 and v S4 are 0 V. i L1 and i L2 have slopes of ( Vin Vo )/ L 1 and ( Vin Vo )/ L 2 , respectively. These slope change values of inductors are considerably smaller than those of inductors in previous modes. Consequently, inductor ripple currents can be considerably reduced. The current through S 3 and S 4 ( iLa ) is the sum of i L1 and i L2 . Therefore, i L1 , i L2 , and iLa have negative slopes during the step-up operation but positive slopes during the step-down operation. S 3 should be switched off before t 0 ' to prevent the reverse short current from the Vo terminal to ground through the auxiliary current path and S 1 .
Reverse ZETA operation waveforms are shown in Fig. 4 .
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ZETA operation waveforms of the proposed converter in (a) step-up and (b) step-down operations.
The negative polarity of i L1 and i L2 indicates reverse power flow in ZETA operation. The principle of the ZETA operation of the proposed converter is similar to that of the SEPIC operation because of the duality between SEPIC and ZETA converters. Therefore, the specific analysis for ZETA operation is omitted in this study.
- C. Conversion Ratio
By using the voltage-time balance principle and assuming 100% power conversion efficiency, we can determine the voltage and current conversion ratios of the proposed converter as
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where Iin and Io refer to input and output currents, respectively; and t S1 and t S2 correspond to the duration of S 1 and S 2 , respectively. Switching duty ratios d 1 and d 2 are given by d 1 = t S1 / T and d 2 = t S2 / T , where T is repeated switching period; d 1 must be larger than d 2 to increase output voltage and vice versa. The power conversion efficiency of the proposed converter increases as d 1 and d 2 become smaller because the low ripple current effect of Mode 3 can be maximized with considerably reduced overall circulation currents. As a result, conduction and switching losses of switches and DC resistive losses of inductors and capacitors can be reduced.
III. DESIGN PARAMETERS
Useful design parameters are presented in this section. La is ignored to simplify the design. To maximize the ripple reduction effect of the proposed converter, d 1 and d 2 should be minimized, whereas d 3 has to be maximized. In this work, d 3 (=1– d 1 d 2 ) denotes the duty ratio of S 3 and S 4 . In SEPIC operation, duty ratios can be determined as
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In ZETA operation, duty ratios are determined by
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where M is voltage conversion ratio defined in (1).
For the proposed converter, inductor ripple current reaches the maximum value between Vind 1 T / L and Vod 2 T / L , where L is L 1 or L 2 . This formula can be also applied to conventional SEPIC converters. However, the ripple value in the proposed converter is smaller than that of the conventional SEPIC converter because of the reduction in d 1 and d 2 . The inflection points of inductor currents, such as i L1 ( t 0 ), i L1 ( t 1 ), i L1 ( t 2 ), i L2 ( t 0 ), i L2 ( t 1 ), and i L2 ( t 2 ) ( Fig. 3 ), are defined as I 1 , I 2 , I 3 , I 4 , I 5 , and I 6 , respectively. These currents are related to one another as follows:
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The average of i L1 is equal to Iin as
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By substituting (4) into (6) and using (1), I 1 is obtained by
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The charge balance of Cs states is as follows:
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Substituting (4) and (5) into (8) and using (1) and (7), I 4 is obtained by
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All other inflection values in (4) and (5) can be determined by using (7) and (9). For the ZETA operation, the same method can be applied to derive the inflection points of inductor currents. Given these values, other design parameters, such as inductor average currents, switch peak and root-mean-square (rms) currents, capacitor ripple voltages, and rms currents, can be determined through simple algebra. Typical capacitor currents of the proposed converter in step-up mode are shown in Fig. 5 , where iCin , iCo , and iCs are currents of Cin , Co , and Cs , respectively. To calculate the capacitor ripple voltage, the capacitor charge can be obtained from the local maximum area enclosed by the capacitor current and time axis, and then divided into its capacitance such as Cin , Co , or Cs . The capacitor ripple voltage can have several different values according to the operating conditions. The major design parameters of the proposed converter are summarized in Table I . The detailed derivations are omitted to save the space in this paper.
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Typical capacitor currents of the proposed converter in step-up mode (a) iCin, (b) iCo, and (c) iCs.
SEVERAL DESIGN PARAMETERS OF THE PROPOSED CONVERTER
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SEVERAL DESIGN PARAMETERS OF THE PROPOSED CONVERTER
IV. ACTUAL CONVERSION RATIO AND EFFICIENCY CONSIDERING RESISTIVE LOSSES
An equivalent circuit for the proposed converter containing resistive elements of inductors and switches is shown in Fig. 6 . r L1 and r L2 represent the equivalent series resistance of L 1 and L 2 , respectively. r S1 , r S2 , r S3 , and r S4 denote the on-state drain-source resistance of S 1 , S 2 , S 3 , and S 4 , respectively. The conversion ratio and efficiency, with the resistive loss elements included, can be determined by using the methodology in [27] . The conversion ratio and efficiency of the proposed converter’s forward SEPIC operation can be derived as follows: Because the average inductor voltage is zero, the average voltage of Cs ( VCs ) is obtained by
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Equivalent circuit of proposed converter containing resistive elements of inductors and switches.
where I L1 and I L2 are the average values of i L1 and i L2 over one switching period, respectively, at steady state. When S 1 is turned on and the others are turned off, the average values of v L1 , v L2 , iCo , and iCs are given by
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where R denotes load resistance. When S 2 is turned on and the others are turned off, the average values of v L1 , v L2 , iCo , and iCs are obtained as
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When S 3 and S 4 are turned on and the others are idle, the average values of v L1 , v L2 , iCo , and iCs are given as
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By applying ampere-time balance on Co and Cs , the following equations are obtained:
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Substituting (12), (15), and (18) into (20), I L1 + I L2 is given by
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Substituting (13), (16), and (19) into (21), I L2 is related with I L1 as follows:
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Substituting (23) into (22), I L1 and I L2 are obtained as
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By using the voltage-time balance principle on L 1 ,
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By substituting (11), (14), (17), (24), and (25) into (26), the actual voltage gain is given by
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Efficiency is obtained by
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The conversion ratio and efficiency of the reverse ZETA operation of the proposed converter can be also derived by using the same procedure as above. The results are summarized, and the actual voltage gain for the ZETA operation is given by
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Efficiency is given as
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The actual conversion ratio and efficiency of the conventional bidirectional SEPIC/ZETA converter can be obtained by removing the auxiliary current paths; thus, d 3 = 0 and d 2 = 1– d 1 . For a forward SEPIC operation of the conventional SEPIC/ZETA converter, the actual voltage conversion ratio is obtained as
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Efficiency is given by
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For a reverse ZETA operation of the conventional SEPIC/ZETA converter, the actual voltage conversion ratio is obtained as
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Efficiency is derived by
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To compare the actual voltage gains between the proposed converter and the conventional bidirectional SEPIC/ZETA converter, the following values of resistance are assumed and substituted into (27), (29), (31), and (33):
  • rL1=rL2=10mΩ,rS1=rS2=rS3=rS4=5mΩ,R=0.9Ω.
The actual voltage gains calculated for the proposed converter and conventional SEPIC/ZETA converter in step-up and step-down modes are shown in Figs. 7 (a) and 7 (b), respectively. In the proposed converter, the selected duty ratio of the synchronous rectifier ( d 2 and d 1 for SEPIC and ZETA operations, respectively) is as small as 0.1 for the step-up mode. For the step-down mode, the selected duty ratio of the main switch ( d 1 for SEPIC operation and d 2 for ZETA operation) is sufficiently small by 0.1. These values are not dependent on the other duty ratios in contrast to the values of the conventional SEPIC/ZETA converter. As a result of such design freedom, the voltage gains of the proposed converter in both the step-up and step-down modes can be higher than those of the conventional SEPIC/ZETA converter at the same duty ratio. The duty ratios d 1 and d 2 can also be widely ranged in the proposed converter than in the conventional one.
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Calculated voltage gains of the proposed converter and the conventional bidirectional SEPIC/ZETA converter in (a) step-up and (b) step-down modes.
The efficiencies of the proposed and conventional bidirectional SEPIC/ZETA converters are calculated, assuming the following parameters:
  • Step-up:rL1=rL2= 10 mW,rS1=rS2=rS3=rS4= 5 mW, voltage conversion from 14 V to 17.3 V
  • Step-down:rL1=rL2= 10 mW,rS1=rS2=rS3=rS4= 5 mW, voltage conversion from 21 V to 17.3 V
Substituting these parameters into (28), (30), (32), and (34), the calculated efficiencies are plotted in Fig. 8 . The proposed converter is more efficient than the conventional SEPIC/ZETA converter, particularly in a higher power range, because it optimized selection of duty ratios is possible with respect to the conversion ratio.
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Calculated efficiencies of the proposed converter and the conventional bidirectional SEPIC/ZETA converter in (a) step-up and (b) step-down modes.
V. SOFT SWITCHING
The proposed converter has been treated as a hard switched type for simple analysis. However, the converter has soft-switching features because of the small inductor La on the auxiliary current path. The soft current commutation aspect of the proposed converter in SEPIC operation mode is shown in Fig. 9 . As mentioned in the analysis of Section II, S 4 is turned off after t 0 at the beginning of Mode 1. During this overlapped time between S 1 and S 4 , the sum of i L1 and i L2 equals the sum of i S1 and iLa . The voltage of La becomes – Vo and i L1 + i L2 can be assumed constant during this short time interval; thus,
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Therefore, S 3 and S 4 are switched off with the current slope of – Vo / La , and S 1 is switched on with the current slope of Vo / La . This soft current commutation takes the time of LaILa ( t 0 )/ Vo ; thus, S 4 should be turned off after this time interval for soft switching. This commutation time should be shorter than the duration of the main switch to achieve ZCS; thus,
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A similar phenomenon occurs at the beginning of Mode 3. After turning on S 3 and S 4 , the sum of inductor currents i L1 + i L2 is distributed to the S 2 and auxiliary current path through S 3 and S 4 . During this commutation time, i L1 + i L2 can be assumed constant and the voltage of La becomes Vin ; therefore,
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S 2 is turned off with the current slope of – Vin / La and thus the diode reverse recovery problem is alleviated. S 3 and S 4 are turned on with the current slope of Vin / La . This commutation process takes the time of LaILa ( t 2 )/ Vin . S 2 should be turned off before t 2 for soft switching. This commutation time should be shorter than the duration of auxiliary switches to achieve ZCS; thus,
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In summary, small inductor La induces soft current commutation between switches on the auxiliary current path and thereby achieves ZCS of all switches. The ZETA operation mode can accomplish the same in the proposed converter. Apart from the ZCS effect, ZVS turn-on and turn-off are also achieved at synchronous rectifiers, which are S 2 in SEPIC and S 1 in ZETA modes, respectively.
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Soft current commutation of the proposed converter in SEPIC operation.
VI. SIMULATIONS AND EXPERIMENTS
A forward SEPIC operation of step-down case (from 21 V to 17.3 V) and a reverse ZETA operation of step-up case (from 14 V to 17.3 V) are simulated to verify the operation of the proposed converter. The electric specifications are as follows: Output power Po = 320 W and switching frequency fs = 100 kHz. To obtain 10% and 50% ripples of i L1 and i L2 , respectively, the inductors are selected by L 1 = L 2 = 30 μH. For the ripple voltages of Cin (⊿ vin ) and Co (⊿ vo ) to reach 1% and that of Cs (⊿ vCs ) to reach 2%, the capacitors are chosen by Cin = 33 μF, Cs = 235 μF, and Co = 440 μF, respectively. These inductors and capacitors are determined by formulas in Table I , with the actual switching duty ratios considered. La is set at 220 nH for the soft current commutation time of 200 ns, with S 1 S 4 = IPP110N20N3 (200 V, 88 A, 10.7 mΩ). In the simulation, a damping resistor of 50 Ω is added parallel to La to attenuate parasitic oscillations occurring from La and the output capacitances of the switches. The simulation results are shown in Fig. 10 . Soft current commutation between the switches and ZCS turn on and/or turn off of switches are observed. With proper gating control, ZVS turn-on and turn-off, and synchronous rectifications are achieved in S 2 and S 1 for SEPIC and ZETA operations, respectively. The inductor current ripples are also highly reduced because the conduction time of the main switch and synchronous rectifier considerably decreased, thereby reducing the DC resistive losses of inductors and capacitors as well as the conduction and switching losses of switches.
A prototype circuit of the proposed converter ( Fig. 11 ) is built to verify the performance of the proposed converter. The electric specifications and circuit component values are the same with simulation. For a fair comparison between the proposed converter and the conventional bidirectional SEPIC/ZETA converter, several experimental waveforms, such as inductor currents ( i L1 , i L2 ), switch currents ( i S1 , i S2 , iLa ), and switch voltages ( v S1 , v S2 , v S3 , v S4 ), are measured under the same electric specifications and circuit parameters. These waveforms are shown in Figs. 12 and 13 for SEPIC step-down operation (from 21 V to 17.3 V) and shown in Figs. 14 and 15 for ZETA step-up operation (from 14 V to 17.3 V). Negative current polarity in ZETA operation indicates reverse power flow. In SEPIC operation, the inductor ripple current of the proposed converter (2.19 A) is reduced by 47% compared with that of the conventional converter (4.14 A). In ZETA operation, the inductor ripple current is reduced by 32% from the conventional SEPIC/ZETA (3.33 A) to the proposed converter (2.25 A). For the proposed converter, soft current commutations between switches are confirmed and all switches achieved good ZCS property. In contrast, the conventional SEPIC/ZETA converter showed hard-switching behavior. Based on the measured switching voltages and currents, the switching and conduction losses of switches are calculated in reference to [26] . The switching loss Psw is given as
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Simulation results of the proposed converter in (a) SEPIC step-down and (b) ZETA step-up operations.
where Won and Woff are energy lost during switching turn-on and turn-off transients, respectively, given by
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where Vp and Ip are the switching peak voltage and current during switching transients, respectively; and ton and toff are the time length of switching turn-on and turn-off transients, respectively. Conduction loss Pcond is given by
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where Is,rms is rms current of switch in Table I , and rs is on state drain-source resistance. Assuming ton and toff are both 50 ns, the switch losses of the proposed and conventional converters are obtained in Table II . As a result, the overall conduction and switching losses of the proposed converter are lower by 41% than those of the conventional SEPIC/ZETA converter.
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Prototype circuit of the proposed converter.
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Measured waveforms of the proposed converter in SEPIC step-down mode (a) iL1 and iL2, (b) iS1, iS2 and iLa, (c) iS1 and vS1, (d) iS2 and vS2, and (e) iLa, vS3, and vS4.
Large voltage spikes are observed at switching turn-off transient in the voltage measurements of both proposed and conventional SEPIC/ZETA converters. The voltage spikes are caused by unclamped parasitic inductances of hardwired connectors in series with switches in prototype circuit that was built in breadboard. To eliminate these voltage spikes, the power stack has to be redesigned to reduce the series inductance, or certain snubber circuits, such as the RC voltage snubber in [28] , are required to suppress them. However, such options are not considered in these experiments because the focus is on the performance comparison between the proposed and conventional converters. Nonetheless, when a properly designed RC voltage snubber is applied to the circuit, the voltage spike during turn-off transient would be effectively reduced, with efficiency dropping below 1%. To measure the switch currents i S1 and i S2 , i S1 + i S2 is used instead of individual i S1 and i S2 . To place a current probe, an artificial wire should be inserted in series with switch. The artificial wire’s small inductance induces unwanted parasitic oscillation with parasitic capacitances of circuit components and causes a high voltage spike during switching turn-off transient. These effects can be avoided by extracting switch currents i S1 and i S2 using the mathematical functions of oscilloscope, such as sum and subtraction, i.e., i S1 + i S2 = i L1 + i L2 iLa . In i S1 + i S2 , i S1 and i S2 are easily distinguished from the current slope change.
CALCULATED SWITCH LOSSES OF THE PROPOSED AND CONVENTIONAL SEPIC/ZETA CONVERTERS ATPO= 320 W
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CALCULATED SWITCH LOSSES OF THE PROPOSED AND CONVENTIONAL SEPIC/ZETA CONVERTERS AT PO = 320 W
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Measured waveforms of the conventional bidirectional SEPIC/ZETA converter in SEPIC step-down mode (a) iL1 and iL2 and (b) iS1, iS2, vS1, and vS2.
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Measured waveforms of the proposed converter in ZETA step-up mode (a) iL1 and iL2, (b) iS1, iS2 and iLa, (c) iS2 and vS2, (d) iS1 and vS1, and (e) iLa, vS3, and vS4.
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Measured waveforms of the conventional bidirectional SEPIC/ZETA converter in ZETA step-up mode (a) iL1 and iL2 and (b) iS1, iS2, vS1, and vS2.
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Measured and calculated efficiencies of the proposed and conventional bidirectional SEPIC/ZETA converters.
The measured efficiencies of the two converters are shown as black lines in Fig. 16 . The average efficiency of the proposed converter is 5% higher than that of the conventional converter. The efficiency difference between the two converters is proportional to output power because of the increased conduction and switching losses of the circuit components in high current range. The thermal design for heat radiation of the switches and inductors is not considered in this prototype circuit because of laboratory limitations. The efficiency curve rapidly decreases in values in the high power range. Assuming that a proper thermal design is implemented and thus efficiency degradation from thermal-related issues are nonexistent, the ideal efficiency curve can be expected through loss analysis, including switching and conduction losses of switches and DC resistive losses of inductors. Switch losses can be calculated using (39), (40), and (41). DC resistive losses of inductors, PL , are determined by
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where IL,rms is rms current of inductor in Table I and rL is DC resistance of inductors of 5 mΩ, shown as gray lines in Fig. 16 . At Po = 650 W, the ideal calculated efficiency of the proposed converter is 3.5% higher than measured one.
VII. CONCLUSIONS
A new non-isolated bidirectional soft switching SEPIC/ZETA converter that can reduce ripple currents in inductors is studied. The proposed converter has the following advantages:
  • 1) Inductor currents have reduced ripple because the conduction time of the main switch and synchronous rectifier is reduced.
  • 2) ZCS turn-on and/or turn-off are achieved in all switches with soft current commutation among them.
  • 3) Synchronous rectification and ZVS turn-on and turn-off are achieved in the synchronous rectifier.
  • 4) Voltage gains in both step-up and step-down modes can be higher than those of conventional bidirectional SEPIC/ZETA converter because of the optimized duty ratios of switches. As a result, conduction and switching losses in circuit components were considerably reduced. Lower current rated switches can be also utilized, and the filter size can be minimized. The experimental results of the prototype circuit shows that the operation waveforms and soft-switching properties well agree with theoretical analysis and simulation results. Measured inductor ripple currents are reduced by 40%, and the overall efficiency of the proposed converter is 5% higher than the conventional bidirectional SEPIC/ZETA converter, demonstrating the effectiveness of the proposed converter.
BIO
Min-Sup Song received his B.S., M.S., and Ph.D. in Electrical Engineering from Pohang University of Science and Technology, Pohang, Korea in 2005, 2007, and 2011, respectively. He is currently a Senior Research Engineer at Samsung Electro-Mechanics, Suwon, Korea. His research interests include power conversion and power control systems.
Young-Dong Son received his B.S. and M.S. degrees in Mechanical Engineering from Chonnam National University, Gwang-Ju, Korea in 2002 and 2006, respectively. He is currently a Senior Research Engineer at Samsung Electro-Mechanics, Suwon, Korea. His research interests are power electronics and electric machine control systems.
Kwang-Hyun Lee received his B.S. and M.S. degrees in Electrical Engineering from Ulsan University, Ulsan, Korea in 2009 and 2011, respectively. Since 2011, he has been with Samsung Electro-Mechanics as an Assistant Research Engineer. His research interests include the design and control of motors, as well as electric vehicle propulsion.
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