Advanced
Design and Analysis of an Interleaved Boundary Conduction Mode (BCM) Buck PFC Converter
Design and Analysis of an Interleaved Boundary Conduction Mode (BCM) Buck PFC Converter
Journal of Power Electronics. 2014. Jul, 14(4): 641-648
Copyright © 2014, The Korean Institute Of Power Electronics
  • Received : January 30, 2014
  • Accepted : April 25, 2014
  • Published : July 28, 2014
Download
PDF
e-PUB
PubReader
PPT
Export by style
Share
Article
Author
Metrics
Cited by
TagCloud
About the Authors
Hangseok Choi
hangseok.choi@fairchildsemi.com

Abstract
This paper presents the design considerations and analysis for an interleaved boundary conduction mode power factor correction buck converter. A thorough analysis of the harmonic content of the AC line current is presented to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing efficiency. The results of the harmonic analysis are used to derive the required value of K and therefore the output voltage necessary to meet the class D requirements for a given AC line voltage. The discussed design consideration and harmonic current analysis are verified on a 300W universal line experimental prototype converter with an 80V output. The measured efficiencies remain above 96% down to 20% of the full load. The input current harmonics also meet the IEC61000-3-2 (class D) standard.
Keywords
I. INTRODUCTION
Typically the power supplies used in computing, networking and telecom systems operate at below 50% of their rated power due to redundancy in design. Even the power supplies used in personal computers, which do not have redundancy in design, rarely operate at their rated capacity. Environmental concerns about the efficiency of power conversion circuits under their actual operating conditions have prompted the creations of minimum efficiency requirements through a number of government energy efficiency standards and specifications.
Specifically, the U.S. Environmental Protection Agency’s (EPA) Energy Star and the European Code of Conduct (CoC) specifications have defined the minimum average efficiencies at 100%, 75%, 50% and 25% of full load [1] , [2] . The 80 PLUS initiative certifies computer power supply products that meet efficiency requirements at 100%, 50% and 20% of rated load [3] as summarized in Table I . Some advanced specifications, such as 80 PLUS Titanium, have already included 10% load efficiency requirements [3] and it is very likely that other specifications will be affected.
For universal input applications that require power factor correction (PFC) in the front end to meet input current harmonic regulations such as IEC61000-3-2, maintaining a high efficiency over the entire load and line range has been a major design challenge. This is due to the fact that the preferred boost topology for PFC typically exhibits a 1%–3% lower efficiency at low line when compared to that of high line since a large input current causes severe conduction losses in the switch and bridge rectifier diode. The high output voltage of a boost converter, which is typically in the 380-400 V range, also has an unfavorable effect on the switching losses and electro-magnetic interference (EMI) of down-stream DC-DC converters.
These drawbacks of boost PFC pre-regulators can be overcome by using a buck converter for the PFC. This allows for high efficiency across the entire line range while reducing the switching losses and EMI of down-stream DC-DC converters. The buck PFC converter operation was first described in [4] . Detailed comparative analyses between buck PFC and its boost counterpart have shown that buck PFC features a higher efficiency at low line and exhibits lower common mode (CM) EMI [5] , [6] . Detailed analyses and improvements on the control method have been discussed to maximize efficiency while complying with harmonic current limits [6] - [18] . The clamp current buck PFC proposed in [6] , [7] simplified the control of the continuous conduction mode (CCM) buck PFC which is suitable for cost sensitive applications. The boundary conduction mode (BCM) operation of buck PFC and its analysis were presented in [8] , which simplified the control and improved the efficiency by eliminating the reverse recovery loss of the freewheeling diode. However, the BCM approach exhibits a relatively large pulsating input current whose peak is twice its CCM counterpart and inevitably necessitates a larger differential mode (DM) EMI filter in the input side. This offsets the benefits of the BCM approach and the practical power level has been limited to below 150W. Another shortcoming of BCM operation is that its switching frequency becomes extremely high, especially for high line and light load conditions. This causes detrimental effect on the efficiency at the light load condition.
EFFICIENCY REQUIREMENT FOR 80 PLUS CERTIFICATION
PPT Slide
Lager Image
EFFICIENCY REQUIREMENT FOR 80 PLUS CERTIFICATION
The limitations of BCM operation can be overcome by using the interleaving technique. This reduces the input current ripple and, consequently, the size of the EMI filter extending their practical power level to above 150W. In addition, the output current ripple can be also significantly reduced by ripple cancellation resulting in a longer life time of the output capacitor. Another benefit of interleaving is that the light load efficiency can be improved by shedding one of the parallel connected converters under the light load condition, which is known as phase management. By shedding one converter, the power that the remaining converter should handle becomes doubled allowing the switching frequency to be halved. This technique is very effective in improving light load efficiency at the high line condition by reducing the switching loss.
While interleaving converters with a fixed switching frequency is relatively easy, interleaving BCM converters is challenging since the switching frequency continuously varies with the instantaneous line voltage and output load conditions [9] - [10] . In general, interleaving techniques can be classified into two categories: the open loop master-slave method ( [11] - [12] ) and the PLL based closed loop method ( [13] - [17] ). The open loop master-slave method has difficulty in guaranteeing stable BCM operation against tolerance of the inductor values and PWM control circuits. Once the BCM operation is lost, the converter operates in CCM and the input current is significantly distorted. The closed loop method can guarantee BCM operation of each converter regardless of the tolerance of the inductor value and PWM control circuits. However, the closed loop method responds to phase shift disturbances relatively slowly and it takes several tens of switching cycles to correct these disturbances. To alleviate the problem of the PLL based closed loop method, the cross-coupled master-slave method was proposed, which responds to disturbances very fast and guarantees a stable interleaving operation against any transient or disturbance ( [18] - [20] ).
This paper presents a thorough analysis of the interleaved BCM buck PFC converter along with a design optimization to meet the IEC61000-3-2 class D harmonic limits while maximizing efficiency.
II. LINE CURRENT DISTORTION ANALYSIS
The cross-coupled master slave interleaving method was originally proposed for BCM boost PFC in [21] , [22] . However, it can be utilized better when applied to BCM buck PFC since BCM buck converters inherently have abrupt operation transition around the line current zero crossing. Fig. 1 and Fig. 2 show a circuit diagram of the interleaved BCM buck PFC converter and its key waveforms. As can be seen in Fig. 2 , a constant ON time is provided from the PFC controller, where the ON time is maintained constant for at least one half a mains cycle to achieve PFC functionality. The turn-on instant of the gate drive signal of the BCM buck converter is determined by the inductor current zero current detection (ZCD). However, while the instantaneous line voltage is smaller than the output voltage, the ZCD is lost since there is no inductor current. Then, the turn-on instant is typically determined by a clock signal given by the internal reset timer of the PFC controller. This introduces a sudden change in the switching frequency when BCM operation is resumed as the instantaneous line voltage rises above the output voltage.
PPT Slide
Lager Image
Interleaved BCM buck PFC converter.
When the instantaneous line voltage is smaller than the output voltage, the buck PFC draws no current from the AC mains since the bridge rectifier is reverse-biased. This introduces a dead angle ( θ Z ) to the line current at around the line zero crossing, as shown in Fig. 2 . The dead angle increases the total harmonic distortion (THD) and lowers the power factor. The dead angle is related to the ratio between the output voltage and the line voltage amplitude as:
PPT Slide
Lager Image
PPT Slide
Lager Image
Interleaved BCM buck PFC converter and key waveforms.
where: K =
PPT Slide
Lager Image
With the constant ON time given by the BCM PFC controller, the inductor peak current of a single PFC converter is proportional to the difference between the instantaneous line voltage and the output voltage. Then, the average inductor current that is locally averaged over the corresponding switching period can be obtained as:
PPT Slide
Lager Image
With a given ON time, the output power of a single PFC converter can be obtained as:
PPT Slide
Lager Image
By rearranging (3), the ON time with a given output power can be obtained as:
PPT Slide
Lager Image
From the power balance between the input and the output it can be seen that:
PPT Slide
Lager Image
The average MOSFET current of a single converter that is locally averaged over the corresponding switching period is obtained as:
PPT Slide
Lager Image
The line current of the interleaved PFC converter which is twice the locally averaged MOSFET current is plotted in Fig. 3 with a given line voltage and output power for different values of K. Note that the input current is normalized to the current when K=0.2. As K increases the dead angle increases while the line current changes from a “U” shape to a crossover distorted sine shape. The line current also exhibits a higher peak as K increases.
To examine the impact of K on harmonic distortion, the current amplitude of the n-th order harmonic is calculated as:
PPT Slide
Lager Image
The amplitude of the current of the n-th order harmonic as a percentage of that of the fundamental current is given as:
PPT Slide
Lager Image
Since the even harmonics are all zero, only the odd harmonics are numerically calculated and plotted in Fig. 4 , Fig. 5 and Fig. 6 as percentages of the fundamental current for different values of K along with the IEC61000-3-2 class D limit. The original class D specification is a combination of the relative limit proportional to the input power and the absolute limit. To simply compare the specifications with the harmonics expressed as a percentage of the fundamental current, the class D harmonic specification is scaled to a percentage of the fundamental current under the 600W condition by multiplying the original relative limit by 230.
Fig. 4 shows that the 3 rd through the 11 th order harmonics are all below their limits when K is smaller than 0.83. Fig. 5 shows that the 13 th through the 23 rd order harmonics all meet their limits when K is smaller than 0.88. Fig. 6 shows that the 25 th through the 39 th order harmonics all comply to their limits regardless of K . It follows from Fig. 4 , Fig. 5 and Fig. 6 that the BCM buck PFC converter employing constant ON time control can meet the IEC61000-3-2 class D harmonic current limit with K smaller than 0.83. For the universal line voltage (90 - 265V AC ), the output voltage can be set as high as 105V, while meeting the Japanese specification corresponding to the IEC61000-3-2 class D limit.
All of the harmonic current analysis done in this section is valid only for BCM operation where the switching frequency varies with the load and instantaneous line voltage. It is worth examining the frequency variation since the BCM buck converter operates in the DCM and does not conduct the PFC function properly when the switching frequency reaches the maximum that the controller allows.
PPT Slide
Lager Image
Input current waveform with different voltage ratio K for a given load condition (Normalized to the input current when K=0.2).
PPT Slide
Lager Image
Harmonic currents and their class-D limit for different K values (3rd through 11th).
The switching frequency to maintain the BCM operation can be obtained as:
PPT Slide
Lager Image
PPT Slide
Lager Image
Harmonic currents and their class-D limit for different K values (13rd through 23rd).
PPT Slide
Lager Image
Harmonic currents and their class-D limit for different K values (25th through 39th).
Fig. 7 shows how the switching frequency varies with the load and instantaneous line voltage by using (9) where the inductor is 100 μH and the output power per converter is 150 W. As observed, the switching frequency is extremely high under the light load condition especially for high line. To maintain a high efficiency under that condition, it is necessary to limit the switching frequency or to employ power management which shuts down one converter under light load so that the power that the remaining converter should handle is doubled halving the switching frequency.
PPT Slide
Lager Image
Switching frequency variation for different line voltage and load condition (POUT=150W per converter, L=100 μH).
III. POWER STAGE DESIGN CONSIDERATIONS
To identify the optimal output voltage of the BCM buck PFC converter to maximize the efficiency, several currents that mainly contribute to the losses are analyzed in this section. The equivalent RMS value of the MOSFET current of a single buck PFC converter over the corresponding switching period can be obtained as:
PPT Slide
Lager Image
where D(θ) is the duty cycle ratio at a given angle θ defined as:
PPT Slide
Lager Image
By root-mean-squaring (10) over half of a line cycle, the RMS value of the MOSFET current of a single buck PFC converter can be obtained as:
PPT Slide
Lager Image
The average line current of a single PFC converter is given as:
PPT Slide
Lager Image
The average diode current of a single buck PFC converter is obtained as:
PPT Slide
Lager Image
Fig. 8 shows how the RMS current of the MOSFET varies with the output voltage and line voltages by using (12). It follow that the conduction loss at high line is reduced as the output voltage increases. However, the MOSFET conduction loss at the minimum line voltage of the universal range has its minimum when the output voltage is around 80V. Meanwhile, setting the output voltage higher than 80V results in severe conduction loss in the MOSFET at low line. It should be noted that the MOSFET RMS current of the buck PFC is significantly larger than that its boost counterpart. Therefore, optimal selection of the output voltage is critical to maximize the efficiency.
PPT Slide
Lager Image
RMS value of MOSFET current of a single buck PFC converter as a function of output voltage for different line voltages (POUT=150W)
PPT Slide
Lager Image
Average line current of a single buck PFC converter as a function of output voltage for different line voltages (POUT=150W)
Fig. 9 shows how the average line current varies with the output voltage and line voltages using (13). It can be observed that the average line current is smaller than that of the boost counterpart and decreases as the output voltage increases. It follows that the conduction loss in the bridge rectifier is smaller than that of the boost counterpart. Fig. 10 plots the average freewheeling diode current variation for different output and line voltages using (14). It can be observed that the average freewheeling diode current is larger than that of the boost counterpart and decreases as the output voltage increases. Since the average input current is much larger than the average freewheeling diode current and two diodes are involved in the conduction path of the bridge rectifier, the buck PFC has significantly lower conduction losses in the diodes than that of its boost counterpart in spite of the increased conduction loss of the freewheeling diode.
In summary, the conduction losses of the diodes can be minimized as the output voltage increases while the conduction loss of the MOSFET at the minimum line voltage has its minimum value when the output voltage is around 80V.
PPT Slide
Lager Image
Average freewheeling diode current of a single buck PFC converter as a function of output voltage for different line voltages (POUT=150W).
IV. EXPERIMENTAL RESULTS
An interleaved BCM buck PFC prototype converter with 300 W of output power and a universal input range has been built using a BCM PFC controller (FAN9611), which was originally developed for interleaved BCM boost PFC converters [21] , [22] . The output voltage is set at 80V so that the power dissipation of the MOSFET can be minimized. With a high voltage NPN transistor (Q3), a high voltage current source is implemented to level-shift the output voltage information to ground the referenced FB pin of the FNA9611. The schematic along with its key components is shown in Fig. 11 . Fig. 12 and Fig. 13 show the key interleaving waveforms for the full load condition at 115V AC . Fig. 14 shows the key interleaving waveforms for the full load condition at 230V AC . To show the input current ripple cancellation by interleaving, the zoomed waveforms of Fig. 12 at around the peak of the line voltage are shown in Fig. 15 . As can be observed, the ripple frequency of the sum of the two switch currents is doubled while the peak to peak of the ripple current is the same as that of one converter handling half of the output power.
PPT Slide
Lager Image
Schematic of prototype converter.
PPT Slide
Lager Image
Operation Waveforms at low line (POUT=300W, VIN=115VAC).
PPT Slide
Lager Image
Inductor Waveforms at low line (POUT=300W, VIN=115VAC).
PPT Slide
Lager Image
Operation Waveforms at high line (POUT=300W, VIN=230VAC).
PPT Slide
Lager Image
Current ripple cancellation by interleaving.
Fig. 16 and 17 show the steady state operation waveforms under full load with 115 V AC and 230 V AC line input voltages, respectively. The measured waveform shows good agreement with the corresponding calculated line current waveform of Fig. 5 . The line current is slightly distorted due to the circulating current through the line filter capacitor which leads the line voltage. The effect of the circulating current is more notable at high line where the input power is lower while the circulating current is larger than that of low line.
PPT Slide
Lager Image
Line voltage and current waveforms (POUT=300W, VIN=115VAC).
PPT Slide
Lager Image
Line voltage and current waveforms (POUT=300W, VIN=230VAC).
Fig. 18 shows how the efficiency varies with the line voltage for different load conditions. The measured efficiencies remain above 96% down to 25% of full load. Even at 10% of the full load condition, the efficiency remains above 94% across the entire line range due to the built-in phase management function of the FAN9611, which is designed to shut down one converter when the load drops below 15% of the full load. Without the phase management, the efficiency at a 10% load drops down to 90% at high line due to the high switching frequency. Fig. 19 shows the line current harmonics along with the IEC61000-3-2 (class D) standard, which shows a good agreement with the calculated harmonics shown in Fig. 4 , Fig. 5 and Fig. 6 while meeting the IEC61000-3-2 specification. Fig. 20 shows the measured power factor. This shows that a high power factor above 96% is achieved under a full load for the entire line range with the proposed method.
PPT Slide
Lager Image
Measured efficiency .
PPT Slide
Lager Image
Measured line current harmonics and EN61000 class D limit.
PPT Slide
Lager Image
Measured power factor.
V. CONCLUSIONS
This paper discussed the design consideration and conducted an in depth analysis for an interleaved boundary conduction mode power factor correction buck converter to examine the allowable voltage gain (K value) for meeting the EN61000-3-2, Class D standard while maximizing the efficiency. By interleaving two parallel connected buck converters, the input current ripple is halved while the ripple frequency is doubled, which leads to a smaller line filter. The smaller capacitor in the line filter also results in a smaller displacement factor of the line current which improves the power factor. The discussion about the optimal design meeting both the harmonic regulation and high efficiency was verified on a 300W, universal line experimental prototype with an 80V output. It exhibits a high efficiency above 96% down to 20% of the full load. Even at 10% of the full load, a high efficiency above 94% is achieved over the entire line range due to the phase management.
BIO
Hangseok Choi received his B.S., M.S., and Ph.D. degrees in Electrical Engineering from Seoul National University, Seoul, Korea, in 1996, 1999, and 2002, respectively. From 2002 to 2007, he was a System and Application Engineer at Fairchild Semiconductor, Bucheon, Korea. Since 2008, he has been a Principal System and Application Engineer at Fairchild Semiconductor, Bedford, NH, USA, where he is presently developing high-performance power management ICs. He has authored or coauthored more than 50 technical papers and holds 31 U.S. patents. His current research interests include the analysis, simulation, and design of high-frequency, high-power-density power converters.
References
Environmental Protection Agency (EPA) (2008) Energy Star Program Requirements for Single Voltage External AC–DC and AC–AC Power Supplies. [Online]. Available:
European Commission. (2004) Code of Conduct on Energy Efficiency of External Power Supplies. [Online]. Available:
80 Plus specification. [Online]. Available:
Endo H. , Yamashita T. , Sugiura T. 1992 “A high-power-factor buck converter,” in Proc. IEEE Power Electronics Specialist Conf. (PESC) 1071 - 1076
Yang J. , Zhang J. , Xinke W. , Qian Z. , Xu M. 2010 “Performance comparison between buck and boost CRM PFC converter,” in Proc. IEEE Control and Modeling for Power Electronics (COMPEL) 1 - 5
Huber L. , Liu G. , Jovanovic M.M. 2010 “Design-oriented analysis and performance evaluation of buck PFC front end,” IEEE Trans. Power Electron. 25 (1) 85 - 94    DOI : 10.1109/TPEL.2009.2024667
Jang Y. , Jovanovic M. M. 2010 “Bridgeless buck PFC rectifier,” in Proc. IEEE Applied Power Electronics Conf. (APEC) 23 - 29
Wu X. , Yang J. , Zhang J. , Xu M. 2011 “Design considerations of soft-switched buck pfc converter with constant on-time (COT) control,” IEEE Trans. Power Electron. 26 (11) 3144 - 3152    DOI : 10.1109/TPEL.2011.2145391
Nussbaumer T. , Raggl K. , Kolar J.W. 2009 “Design guidelines for interleaved single-phase boost PFC circuits,” IEEE Trans. Ind. Electron. 56 (7) 2559 - 2573    DOI : 10.1109/TIE.2009.2020073
Lee P. , Lee Y. , Cheng D. K. W. , Liu X. 2000 “Steady-state analysis of an interleaved boost converter with coupled inductors,” IEEE Trans. Ind. Electron. 47 (4) 787 - 795    DOI : 10.1109/41.857959
Huber L. , Irving B. T. , Jovanović M. M. 2008 “Open-loop control methods for interleaved DCM/CCM boundary boost PFC converters,” IEEE Trans. Power Electron. 23 (4) 1649 - 1657    DOI : 10.1109/TPEL.2008.924611
Ku C. , Chen D. , Huang C. , Liu C. 2011 “A novel SFVM-M control scheme for interleaved CCM/DCM boundary-mode boost converter in PFC applications,” IEEE Trans. Power Electron. 26 (8) 2295 - 2303    DOI : 10.1109/TPEL.2010.2096544
Ishii T. , Mizutani Y. 1999 “Variable frequency switching of synchronized interleaved switching converters,” U.S. Patent No. 5, 905,369
Elmore M. S. 1996 “Input current ripple cancellation in synchronized, parallel connected critically continuous boost converters,” in Proc. IEEE Applied Power Electronics Conf. (APEC) 152 - 158
Lu B. 2008 “A novel control method for interleaved transition mode PFC,” in Proc. IEEE Applied Power Electronics Conf. (APEC) 697 - 701
Huber L. , Irving B. T. , Jovanović M. M. 2009 “Closed-loop control methods for interleaved DCM/CCM boundary boost PFC converters,” in Proc. IEEE Applied Power Electronics Conf. (APEC) 991 - 997
Huber L. , Irving B. T. , Jovanović M. M. 2009 “Review and stability analysis of PLL-based interleaving control of DCM/CCM boundary boost PFC converters,” IEEE Trans. Power Electron. 24 (8) 1992 - 1999    DOI : 10.1109/TPEL.2009.2018560
Choi H. 2010 “Novel cross-coupled master-slave method for interleaved boundary conduction mode (BCM) PFC converters,” in Proc. IEEE Applied Power Electronics Conf. (APEC) 36 - 41
Choi H. , Balogh L. 2012 “A cross-coupled master-slave interleaving method for boundary conduction mode (BCM) PFC converters,” IEEE Trans. Power Electron. 27 (10) 4202 - 4211    DOI : 10.1109/TPEL.2012.2190426
Bridge C. , Balogh L. 2011 “Synchronizing frequency and phase of multiple variable frequency power converters,” U.S. patent, No. 7,933,132
Fairchild Semiconductor. FAN9611 Datasheet. [Online].
Fairchild Semiconductor. FAN9611 Application Note. [Online].