This paper presents a new cascaded asymmetrical single phase multilevel converter with a lower number of power semiconductor switches and isolated DC sources. Therefore, the number of power electronic devices, converter losses, size, and cost are reduced. The proposed multilevel converter topology consists of two Hbridges connected in cascaded configuration. One Hbridge operates at a high frequency (high frequency inverter) and is capable of developing a two level output while the other Hbridge operates at the fundamental frequency (low frequency inverter) and is capable of developing a multilevel output. The addition of each power electronic switch to the low frequency inverter increases the number of levels by four. This paper also introduces a hybrid switching algorithm which uses very simple arithmetic and logical operations. The simplified hybrid switching algorithm is generalized for any number of levels. The proposed simplified switching algorithm is developed using a TMS320F2812 DSP board. The operation and performance of the proposed multilevel converter are verified by simulations using MATLAB/SIMULINK and experimental results.
I. INTRODUCTION
In recent years, the demand for green energy has been heading towards a huge distribution of electric generators driven by solar, wind, fuel cell, hydro, and other renewable energy sources. This tendency will extend throughout the subsequent years because the power produced by renewable sources is expected to satisfy 30% and 60% of the comprehensive needs in the years 2020 and 2050, respectively.
An important consequence of this circumstance is the need to replace the present electric power system, which consists of a low number of very high power ac generators, to a scattered one, which has a huge number of small to medium power ac and dc generators supplied by renewable energy sources connected to the grid through power electronic converters.
This new development introduces various political, financial, and technical challenges because it alters the way in which the electrical energy resources (generation, transmission and distribution) are designed and controlled. From the technical perspective, the use of power electronic converters creates new issues, including increased complexity, increased power losses, electromagnetic interferences (EMIs) and reduced power quality, thus reducing the overall efficiency and stability.
Hence, numerous researchers have put their efforts in proposing new inverter configurations or in altering the existing ones, to improve the quality of the power available at the inverter terminals. Among the various inverter topologies, pulse width modulated (PWM) multilevel inverters (MLIs) are very popular
[1]
. In the beginning, they were used mainly in highvoltage highpower applications since the applied voltage is distributed among a number of cascaded power devices, thus overcoming their voltage limits
[2]

[7]
. As their output voltage is staircase in nature, they are better than twolevel PWM inverters in terms of total harmonic distortion (THD), without the use of hefty, costly and dissipative passive filters. Therefore, in recent times, MLIs have been recommended in the field of renewable energies, including photovoltaic (PV) and fuel cell (FC) generators
[8]

[10]
.
There are three fundamental MLI configurations: neutral point clamped, flying capacitor MLIs, and cascaded Hbridge MLIs (CHBMLI). The neutral point clamped and flying capacitor MLIs require only one DC source to develop a multilevel output whereas the CHBMLI requires more than one isolated DC source. The CHBMLI cannot be used when a single dc source is available. However, this drawback becomes a very attractive feature in the case of PV or FC systems, because solar cells or fuel cell stacks can be assembled in a number of separate generators.
A significant problem in multilevel converter design is the complexity of their control and pulse width modulator. Many authors have proposed diverse solutions (e.g.,
[11]

[35]
). Generally if the number of output voltage levels is increased, then the number of power electronic devices and the number of isolated DC sources are also increased. This makes a CHB inverter even more complex.
In the case of the converters for PV and FC generators, another important issue is the achievement of maximum power point tracking (MPPT). DCDC converters are mandatory for each of the isolated DC sources in a PV or FC application. These converters adjust the variable or low quality output voltage of PV or FC stacks. In addition, the power output of PV and FC stacks has to be maximized as it depends on ecological factors. Therefore, in order to track the maximum power point of the photovoltaic string or fuel cell stacks, additional voltage and current sensors are required for each DCDC converter. These additional sensors further increase the system complexity.
In this paper, a multilevel inverter with a minimum number of power electronic switching devices is proposed. It is a modified version of a multilevel inverter using the series/parallel conversion of DC sources (MLISPC) developed in
[15]
. In the proposed multilevel inverter, an auxiliary circuit comprising of four diodes and a switch is introduced instead of the series/parallel switches of the inverter found in the MLISPC. However, only two isolated voltage sources are needed to output the same number of voltage levels when compared to conventional CHB inverters and the MLISPC.
The number of switching devices used and the harmonics of the output voltage waveform for the proposed inverter are reduced when compared to the conventional methods. The proposed multilevel inverter topology can be extended for the application of grid connected photo voltaic systems, hybrid electric vehicles, etc. Theoretical analysis, numerical simulations and experimental results are presented to demonstrate the validity of the proposed cascaded asymmetrical single phase multilevel converter.
Section II describes the circuit topology of the proposed multilevel inverter. In Section III, the generalized PWM modulation technique of the proposed inverter is explained. In Section IV, the converter losses are discussed. Sections V and VI validate the simulation and experimental results.
II. CIRCUIT TOPOLOGY
Fig. 1
shows the circuit configuration of the proposed cascaded Hbridge multilevel inverter with two Hbridge inverters connected in cascade (upper and lower Hbridge inverters). The DC voltage sources
v_{dco}

v_{dcn}
may either be independent or dependent on each other. The magnitude of each voltage source in the lower Hbridge is two times the magnitude of the upper Hbridge voltage source (i.e. =
v_{dcn}
/
v_{dc0}
= 2). The lower Hbridge of the MLISPC is replaced with the one developed in
[13]
,
[14]
,
[16]
,
[17]
. As shown in
Fig. 1
, in the lower Hbridge, an auxiliary circuit comprising of four diodes and a switch placed between two DC sources.
Proposed cascaded Hbridge multilevel inverter.
Using the proposed circuit configuration, the lower Hbridge inverter outputs V
_{low}
= 2n+1 levels, while the upper Hbridge outputs V
_{up}
= v
_{dc0}
. The proposed inverter outputs 4n + 3 levels by V
_{low}
+ V
_{up}
or V
_{low}
V
_{up}
. Here, n is the number of capacitor sources in the lower Hbridge inverter.
Fig. 2
shows the lower Hbridge inverter with two capacitor sources, which outputs five levels. The switching states of the five level inverter (lower Hbridge) are shown in the
Table I
.
Operation of lower inverter.
SWITCHING STATES OF LOWER HBRIDGE INVERTER
SWITCHING STATES OF LOWER HBRIDGE INVERTER
Table II
gives the complete switching states and the derived output of the proposed multilevel inverter to generate 11 levels. The modes of operation indicated in
Table II
correspond to the modes pointed out in
Fig. 4
. In
Table II
, the symbol ↔ indicates that the voltage level switches between two extremes.
SWITCHING STATES OF PROPOSED INVERTER
SWITCHING STATES OF PROPOSED INVERTER
Modulation strategy of the proposed inverter.
Reference waveform generation for an 11 level inverter (upper bridge).
 A. Capacitor Voltage Balancing
Since the main application of the proposed inverter is fed from a photovoltaic (PV) array or fuel cell (FC) stacks, DCDC boost converters are required to boost the low output voltage of the PV panels or FC stacks. Hence, two boost converters are used, one for the upper Hbridge inverter and the other for the lower Hbridge inverter. For the lower inverter, the Multi Output Boost (MOB) DCDC converter proposed in
[36]
is used. One of the most interesting applications of this MOB DCDC converter is the boosting and regulation of the low and variable output voltage of renewable energy for the DC link of grid connected systems, based on multilevel inverters
[2]
. Hence, the MOB DCDC converter serves the following two purposes:

1) Boosting the low output voltage of the PV array or FC stacks to a desired value.

2) Balancing of the DC link capacitors.
The proposed inverter, fed from a multi output DCDC converter, is shown in
Fig 5
.
Proposed cascaded HBridge multilevel inverter fed from multi output boost converter.
III. GENERALIZED PWM MODULATION TECHNIQUE
This section determines the switching function to get the output of the eleven levels in the proposed inverter. The same procedure can be extended to derive the switching function of an N level inverter. A hybrid PWM modulation technique is used to generate the PWM switching signals
[19]
.
Fig 3
shows the PWM Modulation scheme of the proposed 11 level inverter. The total reference waveform is generated as shown in
Fig. 4
(a) and defined in (1).
Where A is the peak value of the reference waveform. (A = 5 for 11 level inverter). The above equation is scaled down as given in (2).
The reference waveform for the upper inverter is generated by using the following expressions:
Equation (3) is a simple zero crossing detector, while (4) gives the expected output of the lower Hbridge inverter (Vlow) and (5) is a mathematical representation of the upper Hbridge inverter reference waveform. The output of equations (4) and (5) for the 11 level inverter are shown in
Fig. 4
(b) and
Fig. 4
(c). The above equations can be used for higher inverter levels by simply changing the value of A. For example, A = 7 for 15 levels, A = 9 for 19 levels, A = 11 for 23 levels just to mention a few. In order to generate the switching patterns for the lower inverter, the first step is to generate the reference waveform for the lower inverter.
The next step is to split the above reference wave into many signals of R
_{y}
.
Where y = 1 to X. After dividing the reference of the lower inverter into many subsignals, it is necessary to find out the number of auxiliary switches required for an N level inverter.
The main switches of the lower inverter are switched as per the equations given below:
Where y = X, + denotes the logical OR operation and * denotes the multiplication of the signals. The auxiliary switches of the lower inverter can be switched as per the algorithm given below.
1) Step 1:
Form a set:
2) Step 2:
Write the permutation P on R as given below:
3) Step 3:
Remove the last column in the above permutation P
_{1}
and rewrite as:
4) Step 4:
From the above equation, it is very easy to derive the switching pulses for all of the auxiliary switches of the N level inverter. The first and last columns of the above matrix are responsible for developing the switching patterns for the first and last auxiliary switches and the equations for AS
_{1}
and AS
_{n}
are:
Where ⊕ denotes the XOR operation. Similarly, the 2
^{nd}
column from the first and 2
^{nd}
columns from the last of the permutation matrix P
_{1}
are responsible for developing the switching patterns of AS
_{2}
and AS
_{(n1)}
and the equations are:
The above procedure can be repeated to generate the switching patterns for any pair of auxiliary switches based on the following cases.
CASE I (If P
_{1}
contains an odd number of columns): Sometimes as in the case of a 19 level inverter, when X = 4, the number of R signals available will be four (i.e.) R
_{1}
; R
_{2}
; R
_{3}
and R
_{4}
. The number of auxiliary switches in the 19 level inverter will be three. As per the algorithm, the permutation P1 will be:
The first and last columns of the above P1 will be responsible for constructing the switching patterns for AS
_{1}
and AS
_{3}
. However, for developing the switching pattern for AS
_{2}
, only the center column of the permutation P1 should be used. The switching pattern for
AS_{2}
can be developed as:
The possibility of CASE I is also valid for N = 11, 19, 27, 35, 43....
CASE II (If P
_{1}
contains an even number of columns): In the case of a 23 level inverter, when X = 5, the number of R signals available will be five (i.e.) R
_{1}
, R
_{2}
, R
_{3}
, R
_{4}
and R
_{5}
whereas the number of auxiliary switches in the 23 Level inverter will be four. As per the algorithm, the permutation P1 will be:
The first and last columns of the above P
_{1}
will be responsible for constructing the switching patterns for AS
_{1}
and AS
_{4}
, and the 2nd and 3rd columns are used for developing the switching pattern for AS
_{2}
and AS
_{3}
. Columns 2 and 3 have only three unique R signals (i.e.) R
_{2}
, R
_{3}
and R
_{4}
to develop the switching patterns for AS2 and AS3.
The possibility of CASE II is also valid for N = 15, 23,31, 39, 47 etc. The modulation index M
_{a}
of the proposed N level inverter is defined as:
Where
Where A
_{pr}
represents the peak value of the modulating or reference wave and A
_{pc}
represents the peak to peak value of the carrier (triangular) wave. The main switches MS
_{1}
and MS
_{3}
are switched by comparing the reference waveform R
_{01}
with the carrier wave. As a result, the voltage V
_{xz}
between points x and z in
Fig. 1
appears as shown in
Fig. 3
. The main switches MS
_{2}
and MS
_{4}
are switched by comparing the reference waveform R
_{02}
with the carrier wave. As a result, the voltage V
_{yz}
between points y and z in
Fig. 1
appears as shown in
Fig. 3
. The main switches of the lower bridge inverter MS
_{5}
 MS
_{8}
are switched as per equations (10)(13) and auxiliary switch AS
_{1}
is switched as per the above proposed algorithm, as shown in
Fig. 3
. The proposed generalized algorithm is very simple since it makes use of simple logical operations.
IV. CONVERTER LOSSES
The average switching power loss P
_{sloss}
in the switch during the transition of switch is given by:
Where t
_{c(on)}
and t
_{c(off)}
are the turn on and turn off cross over intervals, respectively; V
_{DS}
is the voltage across the switch and I
_{dc}
is the current which flows through the switch. For the sake of clarity, the proposed topology with 15 levels is compared with familiar, similar topologies. For simplification, the proposed topology and the wellknown inverter topologies are assumed to operate at the same turnon and turnoff crossover intervals and at the same
I_{dc}
. Then, the average switching power loss
P_{sloss}
is proportional to V
_{DS}
and
f_{s}
.
The number of primary devices required for generating 15 levels in the proposed inverter is 10 and the voltage across these switches is V
_{DC}
for the upper Hbridge switches (4 numbers), 6V
_{DC}
for the lower Hbridge switches (4 numbers) and 4V
_{DC}
for the auxiliary switches (2 numbers). The upper Hbridge inverter switches at a high frequency f
_{s}
, the lower Hbridge inverter switches at the fundamental frequency fm and the auxiliary devices switch twice at the fundamental frequency (2fm). Therefore, the switching losses of the proposed inverter can be written as:
Similarly, the number of primary devices required for generating 15 levels in the MLISPC inverter is 14 and the voltage across these switches is V
_{DC}
for the upper Hbridge switches (4numbers), 6V
_{DC}
for the lower Hbridge switches (4 numbers) and 2V
_{DC}
for the series/parallel switches (6 numbers). The upper Hbridge inverter switches at a high frequency f
_{s}
, the lower Hbridge inverter switches at the fundamental frequency fm and the series/parallel switches switch twice at the fundamental frequency (2f
_{m}
). Therefore, the switching losses of the proposed inverter can be obtained as:
Likewise, for conventional symmetrical CHB inverters, the switching losses can be calculated as:
For an asymmetrical cascaded H bridge inverter with 1:2:4 configurations, the switching losses can be obtained as:
Since f
_{s}
≫ f
_{m}
and from equations (27)(32), it is evident that among the various familiar topologies, the proposed topology has the lowest switching losses when compared to the other topologies. In the proposed inverter, at any point in time, the number of switches in conduction is only 4 (2 from the upper inverter and 2 from the lower inverter). Therefore, the conduction losses
P_{closs}
of the proposed inverter are:
Where R
_{ON}
is the internal resistance of the switching device and I is the current flowing into the devices. In the case of the MLISPC topology, the number of conducting devices increases as the number of levels increases. This in turn, increases the conduction losses. The same is true for all of the wellknown topologies. Hence, the conduction losses are lower in the case of the proposed topology when compared to the MLISPC, the conventional symmetrical CHB and asymmetrical CHB inverters.
V. SIMULATION RESULTS
To validate the proposed inverter topology, simulations are carried out for the proposed inverter in Matlab/Simulink. The algorithm discussed in Section III is implemented in the simulations up to 43 levels and it can be extended to any required level. The conditions set for simulation and experiment are same.
Table III
gives the simulation parameters for 11, 15 and 43 level inverters. The upper inverter is operated at a high switching rate that is equivalent to the carrier frequency (i.e. 10 kHz), while the lower inverter is operated at a low frequency (nearly equal to the fundamental frequency i.e. 50Hz).
Fig. 6
shows the simulation results for the load voltage of the 11 level inverter together with the upper and lower inverter voltages for a modulation index of M
_{a}
= 1. When the modulation index is reduced from 1, the number of voltage levels at the load also decreases.
Fig. 7
shows the output across the load and the upper and lower inverters for the modulation index M
_{a}
= 0.8 (i.e. when the value of A = 4). From
Fig. 6
and
Fig.7
it is observed that when the modulation index is reduced from 1 to 0.8, the output voltage across the load has only nine levels. Any further reduction in the modulation index will reduce the number of voltage levels at the load end. For example, when
M_{a}
= 0.6 i.e. A = 3 the number of levels obtained at the load voltage is seven, when
M_{a}
= 0.4 i.e. A = 2 the voltage level at the load becomes five and so on.
Fig. 8
shows the resultant waveforms of a 15 level inverter along with the upper and lower inverter waveforms for a modulation index of Ma= 1 (i.e. A = 7). Any further decrease in the value of A leads to a reduction in the output voltage levels. For example, when A =5, it generates an 11 level output as shown in
Fig. 6
.
Fig. 9
shows the simulation results of a 43 level inverter along with the upper and lower inverters, in which the load voltage is very close to sinusoidal.
Table IV
gives the details of the total harmonic distortion at the load voltage and current for various output voltage levels.
SIMULATION PARAMETERS
(a) Voltage across the load (11 Levels). (b) Voltage across the upper inverter V_{up}. (c) Voltage across the lower inverter V_{low}. (d) Load Current waveform for modulation index M_{a}=1.
(a) Voltage across the load (9 Levels). (b) Voltage across the upper inverter V_{up}. (c) Voltage across the lower inverter V_{low}. (d) Load Current waveform for modulation index Ma=0.8.
(a) Voltage across the load (15 Levels). (b) Voltage across the upper inverter V_{up}. (c) Voltage across the lower inverter V_{low}. (d) Load Current waveform for modulation index M_{a}=1.
(a) Voltage across the load (43 Levels A = 21). (b) Voltage across the upper inverter V_{up}. (c) Voltage across the lower inverter V_{low}. (d) Load Current waveform for modulation index M_{a}=1.
THD FOR VOLTAGE AND CURRENT FOR VARIOUS LEVELS
THD FOR VOLTAGE AND CURRENT FOR VARIOUS LEVELS
VI. EXPERIMENTAL RESULTS
Fig. 10
shows a schematic diagram for the hardware setup of the proposed inverter, developed in the laboratory, for 15 levels. The upper and lower inverters consist of MKI 8006T6K series IGBTs. The auxiliary switch used in the lower inverter is a FIO5012BD bidirectional device. The gate driving signal is developed by using a TMS320F2812 Texas instruments DSP. The programs for the TMS320F2812 DSP are composed with code composer studio and Matlab/Simulink.
Fig. 11
shows the experimental results of a 15 level inverter with a modulation index of 1 and a switching frequency of 10 KHz. The prototype inverter is made to drive an RL load with the values of R and L indicated in
Table III
.
Schematic diagram for the hardware Setup of the proposed inverter (15 Levels).
Hardware results (a)Voltage across the lower inverter V_{low} (b)Voltage across the upper inverter V_{up} (c) Voltage across the load (15 Levels) (d) Load Current waveform for modulation index M_{a}=1.
Fig. 12
shows the hardware results of a 15 level inverter with and without a filter. The values of the LC filter used in the hardware prototype are similar to those of the simulation environment. A study very similar to the simulation is done in the hardware prototype for various modulation indices.
Fig. 13
shows the experimental results of a 15 level inverter when the modulation index is reduced to 0.7 (i.e. when A = 5), which leads to an 11 level output at the load terminals.
Hardware results (a) Voltage across the load (15 Levels) with out filter (b) With LC filter.
Hardware results When 15 level inverter is driven by M_{a}=0.7.(a)Voltage across the upper inverter V_{up} (b) Voltage across the lower inverter V_{low} (c) Voltage across the load (11 Levels) (d) Load Current waveform.
Fig. 13
includes the waveforms of the upper and lower inverter along with the load current waveform for
M_{a}
= 0.7.
Fig. 14
shows the hardware results of a 15 level inverter when driven by a modulation index of 0.4, which leads to a 7 level output at the load terminals.
Fig. 15
presents the total harmonic distortion content of the voltage, current and power obtained from the hardware prototype along with the load voltage for a 15 level inverter when driven with a modulation index of 0.4, which leads to a 7 level output. As indicated in
Table IV
, the THD values obtained from the simulation and the results obtained from the hardware prototype match well for a 7 level inverter without a filter. In order to study the performance of the proposed inverter, the inductive load is varied over a wide range.
Fig. 16
and
Fig. 17
show the load voltage and current waveforms of the proposed inverter for various power factors. It is evident from the load profile waveforms that the proposed inverter is also capable of supplying power to a highly inductive load.
Hardware results When 15 level inverter is driven by M_{a}=0.4.(a)Voltage across the load (7 Levels) (b) Voltage across the lower inverter V_{low}(c) Voltage across the upper inverter V_{up} (d) Load Current waveform
Harmonic Spectrum of 15 level inverter when drive by M_{a}=0.4.(a)Numerical Values of Voltage, Current and Power THD (b)Inverter load voltage (7 Level output).
Load voltage and current waveform for power factor of 0.9837.
Load voltage and current waveform for power factor of 0.6198.
In order to validate the proposed multilevel inverter fed from a multi output DCDC boost converter, a step change in the reference values of the lower DC link capacitors were given at 0.5 secs (i.e. a change from 50 Volts to 100 Volts). Similarly a step change in the upper boost converter is given at 0.5 secs (i.e. from 25 Volts to 50 Volts) in order to maintain the ratio between the lower and upper inverter DC link voltages as two.
Fig 18
shows the experimental waveforms of the upper and lower capacitor voltages due to a step change in their reference values (i.e. the upper capacitor voltage is changed from 25 Volts to 50 Volts and the lower capacitor voltages are changed from 50Volts to 100 Volts).
Fig 19
shows the corresponding changes in the upper inverter and lower inverter voltages along with the load voltage.
Step response in Capacitor voltages of lower inverter along with load voltageobtained from the simulation and the results obtained from thehardware prototype match well for a 7 level inverter withoutfilter.
Step response in capacitor voltages of upper and lower inverter along with upper, lower and load voltage waveform.
VII. CONCLUSIONS
Multilevel inverters offer enhanced output waveforms with a minimum of THD. This paper presents a novel single phase multilevel inverter with reduced switching devices and isolated DC sources. Simulations are carried out in MATLAB/Simulink and the proposed inverter is implemented in real time using a DSP board. A generalized switching algorithm which can be used for any number of levels is also presented. The performance of the suggested novel multilevel inverter is investigated in detail. Modulation waveforms and harmonic analyses are presented for various values of the modulation indices. By properly adjusting the modulation index, the required number of levels for the inverter output voltage can be achieved. The simulation and experimental results match perfectly with each other. The proposed inverter system offers the advantage of a reduced number of switching devices and isolated DC sources when compared to the conventional CHB and MLISCP for the same number of output levels. In addition, the high frequency switching devices are operated at a low voltage and the low frequency devices are operated at a high voltage. Thus, it can be concluded that the proposed novel multilevel inverter can be used for medium and high power applications.
BIO
Kaliamoorthy Mylsamy received his B E in Electrical and Electronics Engineering at Madras University, Chennai, India, in 1999, and his M.Tech degree in Electrical Drives and Control from Pondicherry University, Puducherry, India, in 2006. He was a gold medalist for the academic years 20042006. He has one decade of teaching experience for under graduate and post graduate students of electrical and electronics engineering. He is presently working as an Associate Professor in the Department of Electrical and Electronics Engineering, PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India. His current research interests include alternative energy sources, fuel cells, energy conversion, multilevel inverters, analysis and control of power electronics devices, power quality and active harmonic analysis. For further details please visit www.kaliasgoldmedal.yolasite.com
Rajasekaran Vairamani was born in Madurai, Tamil Nadu, India, in 1971. He received his B.E degree in Electrical and Electronics Engineering, ME . degree in Power Systems, and his Ph.D. degree from Madurai Kamaraj University, Madurai, Tamil Nadu, India, in 1994, 1997 and 2007, respectively. He is presently heading the Electrical and Electronics Department, PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India. He is a certified Energy Auditor. His current research interests include power systems, energy, power quality and power electronics energy.
Gerald Christopher Raj Irudayaraj was born on January 7, 1977. He received his B.E., in Electrical and Electronics Engineering from Madurai Kamaraj University, Madurai, Tamil Nadu, India, in 1999, and his M.E. and Ph.D. degrees in Power Electronics and Drives from Anna University, Chennai, Tamil Nadu, India, in 2006 and 2013, respectively. He is presently working as an Associate Professor in the Department of Electrical and Electronics Engineering, PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India. His current research interests include power electronics and drives, current source inverters, AC drives and applications.
Hubert Tony Raj Lawrence received his B.E degree in Electrical and Electronics Engineering from the FX Engineering College, Thirunelveli, Tamil Nadu, India, in 2011, and his M.E degree in Power Electronics and Drives from the PSNA College of Engineering and Technology, Dindigul, Tamil Nadu, India, in 2013. At present he is working as Assistant Professor in the Department of Electrical and Electronics Engineering, Christian College of Engineering and Technology, Ottanchatram, Tamil Nadu, India. His current research interests include multilevel inverters and induction motor drives. He has a particular interest in the study of power electronics for real time applications.
Govindaraju C.
,
Baskaran K.
2010
“Efficient hybrid carrier based space vector modulation for a cascaded multilevel inverter,”
Journal of Power Electronics
10
(3)
277 
284
DOI : 10.6113/JPE.2010.10.3.277
Aghdam M. G. H.
,
Fathi S. H.
,
Gharehpetian G. B.
2008
“Harmonic optimization techniques in multilevel voltagesource inverter with unequal DC sources,”
Journal of Power Electronics
8
(2)
171 
180
Babaei E.
,
Dehqan A.
,
Sabahi M.
2013
“Improvement of the performance of the cascaded multilevel inverters using power cells with two series legs,”
Journal of Power Electronics
13
(2)
223 
231
DOI : 10.6113/JPE.2013.13.2.223
Zhang Y.
,
Adam G. P.
,
Lim T. C.
,
Finney S. J.
,
Williams B. W.
2012
“Mathematical analysis and experiment validation of modular multilevel converters,”
Journal of Power Electronics
12
(1)
33 
39
DOI : 10.6113/JPE.2012.12.1.33
Menshawi M. K.
,
Mekhilef S.
2013
“Multistage inverters control using surface hysteresis comparators,”
Journal of Power Electronics
13
(1)
59 
69
DOI : 10.6113/JPE.2013.13.1.59
Nguyen N.V.
,
Quach H.T.
,
Lee H.H.
2012
“Novel singlestate PWM technique for commonmode voltage elimination in multilevel inverters,”
Journal of Power Electronics
12
(4)
548 
558
DOI : 10.6113/JPE.2012.12.4.548
Park Y.M.
,
Ryu H.S.
,
Lee H.W.
,
Jung M.G.
,
Lee S.H.
2010
“Design of a cascaded hbridge multilevel inverter based on power electronics building blocks and control for highperformance,”
Journal of Power Electronics
10
(3)
262 
269
DOI : 10.6113/JPE.2010.10.3.262
Kim H.
2009
“Filter design for gridconnected singlephase inverters,”
Journal of Power Electronics
9
(4)
623 
630
Oh S.J.
,
Sunwoo M.H.
2009
“Variable structure PWM controller for highly efficient PV inverters,”
Journal of Power Electronics
9
(6)
866 
873
Kim H.
,
Sul S.K.
2011
“A novel filter design for output LC filters of PWM inverters,”
Journal of Power Electronics
11
(1)
74 
80
DOI : 10.6113/JPE.2011.11.1.074
Babaei E.
2011
“Charge balance control methods for a class of fundamental frequency modulated asymmetric cascaded multilevel inverters,”
Journal of Power Electronics
11
(6)
811 
818
DOI : 10.6113/JPE.2011.11.6.811
Besery E.
,
Arifoglu B.
,
Camur S.
,
Beser E. K.
2010
”Design and application of a single phase multilevel inverter suitable for using as a voltage harmonic source,”
Journal of Power Electronics
10
(2)
138 
145
DOI : 10.6113/JPE.2010.10.2.138
Agelidis V. G.
,
Baker D. M.
,
Lawrance W. B.
,
Nayar C. V.
1997
“A multilevel PWM inverter topology for photovoltaic applications,”
inProc. the IEEE International Symposium on Industrial Electronics (ISIE’97)
2
(6)
589 
594
Ceglia G.
,
Guzmn V.
,
Snchez C.
,
Ibez F.
,
Walter J.
,
Gimnez M. I.
2006
“A new simplified multilevel inverter topology for DCAC conversion,”
IEEE Trans. Power. Electron.
21
(5)
1311 
1319
DOI : 10.1109/TPEL.2006.880303
Hinago Y.
,
Koizumi H.
2010
“A singlephase multilevel inverter using switched series/parallel DC voltage sources,”
IEEE Trans. Ind. Electron.
57
(8)
2643 
2650
DOI : 10.1109/TIE.2009.2030204
Rahim N. A.
,
Selvaraj J.
2010
“Multi string fivelevel inverter with novel PWM control scheme for PV application,”
IEEE Trans. Ind. Electron.
57
(6)
2111 
2123
DOI : 10.1109/TIE.2009.2034683
Park S.J.
,
Kang F.S.
,
Lee M. H.
,
Kim C.U.
2003
“A new singlephase fivelevel PWM inverter employing a deadbeat control scheme,”
IEEE Trans. Power Electron.
18
(3)
831 
843
DOI : 10.1109/TPEL.2003.810837
Dehghan S. M.
,
Diany M. M.
,
Yazdian A.
2010
“Currenttype nineswitch inverters,”
Journal of Power Electronics
10
(2)
146 
154
DOI : 10.6113/JPE.2010.10.2.146
Zhang J.
,
Zou Y.
,
Zhang M.
,
Ding K.
2001
”Study on a modified cascade inverter with hybrid modulation,”
4th IEEE International Conference on Power Electronics and Drive Systems
1
379 
383
Dixon J.
,
Moran L.
2006
“Highlevel multi step inverter optimization using a minimum number of power transistors,”
IEEE Trans. Power Electron
21
(2)
330 
337
DOI : 10.1109/TPEL.2005.869745
Nho N. V.
,
Hai Q. T.
,
Lee H.H.
2010
“Carrier based singlestate PWM technique for minimizing vector errors in multilevel inverters,”
Journal of Power Electronics
10
(4)
357 
364
DOI : 10.6113/JPE.2010.10.4.357
Gupta K. K.
,
Jain S.
2013
“Multilevel inverter topology based on series connected switched sources,”
IET Power Electronics
6
(1)
164 
174
DOI : 10.1049/ietpel.2012.0209
Nho N. V.
,
Youn M. J.
2005
“A unified carrier based PWM method in multilevel inverters,”
Journal of Power Electronics
5
(2)
142 
150
Rahim N. A.
,
Chaniago K.
,
Selvaraj J.
2011
“Singlephase sevenlevel gridconnected inverter for photovoltaic system,”
IEEE Trans. Ind. Electron.
58
(6)
2435 
2443
DOI : 10.1109/TIE.2010.2064278
Salehi R.
,
Farokhnia N.
,
Abedi M.
,
Fathi S. H.
2011
“Elimination of low order harmonics in multilevel inverters using genetic algorithm,”
Journal of Power Electronics
11
(2)
132 
139
DOI : 10.6113/JPE.2011.11.2.132
Du S.
,
Liu J.
,
Lin J.
2012
“Legbalancing control of the DClink voltage for modular multilevel converters,”
Journal of Power Electronics
12
(5)
739 
747
DOI : 10.6113/JPE.2012.12.5.739
Sha D.
,
Guo Z.
,
Deng K.
,
Liao X. H.
2012
“Parallel connected high frequency AC Link inverters based on full digital control,”
Journal of Power Electronics
12
(4)
595 
603
DOI : 10.6113/JPE.2012.12.4.595
Kangarlu M. F.
,
Babaei E.
,
Sabah M.
2013
“Cascaded crossswitched multilevel inverter in symmetric and asymmetric conditions,”
IET Power Electronics
6
(6)
1041 
1050
DOI : 10.1049/ietpel.2012.0563
Zhang Y.
,
Adam G.
,
Finney S.
,
Williams B.
2013
“Improved pulsewidth modulation and capacitor voltagebalancing strategy for a scalable hybrid cascaded multilevel converter,”
IET Power Electronics
6
(4)
783 
797
DOI : 10.1049/ietpel.2012.0403
Ding K.
,
Cheng K. W. E.
,
Zou Y. P.
2012
“Analysis of an asymmetric modulation method for cascaded multilevel inverters,”
IET Power Electronics
5
(1)
74 
85
DOI : 10.1049/ietpel.2010.0370
De S.
,
Banerjee D.
,
Siva kumar K.
,
Gopakumar K.
,
Ramchand R.
,
Patel C.
2011
“Multilevel inverters for lowpower application,”
IET Power Electronics
4
(4)
384 
392
DOI : 10.1049/ietpel.2010.0027
AbuRub H.
,
Holtz J.
,
Rodriguez J.
,
Baoming G.
2010
“Mediumvoltage multilevel converters – State of the art, challenges, and requirements in industrial applications,”
IEEE Trans. Ind. Electron.
57
(8)
2581 
2596
DOI : 10.1109/TIE.2010.2043039
Dey A.
,
Rajeevan P. P.
,
Ramchand R.
,
Mathew K.
,
Gopakumar K.
2013
“A spacevectorbased hysteresis current controller for a general nlevel inverterfed drive with nearly constant switching frequency control,”
IEEE Trans. Ind. Electron.
60
(5)
1989 
1998
DOI : 10.1109/TIE.2012.2200217
Rahim N. A.
,
Elias M. F. M.
,
Hew W. P.
2013
“Transistorclamped Hbridge based cascaded multilevel inverter with new method of capacitor voltage balancing,”
IEEE Trans. Ind.Electron.
60
(8)
2943 
2956
Boora A. A.
,
Nami A.
,
Zare F.
,
Ghosh A.
,
Blaabjerg F.
2010
“Voltage sharing converter to supply single phase asymmetrical four level diode clamped inverter with high power factor loads,”
IEEE Trans. Power Electron.
25
(10)
2507 
2520
DOI : 10.1109/TPEL.2010.2046651